This patch is about the DA-C2 and RB-C2. Chip with install processor

Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly
defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied to
them are almost the same.

Issues:
1. I really dont know what their nicknames are (Shanghai C2 or something).
2. About the mc_patch_01000086.h, I dont know if it is allowed to be released.
   If you really need it, please contact AMD Inc to see if it is public.
3. My RB-C2 is Socket type AM3, which needs DDR3 support. Probably your RB-C2
   doesnt need DDR3. If it does and you really need it, please contack AMD Inc
   to see if it is allowed to release DDR3 code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index a2ee0cac942fbdb53f75ba9c82741757ee36a2f0..65290089f1c76c1c2bd4be2c720561b50878e025 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -290,7 +290,7 @@ static const struct {
 
        /* errata 346 - Fam10 C2
         *  System software should set F3x188[22] to 1b. */
-       { 3, 0x188, AMD_RB_C2, AMD_PTYPE_ALL,
+       { 3, 0x188, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
          0x00400000, 0x00400000 },
 
        /* L3 Control Register */
@@ -317,82 +317,82 @@ static const struct {
 
        /* Errata 344 - Fam10 C2
         * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
-       { 0x60, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x60, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x61, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x61, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x62, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x62, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x63, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x63, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x64, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x64, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x65, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x65, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x66, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x66, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x67, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x67, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x68, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x68, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       { 0x70, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x70, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x71, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x71, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x72, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x72, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x73, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x73, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x74, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x74, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x75, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x75, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x76, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x76, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x77, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x77, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x78, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x78, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
        /* Errata 354 - Fam10 C2
         * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
-       { 0x40, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x40, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x41, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x41, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x42, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x42, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x43, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x43, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x44, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x44, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x45, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x45, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x46, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x46, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x47, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x47, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x48, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x48, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       { 0x50, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x50, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x51, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x51, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x52, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x52, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x53, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x53, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x54, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x54, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x55, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x55, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x56, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x56, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x57, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x57, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x58, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
        /* Errata 327 - Fam10 C2
@@ -400,15 +400,15 @@ static const struct {
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
         * Link Phy Impedance Register[RttIndex]
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
-       { 0xC0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xC0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
-       { 0xD0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xD0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
 
-       { 0x520A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x520A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
-       { 0x530A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x530A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
        { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,

diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index f996247d8dffbedd9a9d45a4c9a9f21f5ee5713e..ff38c653779d0f6413c32e89e276a8d8e9cabde4 100644 (file)
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -44,6 +44,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
  * 00100F2Ah (DR-BA)     1020h                  01000096h
  * 00100F22h (DR-B2)     1022h                  01000095h
  * 00100F23h (DR-B3)     1022h                  01000095h
+ * 00100F42h (RB-C2)     1041h                  01000086h
  * 00100F62h (DA-C2)     1062h                  0100009Fh
  */
 
@@ -67,6 +68,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
                0x100f2A, 0x1020,
                0x100f22, 0x1022,
                0x100f23, 0x1022,
+               0x100f42, 0x1041,
                0x100f62, 0x1062,
        };
 

diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 618f344d234d3aa138672caf1bf59b53a789debd..7bd6d4e4e75a56b09583982d0b11699ac925aece 100644 (file)
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -149,9 +149,12 @@ u32 mctGetLogicalCPUID(u32 Node)
        case 0x10023:
                ret = AMD_DR_B3;
                break;
-       case 0x10062:
+       case 0x10042:
                ret = AMD_RB_C2;
                break;
+       case 0x10062:
+               ret = AMD_DA_C2;
+               break;
        default:
                /* FIXME: mabe we should die() here. */
                print_err("FIXME! CPU Version unknown or not supported! \n");

diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 5afb0a3c1d5350d13f6945521dc0d0ec3ca6e711..004e4cf50d3d8f5dada8130a7dc674800d51c871 100644 (file)
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -41,6 +41,7 @@
 #define        AMD_DR_BA       0x00400000      /* Barcelona BA */
 #define        AMD_DR_B3       0x00800000      /* Barcelona B3 */
 #define        AMD_RB_C2       0x01000000      /* Shanghai C2 */
+#define        AMD_DA_C2       0x02000000      /* XXXX C2 */
 
 /*
  * Groups - Create as many as you wish, from the above public values

diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 1ec8d4ede803905e532dfad3a85887510e79695b..54ee28f8d5c6b5a16d489b03bd72c8bb99325097 100644 (file)
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -394,7 +394,7 @@ void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
 
 void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 {
-       if (pDCTstatA->LogicalCPUID & AMD_RB_C2) {
+       if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2)) {
                vErrata350(pMCTstat, pDCTstatA);
        }
 }