void console_init(void)
{
struct console_driver *driver;
- if(get_option(&console_loglevel, "debug_level"))
- console_loglevel=DEFAULT_CONSOLE_LOGLEVEL;
-
+
+ if (get_option("debug_level", &console_loglevel))
+ console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+
for(driver = console_drivers; driver < econsole_drivers; driver++) {
if (!driver->init)
continue;
#include <smp/spinlock.h>
#include <console/console.h>
-/* printk's without a loglevel use this.. */
-#define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */
-
-/* We show everything that is MORE important than this.. */
-#define MINIMUM_CONSOLE_LOGLEVEL 1 /* Minimum loglevel we let people use */
-
/* Keep together for sysctl support */
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
-int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL;
-int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL;
-int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+unsigned int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
void display(char*);
extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
static void ttyS0_init(void)
{
static const unsigned char div[8]={1,2,3,6,12,24,48,96};
- int b_index=0;
+ unsigned int b_index=0;
unsigned int divisor=TTYS0_DIV;
- if(get_option(&b_index,"baud_rate")==0) {
+ if(!get_option("baud_rate", &b_index)) {
divisor=div[b_index];
}
uart8250_init(TTYS0_BASE, divisor, TTYS0_LCS);
#include <cpu/amd/amdk8_sysconf.h>
static int first_time = 1;
-static int disable_siblings = !CONFIG_LOGICAL_CPUS;
+static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS;
#include "dualcore_id.c"
unsigned nb_cfg_54;
int bsp_apic_id = lapicid(); // bsp apicid
- get_option(&disable_siblings, "dual_core");
+ get_option("dual_core", &disable_siblings);
//get the nodes number
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
- get_option(&disable_siblings, "dual_core");
+ get_option("dual_core", &disable_siblings);
}
result = cpuid(0x80000008);
/* See how many sibling cpus we have */
struct mtrr_state mtrr_state;
device_t f1_dev, f2_dev, f3_dev;
- int enable_scrubbing;
+ uint32_t enable_scrubbing;
uint32_t dcl;
f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1));
/* See if we scrubbing should be enabled */
enable_scrubbing = 1;
- get_option(&enable_scrubbing, "hw_scrubber");
+ get_option("hw_scrubber", &enable_scrubbing);
/* Enable cache scrubbing at the lowest possible rate */
if (enable_scrubbing) {
u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
- get_option(&disable_siblings, "quad_core");
+ get_option("quad_core", &disable_siblings);
siblings = get_max_siblings(sysconf.nodes);
#include <smp/spinlock.h>
static int first_time = 1;
-static int disable_siblings = !CONFIG_LOGICAL_CPUS;
+static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS;
void intel_sibling_init(device_t cpu)
{
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
- get_option(&disable_siblings, "hyper_threading");
+ get_option("hyper_threading", &disable_siblings);
}
result = cpuid(1);
/* Is hyperthreading supported */
extern struct console_driver console_drivers[];
extern struct console_driver econsole_drivers[];
-extern int console_loglevel;
+extern unsigned int console_loglevel;
int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
#if !defined(ASSEMBLY)
void rtc_init(int invalid);
-#if USE_OPTION_TABLE == 1
-int get_option(void *dest, char *name);
-#else
-static inline int get_option(void *dest, char *name) { return -2; }
-#endif
+
+int get_option(char *name, unsigned int *value);
+int set_option(char *name, unsigned int value);
#endif
#endif /* PC80_MC146818RTC_H */
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
- 728 256 h 0 user_data
+ 728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
432 8 h 0 boot_countdown
#440 4 e 9 slow_cpu
444 1 e 1 nmi
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
-728 256 h 0 user_data
+728 256 r 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory1
}
iommu = 1;
- get_option(&iommu, "iommu");
+ get_option("iommu", &iommu);
if (iommu) {
/* Add a Gart apeture resource */
unsigned nb_cfg_54;
unsigned siblings;
int cores_found;
- int disable_siblings;
+ uint32_t disable_siblings;
unsigned ApicIdCoreIdSize;
nb_cfg_54 = 0;
disable_siblings = !CONFIG_LOGICAL_CPUS;
#if CONFIG_LOGICAL_CPUS == 1
- get_option(&disable_siblings, "quad_core");
+ get_option("quad_core", &disable_siblings);
#endif
// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it
}
iommu = 1;
- get_option(&iommu, "iommu");
+ get_option("iommu", &iommu);
if (iommu) {
/* Add a Gart apeture resource */
unsigned nb_cfg_54;
unsigned siblings;
int e0_later_single_core;
- int disable_siblings;
+ uint32_t disable_siblings;
nb_cfg_54 = 0;
sysconf.enabled_apic_ext_id = 0;
disable_siblings = !CONFIG_LOGICAL_CPUS;
#if CONFIG_LOGICAL_CPUS == 1
- get_option(&disable_siblings, "dual_core");
+ get_option("dual_core", &disable_siblings);
#endif
// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
#if USE_OPTION_TABLE == 1
-/* This routine returns the value of the requested bits
- input bit = bit count from the beginning of the cmos image
- length = number of bits to include in the value
- ret = a character pointer to where the value is to be returned
- output the value placed in ret
- returns 0 = successful, -1 = an error occurred
-*/
-static int get_cmos_value(unsigned long bit, unsigned long length, void *vret)
+/*
+ * Functions to save/return values stored in the 256byte cmos.
+ *
+ * To be able to use space maximally we want to only store as many bits as
+ * needed, and not be limited by byte boundaries. We therefor clamp the size
+ * down to an unsigned int. Since the values that we are allowed to touch are
+ * either an enum or a hexadecimal value, this size should suit most purposes.
+ *
+ * These two functions are doing bitshifting, and are therefor a bit
+ * nontrivial. To understand these operations, first read the ones outside the
+ * loop. The ones inside the loop are just adding i to the same calculations,
+ * with the shift twice inverted, as negative shifts aren't nice.
+ */
+static unsigned int
+get_cmos_value(int bit, int length)
{
- unsigned char *ret;
- unsigned long byte,byte_bit;
- unsigned long i;
- unsigned char uchar;
-
- /* The table is checked when it is built to ensure all
- values are valid. */
- ret = vret;
- byte=bit/8; /* find the byte where the data starts */
- byte_bit=bit%8; /* find the bit in the byte where the data starts */
- if(length<9) { /* one byte or less */
- uchar = cmos_read(byte); /* load the byte */
- uchar >>= byte_bit; /* shift the bits to byte align */
- /* clear unspecified bits */
- ret[0] = uchar & ((1 << length) -1);
- }
- else { /* more that one byte so transfer the whole bytes */
- for(i=0;length;i++,length-=8,byte++) {
- /* load the byte */
- ret[i]=cmos_read(byte);
- }
+ unsigned int tmp;
+ int i;
+
+ /* negative left shift --> right shift */
+ tmp = cmos_read(bit / 8) >> (bit % 8);
+
+ for (i = 1; (8 * i) < ((bit % 8) + length); i++)
+ tmp |= cmos_read((bit / 8) + i) << ((8 * i) - (bit % 8));
+
+ /* 1 << 32 - 1 isn't cool inside an int */
+ if (length != 32)
+ tmp &= (1 << length) - 1;
+
+ return tmp;
+}
+
+static void
+set_cmos_value(int bit, int length, unsigned int value)
+{
+ unsigned int mask;
+ unsigned char cmos;
+ int i;
+
+ /* 1 << 32 - 1 isn't cool inside an int */
+ if (length != 32)
+ mask = (1 << length) - 1;
+ else
+ mask = -1;
+
+ value &= mask;
+
+ /* negative right shifts --> left shifts */
+ cmos = cmos_read(bit / 8);
+ cmos &= ~(mask << (bit % 8));
+ cmos |= value << (bit % 8);
+ cmos_write(cmos, bit / 8);
+
+ for (i = 1; (8 * i) < ((bit % 8) + length); i++) {
+ cmos = cmos_read((bit / 8) + i);
+ cmos &= ~(mask >> ((8 * i) - (bit % 8)));
+ cmos |= value >> ((8 * i) - (bit % 8));
+ cmos_write(cmos, (bit / 8) + i);
}
- return 0;
}
-int get_option(void *dest, char *name)
+int
+get_option(char *name, unsigned int *value)
{
extern struct cmos_option_table option_table;
struct cmos_option_table *ct;
/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
-
+
/* find the requested entry record */
ct=&option_table;
ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
printk_err("ERROR: No cmos option '%s'\n", name);
return(-2);
}
-
- if(get_cmos_value(ce->bit, ce->length, dest))
- return(-3);
+
+ if (ce->length > 32) {
+ printk_err("ERROR: cmos option '%s' is too large.\n", name);
+ return -3;
+ }
+
+
+ *value = get_cmos_value(ce->bit, ce->length);
+
if(!rtc_checksum_valid(LB_CKS_RANGE_START,
- LB_CKS_RANGE_END,LB_CKS_LOC))
+ LB_CKS_RANGE_END,LB_CKS_LOC))
return(-4);
return(0);
}
+
+int
+set_option(char *name, unsigned int value)
+{
+ extern struct cmos_option_table option_table;
+ struct cmos_option_table *ct;
+ struct cmos_entries *ce;
+ size_t namelen;
+ int found = 0;
+
+ /* Figure out how long name is */
+ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
+
+ /* find the requested entry record */
+ ct = &option_table;
+ ce = (struct cmos_entries*) ((unsigned char *) ct + ct->header_length);
+
+ for(;ce->tag==LB_TAG_OPTION;
+ ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ if (memcmp(ce->name, name, namelen) == 0) {
+ found=1;
+ break;
+ }
+ }
+
+ if (!found) {
+ printk_err("ERROR: Unknown cmos option '%s'\n", name);
+ return(-2);
+ }
+
+ if (ce->length > 32) {
+ printk_err("ERROR: cmos option '%s' is too large.\n", name);
+ return -3;
+ }
+
+ set_cmos_value(ce->bit, ce->length, value);
+
+ /* We should not update the checksum here. */
+
+ return 0;
+}
+#else
+int
+get_option(char *name, unsigned int *value)
+{
+ return -2;
+}
+
+int
+set_option(char *name, unsigned int value)
+{
+ return -2;
+}
+
#endif /* USE_OPTION_TABLE */
uint16_t word;
uint16_t pm10_bar;
uint32_t dword;
- int on;
+ uint32_t on;
#if 0
printk_debug("ACPI: disabling NMI watchdog.. ");
/* power on after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- get_option(&on, "power_on_after_fail");
+ get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
- get_option(&on, "slow_cpu");
+ get_option("slow_cpu", &on);
if(on) {
pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
static void lpc_init(struct device *dev)
{
uint8_t byte;
- int nmi_option;
+ uint32_t nmi_option;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x4B);
byte |= (1 << 6); /* clear LPCERR */
pci_write_config8(dev, 0x40, byte);
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte |= (1 << 7); /* set NMI */
pci_write_config8(dev, 0x40, byte);
uint32_t dword;
uint16_t word;
uint8_t byte;
- int nmi_option;
+ uint32_t nmi_option;
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);
/* NMI enable */
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if(nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);
/* power after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- get_option(&on, "power_on_after_fail");
+ get_option("power_on_after_fail", &on);
byte = pm_ioread(0x74);
byte &= ~0x03;
if (on) {
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
printk_info("++++++++++set NMI+++++\n");
{
uint8_t byte;
uint8_t byte_old;
- int nmi_option;
+ uint32_t nmi_option;
uint32_t dword;
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
- if (nmi_option) {
+ get_option("nmi", &nmi_option);
+ if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
{
uint8_t byte;
uint32_t value;
- int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
+ uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
/* sata settings */
pci_write_config32(dev, 0x58, 0x00001181);
esb6300_enable_lpc(dev);
- get_option(&pwr_on, "power_on_after_fail");
+ get_option("power_on_after_fail", &pwr_on);
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
static void lpc_init(struct device *dev)
{
u8 byte;
- int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
+ uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
setup_ioapic(dev);
i3100_enable_serial_irqs(dev);
- get_option(&pwr_on, "power_on_after_fail");
+ get_option("power_on_after_fail", &pwr_on);
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
{
uint32_t dword;
int rtc_failed;
- int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
pmcon3 &= ~RTC_POWER_FAILED;
}
- get_option(&pwr_on, "power_on_after_fail");
+ get_option("power_on_after_fail", &pwr_on);
pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
if (!pwr_on) {
pmcon3 |= SLEEP_AFTER_POWER_FAIL;
{
uint8_t byte;
int pwr_on=-1;
- int nmi_option;
+ uint32_t nmi_option;
/* IO APIC initialization */
i82801ca_enable_ioapic(dev);
outb(byte, 0x61);
byte = inb(0x70);
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);
{
uint8_t byte;
int pwr_on=-1;
- int nmi_option;
+ uint32_t nmi_option;
/* IO APIC initialization */
i82801dbm_enable_ioapic(dev);
outb(byte, 0x61);
byte = inb(0x70);
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);
{
uint8_t byte;
uint32_t value;
- int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* IO APIC initialization */
value = pci_read_config32(dev, 0xd0);
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
- get_option(&pwr_on, "power_on_after_fail");
+ get_option("power_on_after_fail", &pwr_on);
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
u8 reg8;
u16 reg16;
- int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- int nmi_option;
+ uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ uint32_t nmi_option;
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
*/
- get_option(&pwr_on, "power_on_after_fail");
+ get_option("power_on_after_fail", &pwr_on);
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 &= 0xfe;
if (pwr_on) {
reg8 = inb(0x70);
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
printk_info ("NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */
{
uint8_t byte;
int pwr_on = -1;
- int nmi_option;
+ uint32_t nmi_option;
/* power after power fail */
/* FIXME this doesn't work! */
byte = inb(0x70);
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* Set NMI. */
outb(byte, 0x70);
static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
{
- int bus_100Mhz = 0;
+ uint32_t bus_100Mhz = 0;
dev->link[0].dev = dev;
dev->links = 1;
- get_option(&bus_100Mhz, "pxhd_bus_speed_100");
+ get_option("pxhd_bus_speed_100", &bus_100Mhz);
if(bus_100Mhz) {
uint16_t word;
uint32_t dword;
uint16_t word;
uint8_t byte;
- int nmi_option;
+ uint32_t nmi_option;
/* Bridge control ISA enable */
pci_write_config8(dev, 0x3e, 0x07);
/* NMI enable */
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if(nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);
static void lpc_init(device_t dev)
{
uint8_t byte, byte_old;
- int on, nmi_option;
+ uint32_t on, nmi_option;
lpc_common_init(dev);
/* power after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- get_option(&on, "power_on_after_fail");
+ get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on)
/* Throttle the CPU speed down for testing. */
on = SLOW_CPU_OFF;
- get_option(&on, "slow_cpu");
+ get_option("slow_cpu", &on);
if (on) {
uint16_t pm10_bar;
uint32_t dword;
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* Set NMI. */
} else {
{
uint8_t byte;
uint8_t byte_old;
- int on;
- int nmi_option;
+ uint32_t on;
+ uint32_t nmi_option;
lpc_common_init(dev, 1);
#if 1
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- get_option(&on, "power_on_after_fail");
+ get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
#endif
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
- get_option(&on, "slow_cpu");
+ get_option("slow_cpu", &on);
if(on) {
uint16_t pm10_bar;
uint32_t dword;
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
{
uint8_t byte;
uint8_t byte_old;
- int on;
- int nmi_option;
+ uint32_t on;
+ uint32_t nmi_option;
printk_debug("LPC_INIT -------->\n");
init_pc_keyboard(0x60, 0x64, 0);
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- get_option(&on, "power_on_after_fail");
+ get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
- get_option(&on, "slow_cpu");
+ get_option("slow_cpu", &on);
if(on) {
uint16_t pm10_bar;
uint32_t dword;
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
+ get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
static void init_acpi(device_t dev)
{
uint8_t value = 0x20;
- int power_on = 1;
+ uint32_t power_on = 1;
- get_option(&power_on, "power_on_after_fail");
+ get_option("power_on_after_fail", &power_on);
pnp_enter_ext_func_mode(dev);
pnp_write_index(dev->path.pnp.port, 7, 0x0a);
value = pnp_read_config(dev, 0xe4);
static void init_acpi(device_t dev)
{
uint8_t value = 0x20;
- int power_on = 1;
+ uint32_t power_on = 1;
- get_option(&power_on, "power_on_after_fail");
+ get_option("power_on_after_fail", &power_on);
pnp_enter_ext_func_mode(dev);
pnp_write_index(dev->path.pnp.port,7,0x0a);
value = pnp_read_config(dev, 0xE4);
static unsigned char cmos_table[4096];
-/* This array is used to isolate bits that are to be changed in a byte */
-static unsigned char clip[9]={0,1,3,7,0x0f,0x1f,0x3f,0x7f,0xff};
-
-
/* This routine loops through the entried and tests if any of the fields overlap
input entry_start = the memory pointer to the start of the entries.
entry_end = the byte past the entries.
output none
if there is an overlap, the routine exits, other wise it returns.
*/
+
void test_for_entry_overlaps(void *entry_start, void *entry_end)
{
- int ptr;
char *cptr;
- int buffer_bit_size;
- int offset;
- int byte;
- int byte_length;
- struct cmos_entries *ce;
+ struct cmos_entries *ce = NULL;
unsigned char test[CMOS_IMAGE_BUFFER_SIZE];
- unsigned char set;
+ int i;
- /* calculate the size of the cmos buffer in bits */
- buffer_bit_size=(CMOS_IMAGE_BUFFER_SIZE*8);
- /* clear the temporary test buffer */
- for(ptr=0; ptr < CMOS_IMAGE_BUFFER_SIZE; ptr++)
- test[ptr]=0;
+ memset(test, 0, CMOS_IMAGE_BUFFER_SIZE);
+
+ for (cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) {
+ ce = (struct cmos_entries *)cptr;
+
+ /* Only reserved space can be larger than 32bits */
+ if ((ce->length > 32) && (ce->config != 'r')) {
+ fprintf(stderr, "Error: Entry %s is longer than"
+ " 32bits.\n", ce->name);
+ exit(1);
+ }
- /* loop through each entry in the table testing for errors */
- for(cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) {
- ce=(struct cmos_entries *)cptr;
/* test if entry goes past the end of the buffer */
- if((ce->bit+ce->length)>buffer_bit_size) {
- printf("Error - Entry %s start bit + length must be less than %d\n",
- ce->name,buffer_bit_size);
+ if ((ce->bit + ce->length) > (CMOS_IMAGE_BUFFER_SIZE * 8)) {
+ fprintf(stderr, "Error: Entry %s exceeds CMOS"
+ " space.\n", ce->name);
exit(1);
}
- byte=ce->bit/8;
- offset=ce->bit%8;
- byte_length=ce->length/8;
- if(byte_length) { /* entry is 8 bits long or more */
- if(offset) { /* if 8 bits or more long, it must be byte aligned */
- printf("Error - Entry %s length over 8 must be byte aligned\n",
- ce->name);
+
+ /* see whether our bits were marked before */
+ for (i = ce->bit; i < (ce->bit + ce->length); i++)
+ if (test[i / 8] & (0x01 << (i % 8))) {
+ printf("Error: Entry %s overlaps at bit %d.\n",
+ ce->name, i);
exit(1);
}
- /* test if entries 8 or more in length are even bytes */
- if(ce->length%8){
- printf("Error - Entry %s length over 8 must be a multiple of 8\n",
- ce->name);
- exit(1);
- }
- /* test if any of the bits have been previously used */
- for(;byte_length;byte_length--,byte++) {
- if(test[byte]) {
- printf("Error - Entry %s uses same bits previously used\n",
- ce->name);
- exit(1);
- }
- test[byte]=clip[8]; /* set the bits defined in test */
- }
- } else {
- /* test if bits overlap byte boundaries */
- if(ce->length>(8-offset)) {
- printf("Error - Entry %s length overlaps a byte boundry\n",
- ce->name);
- exit(1);
- }
- /* test for bits previously used */
- set=(clip[ce->length]<<offset);
- if(test[byte]&set) {
- printf("Error - Entry %s uses same bits previously used\n",
- ce->name);
- exit(1);
- }
- test[byte]|=set; /* set the bits defined in test */
- }
+
+ /* now mark our bits */
+ for (i = ce->bit; i < (ce->bit + ce->length); i++)
+ test[i / 8] |= 0x01 << (i % 8);
+
}
- return;
}
/* This routine displays the usage options */
return value;
}
-static int is_ident_digit(int c)
-{
- int result;
- switch(c) {
- case '0': case '1': case '2': case '3':
- case '4': case '5': case '6': case '7':
- case '8': case '9':
- result = 1;
- break;
- default:
- result = 0;
- break;
- }
- return result;
-}
-
static int is_ident_nondigit(int c)
{
- int result;
- switch(c) {
- case 'A': case 'B': case 'C': case 'D':
- case 'E': case 'F': case 'G': case 'H':
- case 'I': case 'J': case 'K': case 'L':
- case 'M': case 'N': case 'O': case 'P':
- case 'Q': case 'R': case 'S': case 'T':
- case 'U': case 'V': case 'W': case 'X':
- case 'Y': case 'Z':
- case 'a': case 'b': case 'c': case 'd':
- case 'e': case 'f': case 'g': case 'h':
- case 'i': case 'j': case 'k': case 'l':
- case 'm': case 'n': case 'o': case 'p':
- case 'q': case 'r': case 's': case 't':
- case 'u': case 'v': case 'w': case 'x':
- case 'y': case 'z':
- case '_':
- result = 1;
- break;
- default:
- result = 0;
- break;
- }
- return result;
+ if (((c >= 'A') && (c <='Z')) ||
+ ((c >= 'a') && (c <='z')) ||
+ (c == '_'))
+ return 1;
+ else
+ return 0;
}
static int is_ident(char *str)
do {
str++;
ch = *str;
- } while(ch && (is_ident_nondigit(ch) || (is_ident_digit(ch))));
+ } while(ch && (is_ident_nondigit(ch) || isdigit(ch)));
result = (ch == '\0');
}
return result;
c_enums->config_id=strtol(&line[ptr],(char**)NULL,10);
for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++);
for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++);
- c_enums->value=strtol(&line[ptr],(char**)NULL,10);
+ c_enums->value = strtoul(&line[ptr],(char**)NULL,0);
for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++);
for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++);
for(cnt=0;(line[ptr]!='\n')&&(cnt<31);ptr++,cnt++)
projects / coreboot.git / commitdiff