src/southbridge/nvidia/ck804/ck804_lpc.c

   1 /*
   2  * (C) 2003 Linux Networx, SuSE Linux AG
   3  * Copyright 2004 Tyan Computer
   4  *  by yhlu@tyan.com
   5  *  2006.1 yhlu add dest apicid for IRQ0
   6  */
   7
   8 #include <console/console.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <device/pnp.h>
  12 #include <device/pci_ids.h>
  13 #include <device/pci_ops.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <pc80/isa-dma.h>
  16 #include <bitops.h>
  17 #include <arch/io.h>
  18 #include <cpu/x86/lapic.h>
  19 #include <stdlib.h>
  20 #include "ck804.h"
  21
  22 #define CK804_CHIP_REV 2
  23
  24 #define NMI_OFF 0
  25
  26 struct ioapicreg {
  27         unsigned int reg;
  28         unsigned int value_low, value_high;
  29 };
  30
  31 static struct ioapicreg ioapicregvalues[] = {
  32 #define ALL             (0xff << 24)
  33 #define NONE            (0)
  34 #define DISABLED        (1 << 16)
  35 #define ENABLED         (0 << 16)
  36 #define TRIGGER_EDGE    (0 << 15)
  37 #define TRIGGER_LEVEL   (1 << 15)
  38 #define POLARITY_HIGH   (0 << 13)
  39 #define POLARITY_LOW    (1 << 13)
  40 #define PHYSICAL_DEST   (0 << 11)
  41 #define LOGICAL_DEST    (1 << 11)
  42 #define ExtINT          (7 << 8)
  43 #define NMI             (4 << 8)
  44 #define SMI             (2 << 8)
  45 #define INT             (1 << 8)
  46         /* IO-APIC virtual wire mode configuration */
  47         /* mask, trigger, polarity, destination, delivery, vector */
  48         {0,  ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
  49         {1,  DISABLED, NONE},
  50         {2,  DISABLED, NONE},
  51         {3,  DISABLED, NONE},
  52         {4,  DISABLED, NONE},
  53         {5,  DISABLED, NONE},
  54         {6,  DISABLED, NONE},
  55         {7,  DISABLED, NONE},
  56         {8,  DISABLED, NONE},
  57         {9,  DISABLED, NONE},
  58         {10, DISABLED, NONE},
  59         {11, DISABLED, NONE},
  60         {12, DISABLED, NONE},
  61         {13, DISABLED, NONE},
  62         {14, DISABLED, NONE},
  63         {15, DISABLED, NONE},
  64         {16, DISABLED, NONE},
  65         {17, DISABLED, NONE},
  66         {18, DISABLED, NONE},
  67         {19, DISABLED, NONE},
  68         {20, DISABLED, NONE},
  69         {21, DISABLED, NONE},
  70         {22, DISABLED, NONE},
  71         {23, DISABLED, NONE},
  72         /* Be careful and don't write past the end... */
  73 };
  74
  75 static void setup_ioapic(unsigned long ioapic_base)
  76 {
  77         int i;
  78         unsigned long value_low, value_high;
  79         /* unsigned long ioapic_base = 0xfec00000; */
  80         volatile unsigned long *l;
  81         struct ioapicreg *a = ioapicregvalues;
  82
  83         ioapicregvalues[0].value_high = lapicid() << (56 - 32);
  84
  85         l = (unsigned long *)ioapic_base;
  86
  87         for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
  88                 l[0] = (a->reg * 2) + 0x10;
  89                 l[4] = a->value_low;
  90                 value_low = l[4];
  91                 l[0] = (a->reg * 2) + 0x11;
  92                 l[4] = a->value_high;
  93                 value_high = l[4];
  94                 if ((i == 0) && (value_low == 0xffffffff)) {
  95                         printk_warning("IO APIC not responding.\n");
  96                         return;
  97                 }
  98                 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
  99                             a->reg, a->value_low, a->value_high);
 100         }
 101 }
 102
 103 // 0x7a or e3
 104 #define PREVIOUS_POWER_STATE 0x7A
 105
 106 #define MAINBOARD_POWER_OFF 0
 107 #define MAINBOARD_POWER_ON 1
 108 #define SLOW_CPU_OFF 0
 109 #define SLOW_CPU__ON 1
 110
 111 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 112 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 113 #endif
 114
 115 static void lpc_common_init(device_t dev)
 116 {
 117         uint8_t byte;
 118         uint32_t dword;
 119
 120         /* I/O APIC initialization */
 121         byte = pci_read_config8(dev, 0x74);
 122         byte |= (1 << 0);       /* Enable APIC. */
 123         pci_write_config8(dev, 0x74, byte);
 124         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);     /* 0x14 */
 125
 126         setup_ioapic(dword);
 127
 128 #if 1
 129         dword = pci_read_config32(dev, 0xe4);
 130         dword |= (1 << 23);
 131         pci_write_config32(dev, 0xe4, dword);
 132 #endif
 133 }
 134
 135 static void lpc_slave_init(device_t dev)
 136 {
 137         lpc_common_init(dev);
 138 }
 139
 140 static void rom_dummy_write(device_t dev)
 141 {
 142         uint8_t old, new;
 143         uint8_t *p;
 144
 145         old = pci_read_config8(dev, 0x88);
 146         new = old | 0xc0;
 147         if (new != old)
 148                 pci_write_config8(dev, 0x88, new);
 149         /* Enable write. */
 150         old = pci_read_config8(dev, 0x6d);
 151         new = old | 0x01;
 152         if (new != old)
 153                 pci_write_config8(dev, 0x6d, new);
 154
 155         /* Dummy write. */
 156         p = (uint8_t *) 0xffffffe0;
 157         old = 0;
 158         *p = old;
 159         old = *p;
 160
 161         /* Disable write. */
 162         old = pci_read_config8(dev, 0x6d);
 163         new = old & 0xfe;
 164         if (new != old)
 165                 pci_write_config8(dev, 0x6d, new);
 166 }
 167
 168 static void enable_hpet(struct device *dev)
 169 {
 170         unsigned long hpet_address;
 171
 172         pci_write_config32(dev, 0x44, 0xfed00001);
 173         hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
 174         printk_debug("Enabling HPET @0x%lx\n", hpet_address);
 175 }
 176
 177 unsigned pm_base=0;
 178
 179 static void lpc_init(device_t dev)
 180 {
 181         uint8_t byte, byte_old;
 182         int on, nmi_option;
 183
 184         lpc_common_init(dev);
 185
 186         pm_base = pci_read_config32(dev, 0x60) & 0xff00;
 187         printk_info("%s: pm_base = %x \n", __func__, pm_base);
 188
 189 #if CK804_CHIP_REV==1
 190         if (dev->bus->secondary != 1)
 191                 return;
 192 #endif
 193
 194 #if 0
 195         /* Posted memory write enable */
 196         byte = pci_read_config8(dev, 0x46);
 197         pci_write_config8(dev, 0x46, byte | (1 << 0));
 198 #endif
 199
 200         /* power after power fail */
 201         on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 202         get_option(&on, "power_on_after_fail");
 203         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 204         byte &= ~0x40;
 205         if (!on)
 206                 byte |= 0x40;
 207         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 208         printk_info("set power %s after power fail\n", on ? "on" : "off");
 209
 210         /* Throttle the CPU speed down for testing. */
 211         on = SLOW_CPU_OFF;
 212         get_option(&on, "slow_cpu");
 213         if (on) {
 214                 uint16_t pm10_bar;
 215                 uint32_t dword;
 216                 pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
 217                 outl(((on << 1) + 0x10), (pm10_bar + 0x10));
 218                 dword = inl(pm10_bar + 0x10);
 219                 on = 8 - on;
 220                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 221                              (on * 12) + (on >> 1), (on & 1) * 5);
 222         }
 223 #if 0
 224 // default is enabled
 225         /* Enable Port 92 fast reset. */
 226         byte = pci_read_config8(dev, 0xe8);
 227         byte |= ~(1 << 3);
 228         pci_write_config8(dev, 0xe8, byte);
 229 #endif
 230
 231         /* Enable Error reporting. */
 232         /* Set up sync flood detected. */
 233         byte = pci_read_config8(dev, 0x47);
 234         byte |= (1 << 1);
 235         pci_write_config8(dev, 0x47, byte);
 236
 237         /* Set up NMI on errors. */
 238         byte = inb(0x70);               /* RTC70 */
 239         byte_old = byte;
 240         nmi_option = NMI_OFF;
 241         get_option(&nmi_option, "nmi");
 242         if (nmi_option) {
 243                 byte &= ~(1 << 7); /* Set NMI. */
 244         } else {
 245                 byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
 246         }
 247         if (byte != byte_old)
 248                 outb(0x70, byte);
 249
 250         /* Initialize the real time clock (RTC). */
 251         rtc_init(0);
 252
 253         /* Initialize ISA DMA. */
 254         isa_dma_init();
 255
 256         /* Initialize the High Precision Event Timers (HPET). */
 257         enable_hpet(dev);
 258
 259         rom_dummy_write(dev);
 260 }
 261
 262 static void ck804_lpc_read_resources(device_t dev)
 263 {
 264         struct resource *res;
 265         unsigned long index;
 266
 267         /* Get the normal PCI resources of this device. */
 268         /* We got one for APIC, or one more for TRAP. */
 269         pci_dev_read_resources(dev);
 270
 271         /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
 272         for (index = 0x60; index <= 0x68; index += 4)   /* We got another 3. */
 273                 pci_get_resource(dev, index);
 274         compact_resources(dev);
 275
 276         /* Add an extra subtractive resource for both memory and I/O. */
 277         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 278         res->flags =
 279             IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 280
 281         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 282         res->flags =
 283             IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 284 }
 285
 286 /**
 287  * Enable resources for children devices.
 288  *
 289  * This function is called by the global enable_resources() indirectly via the
 290  * device_operation::enable_resources() method of devices.
 291  *
 292  * Indirect mutual recursion:
 293  *      enable_childrens_resources() -> enable_resources()
 294  *      enable_resources() -> device_operation::enable_resources()
 295  *      device_operation::enable_resources() -> enable_children_resources()
 296  *
 297  * @param dev The device whose children's resources are to be enabled.
 298  */
 299 static void ck804_lpc_enable_childrens_resources(device_t dev)
 300 {
 301         unsigned link;
 302         uint32_t reg, reg_var[4];
 303         int i, var_num = 0;
 304
 305         reg = pci_read_config32(dev, 0xa0);
 306
 307         for (link = 0; link < dev->links; link++) {
 308                 device_t child;
 309                 for (child = dev->link[link].children; child; child = child->sibling) {
 310                         enable_resources(child);
 311                         if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
 312                                 for (i = 0; i < child->resources; i++) {
 313                                         struct resource *res;
 314                                         unsigned long base, end;        // don't need long long
 315                                         res = &child->resource[i];
 316                                         if (!(res->flags & IORESOURCE_IO))
 317                                                 continue;
 318                                         base = res->base;
 319                                         end = resource_end(res);
 320                                         printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
 321                                         switch (base) {
 322                                         case 0x3f8:     // COM1
 323                                                 reg |= (1 << 0);
 324                                                 break;
 325                                         case 0x2f8:     // COM2
 326                                                 reg |= (1 << 1);
 327                                                 break;
 328                                         case 0x378:     // Parallel 1
 329                                                 reg |= (1 << 24);
 330                                                 break;
 331                                         case 0x3f0:     // FD0
 332                                                 reg |= (1 << 20);
 333                                                 break;
 334                                         case 0x220:     // Audio 0
 335                                                 reg |= (1 << 8);
 336                                                 break;
 337                                         case 0x300:     // Midi 0
 338                                                 reg |= (1 << 12);
 339                                                 break;
 340                                         }
 341                                         if (base == 0x290 || base >= 0x400) {
 342                                                 if (var_num >= 4)
 343                                                         continue;       // only 4 var ; compact them ?
 344                                                 reg |= (1 << (28 + var_num));
 345                                                 reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
 346                                         }
 347                                 }
 348                         }
 349                 }
 350         }
 351         pci_write_config32(dev, 0xa0, reg);
 352         for (i = 0; i < var_num; i++)
 353                 pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
 354 }
 355
 356 static void ck804_lpc_enable_resources(device_t dev)
 357 {
 358         pci_dev_enable_resources(dev);
 359         ck804_lpc_enable_childrens_resources(dev);
 360 }
 361
 362 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 363 {
 364         pci_write_config32(dev, 0x40,
 365                            ((device & 0xffff) << 16) | (vendor & 0xffff));
 366 }
 367
 368 static struct pci_operations lops_pci = {
 369         .set_subsystem = lpci_set_subsystem,
 370 };
 371
 372 static struct device_operations lpc_ops = {
 373         .read_resources   = ck804_lpc_read_resources,
 374         .set_resources    = pci_dev_set_resources,
 375         .enable_resources = ck804_lpc_enable_resources,
 376         .init             = lpc_init,
 377         .scan_bus         = scan_static_bus,
 378         // .enable        = ck804_enable,
 379         .ops_pci          = &lops_pci,
 380 };
 381
 382 static const struct pci_driver lpc_driver __pci_driver = {
 383         .ops    = &lpc_ops,
 384         .vendor = PCI_VENDOR_ID_NVIDIA,
 385         .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC,
 386 };
 387
 388 static const struct pci_driver lpc_driver_pro __pci_driver = {
 389         .ops    = &lpc_ops,
 390         .vendor = PCI_VENDOR_ID_NVIDIA,
 391         .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
 392 };
 393
 394 #if CK804_CHIP_REV == 1
 395 static const struct pci_driver lpc_driver_slave __pci_driver = {
 396         .ops    = &lpc_ops,
 397         .vendor = PCI_VENDOR_ID_NVIDIA,
 398         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 399 };
 400 #else
 401 static struct device_operations lpc_slave_ops = {
 402         .read_resources   = ck804_lpc_read_resources,
 403         .set_resources    = pci_dev_set_resources,
 404         .enable_resources = pci_dev_enable_resources,
 405         .init             = lpc_slave_init,
 406         // .enable        = ck804_enable,
 407         .ops_pci          = &lops_pci,
 408 };
 409
 410 static const struct pci_driver lpc_driver_slave __pci_driver = {
 411         .ops    = &lpc_slave_ops,
 412         .vendor = PCI_VENDOR_ID_NVIDIA,
 413         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 414 };
 415 #endif