+- 1.1.1
+ Updates to the new configuration system so it works more reliably
+ Removed a bunch of unused configuration variables
+ Removed a bunch of unused assembly code
+- 1.1.0
+ A whole bunch of random ppc and opteron work we never put a good label on
- 1.1.0
Intial development release of LinuxBIOS.
Everything is thrown overboard and will be reincluded as necessary so we can
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript cpu/i386/reset16.lds
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript cpu/i386/reset16.lds
+else
+ mainboardinit cpu/i386/reset32.inc
+ ldscript cpu/i386/reset32.lds
end
.
.
mainboardinit ./auto.inc
#
###
-### Setup RAM
-###
-mainboardinit ram/ramtest.inc
-mainboardinit southbridge/amd/amd8111/smbus.inc
-mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
export _RAMBASE:=0x4000
export ROM_IMAGE_SIZE:=65535
export PAYLOAD_SIZE:=131073
-export MAX_CPUS:=1
+export CONFIG_MAX_CPUS:=1
export HEAP_SIZE:=8192
export STACK_SIZE:=8192
export MEMORY_HOLE:=0
if (disable_logical_cpus) {
/* disable logical cpus */
int cnt;
- for(cnt=MAX_PHYSICAL_CPUS;cnt<MAX_CPUS;cnt++)
+ for(cnt=CONFIG_MAX_PHYSICAL_CPUS;cnt<CONFIG_MAX_CPUS;cnt++)
processor_map[cnt]=0;
printk_debug("logical cpus disabled\n");
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map);
/* A table (per mainboard) listing the initial apicid of each cpu. */
-extern unsigned long initial_apicid[MAX_CPUS];
+extern unsigned long initial_apicid[CONFIG_MAX_CPUS];
#else /* HAVE_MP_TABLE */
static inline
movl APIC_ID(%edi), %eax
shrl $24, %eax
- /* Get the cpu index (MAX_CPUS on error) */
+ /* Get the cpu index (CONFIG_MAX_CPUS on error) */
movl $-4, %ebx
1: addl $4, %ebx
- cmpl $(MAX_CPUS << 2), %ebx
+ cmpl $(CONFIG_MAX_CPUS << 2), %ebx
je 2
cmpl %eax, initial_apicid(%ebx)
jne 1b
cpuid(1, &eax, &ebx, &ecx, &edx);
cpu_features = eax;
cpu_feature_flags = edx;
- for(i = 0; i < MAX_CPUS; i++) {
+ for(i = 0; i < CONFIG_MAX_CPUS; i++) {
unsigned long cpu_apicid = initial_apicid[i];
unsigned long cpu_flag;
if(initial_apicid[i]==-1)
movl (APIC_ID + APIC_DEFAULT_BASE), %edi
shrl $24, %edi
- /* Get the cpu index (MAX_CPUS on error) */
+ /* Get the cpu index (CONFIG_MAX_CPUS on error) */
movl $-4, %ebx
1: addl $4, %ebx
- cmpl $(MAX_CPUS << 2), %ebx
+ cmpl $(CONFIG_MAX_CPUS << 2), %ebx
je 2
cmpl %edi, initial_apicid(%ebx)
jne 1b
#include <string.h>
#include <console/console.h>
-#ifndef START_CPU_SEG
-#define START_CPU_SEG 0x90000
-#endif
-#if (START_CPU_SEG&0xffff) != 0
-#error START_CPU_SEG must be 64k aligned
-#endif
-
static inline void hlt(void)
{
asm("hlt");
int processor_index(unsigned long apicid)
{
int i;
- for(i = 0; i < MAX_CPUS; i++) {
+ for(i = 0; i < CONFIG_MAX_CPUS; i++) {
if (initial_apicid[i] == apicid) {
return i;
}
int i;
/* Assume the cpus are densly packed by apicid */
- for(i = 0; i < MAX_CPUS; i++) {
+ for(i = 0; i < CONFIG_MAX_CPUS; i++) {
unsigned long cpu_apicid = initial_apicid[i];
if (cpu_apicid == -1) {
printk_err("CPU %d not found\n",i);
* info per processor at some point. I hope we don't need
* anything more complex than an int.
*/
-static unsigned long processor_map[MAX_CPUS];
+static unsigned long processor_map[CONFIG_MAX_CPUS];
static struct mem_range *get_ramsize(void)
{
}
active_count = atomic_read(&active_cpus);
}
- for(i = 0; i < MAX_CPUS; i++) {
+ for(i = 0; i < CONFIG_MAX_CPUS; i++) {
if (!(processor_map[i] & CPU_ENABLED)) {
printk_err("CPU %d did not initialize!\n", i);
processor_map[i] = 0;
comment "Objcopy command"
end
define LINUXBIOS_VERSION
- default "1.1.0"
+ default "1.1.1"
export always
comment "LinuxBIOS version"
end
end
define LINUXBIOS_COMPILE_DOMAIN
- default ""
+ default "$(shell dnsdomainname)"
export always
comment "Build domain name"
end
comment "Set if fallback booting required"
end
define USE_FALLBACK_IMAGE
- default 0
+ default 1
export used
comment "Set to build a fallback image"
end
-define USE_NORMAL_IMAGE
- format "%d"
- default {!USE_FALLBACK_IMAGE}
- export used
- comment "Set to build a normal image"
-end
define FALLBACK_SIZE
default 65536
format "0x%x"
comment "Size of cache when using it for temporary RAM"
end
define XIP_ROM_BASE
- default 0xffff8000
+ default 0
format "0x%x"
export used
- comment "base address of range of ROM that can be cached to speed up linuxBIOS"
+ comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
end
define XIP_ROM_SIZE
- default 0x8000
+ default 0
format "0x%x"
export used
- comment "size of range of ROM that can be cached to speed up linuxBIOS"
+ comment "Size of area to cache during LinuxBIOS execution directly from ROM"
end
define CONFIG_COMPRESS
default 1
define CONFIG_CONSOLE_SERIAL8250
default 0
export always
- comment "Log messages to serial 8250 console"
+ comment "Log messages to 8250 uart based serial console"
end
-define SERIAL_CONSOLE
- default none
- export used
- comment "Log messages to serial console"
-end
-
define DEFAULT_CONSOLE_LOGLEVEL
default 7
export always
export always
comment "Disable POST codes"
end
+
+define TTYS0_BASE
+ default 0x3f8
+ export always
+ comment "Base address for 8250 uart for the serial console"
+end
+
define TTYS0_BAUD
default 115200
export always
comment "Default baud rate for serial console"
end
-define NO_KEYBOARD
- default none
- export never
- comment "Set if we don't have a keyboard"
-end
+define TTYS0_LCS
+ default 0x3
+ export always
+ comment "Default flow control settings for the 8250 serial console uart"
+end
+
###############################################
# Mainboard options
###############################################
export always
comment "Vendor of mainboard"
end
-define FINAL_MAINBOARD_FIXUP
- default 0
- export used
- comment "Do final mainboard fixups"
-end
define CONFIG_SYS_CLK_FREQ
default none
export used
define CONFIG_MAX_CPUS
default 1
export always
- comment "Config CPU count for this machine"
+ comment "Maximum CPU count for this machine"
end
-define MAX_CPUS
- default 1
+define CONFIG_MAX_PHYSICAL_CPUS
+ default {CONFIG_MAX_CPUS}
export always
- comment "CPU count for this machine"
+ comment "Physical CPU count for this machine"
end
define CONFIG_LOGICAL_CPUS
- default 1
- export always
- comment "Logical CPU count for this machine"
-end
-define MAX_PHYSICAL_CPUS
- default 1
+ default 0
export always
- comment "Physical CPU count for this machine"
+ comment "Should multiple cpus per die be enabled?"
end
define HAVE_MP_TABLE
default none
# Boot options
###############################################
-define USE_ELF_BOOT
- default none
- export always
- comment "Use ELF boot loader"
-end
define CONFIG_IDE_STREAM
default 0
export always
comment "Increment value SMBUS"
end
-###############################################
-# SuperIO options
-###############################################
-
-define SIO_BASE
- default none
- export used
- comment "Superio base address"
-end
-define SIO_SYSTEM_CLK_INPUT
- default none
- export used
- comment "Superio CLK input default"
-end
-
###############################################
# Misc options
###############################################
export used
comment "Set to deal with memory hole"
end
-define ENABLE_FIXED_AND_VARIABLE_MTRRS
- default none
- export used
- comment "Enable fixed and variable mtrrs"
-end
-define START_CPU_SEG
- default 0xf0000
- format "0x%x"
- export always
- comment "Start CPU segment"
-end
define MAX_REBOOT_CNT
- default 2
+ default 3
export always
comment "Set maximum reboots"
end
-define DISABLE_WATCHDOG
- default {MAXIMUM_CONSOLE_LOGLEVEL >= 8}
- export used
- comment "Disable watchdog if we're doing lots of output"
-end
-define ENABLE_IOMMU
- default 1
- export used
- comment "Enable IOMMU aperture"
-end
###############################################
# Misc device options
###############################################
define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
- default none
+ default 0
export used
- comment ""
+ comment "Use timer2 to callibrate the x86 time stamp counter"
end
define INTEL_PPRO_MTRR
default none
export always
comment ""
end
-define AMD8111_DEV
- default 0x3800
- format "0x%x"
- export used
- comment ""
-end
define CONFIG_UDELAY_TSC
default 0
export used
- comment ""
+ comment "Implement udelay with the x86 time stamp counter"
end
###############################################
_stack = .;
.stack . : {
/* Reserve a stack for each possible cpu, +1 extra */
- . = ((MAX_CPUS * STACK_SIZE) + STACK_SIZE) ;
+ . = ((CONFIG_MAX_CPUS * STACK_SIZE) + STACK_SIZE) ;
}
_estack = .;
_heap = .;
#ifndef DEVICE_H
#define DEVICE_H
+#include <stdint.h>
#include <device/resource.h>
struct device;
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
-uses ENABLE_IOMMU
#
#
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
else
- print "NO FALLBACK USED!"
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
mainboardinit cpu/k8/earlymtrr.inc
#
#
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
-end
-#
####
#### O.k. We aren't just an intermediary anymore!
####
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
mainboardinit ./auto.inc
#
###
-### Setup RAM
-###
-mainboardinit ram/ramtest.inc
-mainboardinit southbridge/amd/amd8111/smbus.inc
-mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
cpu k7 end
cpu k8 end
-option ENABLE_IOMMU=1
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
+#define SIO_BASE 0x2e
+
static void memreset_setup(void)
{
/* Set the memreset low */
#include <device/pci_ops.h>
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1, 2, 3
};
###
### Customize our winbond superio chip for this motherboard
###
-option SIO_BASE=0x2e
-option SIO_SYSTEM_CLK_INPUT=0
option CONFIG_CONSOLE_SERIAL8250=0
#
###
##option HAVE_MP_TABLE=1
#
###
-### Do not build special code for the keyboard
-###
-default NO_KEYBOARD=1
-#
-###
### Build code for SMP support
### Only worry about 2 micro processors
###
##option CONFIG_SMP=1
-option MAX_CPUS=1
+option CONFIG_MAX_CPUS=1
#
###
### Build code to setup a generic IOAPIC
option MEMORY_HOLE=0
#
###
-### Enable both fixed and variable MTRRS
-### When we setup MTRRs in mtrr.c
-###
-### We must setup the fixed mtrrs or we confuse SMP secondary
-### processor identification
-###
-option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
-#
-###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="Solo7"
option MAINBOARD_VENDOR="AMD"
#
###
-### Let Assembly code know where on the pci bus the AMD southbridge is
-###
-option AMD8111_DEV=0x3800
-#
-###
-### Call the final_mainboard_fixup function
-###
-option FINAL_MAINBOARD_FIXUP=1
-#
-###
### Figure out which type of linuxBIOS image to build
### If we aren't a fallback image we must be a normal image
### This is useful for optional includes
###
default USE_FALLBACK_IMAGE=0
-option USE_NORMAL_IMAGE=(! USE_FALLBACK_IMAGE)
#
####
#### LinuxBIOS layout values
if USE_FALLBACK_IMAGE
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-end
-if USE_NORMAL_IMAGE
+else
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
option ROM_SECTION_OFFSET= 0
end
##option XIP_ROM_BASE=0xffff8000
#
###
-### Compute where the SMP startup code needs to live
-### FIXME I don't see how to make this work for the normal image....
-###
-option START_CPU_SEG=0xf0000
-#
-#
-###
### Set all of the defaults for an x86 architecture
###
#
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
+else
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
mainboardinit cpu/k8/earlymtrr.inc
#
#
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
-end
-#
####
#### O.k. We aren't just an intermediary anymore!
####
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
###
### Setup the serial port
mainboardinit ./auto.inc
#
###
-### Setup RAM
-###
-mainboardinit ram/ramtest.inc
-mainboardinit southbridge/amd/amd8111/smbus.inc
-mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
#include <device/pci_ops.h>
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0
};
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
-uses AMD8111_DEV
uses MAINBOARD
uses ARCH
-uses ENABLE_IOMMU
-#
-#
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+
###
-### Set all of the defaults for an x86 architecture
+### Build options
###
-#
-#
+
+##
+## Build code for the fallback boot
+##
+option HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+option HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+option HAVE_PIRQ_TABLE=1
+option IRQ_SLOT_COUNT=7
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+option HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+option HAVE_OPTION_TABLE=1
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+option CONFIG_SMP=1
+option CONFIG_MAX_CPUS=2
+
+##
+## Build code to setup a generic IOAPIC
+##
+option CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+option MAINBOARD_PART_NUMBER="HDAMA"
+option MAINBOARD_VENDOR="ARIMA"
+
###
-### Build the objects we have code for in this directory.
+### LinuxBIOS layout values
###
-##object mainboard.o
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+option ROM_SIZE = 524288
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+option ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+option STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+option HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ option ROM_SECTION_SIZE = FALLBACK_SIZE
+ option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ option ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+option CONFIG_ROM_STREAM = 1
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+option XIP_ROM_SIZE=65536
+option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+#cpu k8 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+#object mainboard.o
driver mainboard.o
-object static_devices.o
+#object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
+object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
+
+makerule ./failover.inc
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+end
+makerule ./auto.inc
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
else
- print "NO FALLBACK USED!"
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
-end
-#
-#### Should this be in the northbridge code?
+### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
+
+##
+## Include an id string (For safe flashing)
+##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
+
+##
+## Setup our mtrrs
+##
mainboardinit cpu/k8/earlymtrr.inc
+
###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
###
-#
if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
-# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
-#
-#
-###
-### Setup the serial port
-###
-#mainboardinit superiowinbond/w83627hf/setup_serial.inc
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### When debugging disable the watchdog timer
###
-##option MAXIMUM_CONSOLE_LOGLEVEL=7
-#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
-#
-#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
-#
+### O.k. We aren't just an intermediary anymore!
###
-### Romcc output
-###
-#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
-#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
-#mainboardinit .failover.inc
-
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
-end
-makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
-end
-makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
-end
+##
+## Setup RAM
+##
mainboardinit cpu/k8/enable_mmx_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/k8/disable_mmx_sse.inc
-#
-###
-### Setup RAM
-###
-#mainboardinit ram/ramtest.inc
-#mainboardinit southbridge/amd/amd8111/smbus.inc
-#mainboardinit sdram/generic_dump_spd.inc
-#
-###
-### Include the secondary Configuration files
-###
-northbridge amd/amdk8
-end
-southbridge amd/amd8111 "amd8111"
-end
-southbridge amd/amd8131 "amd8131"
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+
+northbridge amd/amdk8 "mc0"
+ #pci 0:18.0
+ #pci 0:18.0
+ #pci 0:18.0
+ #pci 0:18.1
+ #pci 0:18.2
+ #pci 0:18.3
+ southbridge amd/amd8131 "amd8131"
+ #pci 0:0.0
+ #pci 0:0.1
+ #pci 0:1.0
+ #pci 0:1.1
+ end
+ southbridge amd/amd8111 "amd8111"
+ #pci 0:0.0
+ #pci 0:1.0
+ #pci 0:1.1
+ #pci 0:1.2
+ #pci 0:1.3
+ #pci 0:1.5 off
+ #pci 0:1.6 off
+ superio NSC/pc87360
+ #pnp 1:2e.0
+ #pnp 1:2e.1
+ #pnp 1:2e.2
+ #pnp 1:2e.3
+ #pnp 1:2e.4
+ #pnp 1:2e.5
+ #pnp 1:2e.6
+ #pnp 1:2e.7
+ #pnp 1:2e.8
+ #pnp 1:2e.9
+ #pnp 1:2e.a
+ register "com1" = "{1, 0, 0x3f8, 4}"
+ register "lpt" = "{1}"
+ end
+ end
end
-#mainboardinit archi386/smp/secondary.inc
-superio NSC/pc87360
- register "com1" = "{1}"
- register "lpt" = "{1}"
+
+northbridge amd/amdk8 "mc1"
+ #pci 0:19.0
+ #pci 0:19.0
+ #pci 0:19.0
+ #pci 0:19.1
+ #pci 0:19.2
+ #pci 0:19.3
end
-dir /pc80
-##dir /src/superio/winbond/w83627hf
-#dir /cpu/k8
-cpu k8 "cpu0"
- register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
+
+cpu k8 "cpu0"
+ register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
end
-option ENABLE_IOMMU=1
+##
+## Include the old serial code for those few places that still need it.
+##
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
+
#define ASSEMBLY 1
-#define MAXIMUM_CONSOLE_LOGLEVEL 9
-#define DEFAULT_CONSOLE_LOGLEVEL 9
#include <stdint.h>
#include <device/pci_def.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
+#define SIO_BASE 0x2e
+
static void memreset_setup(void)
{
/* Set the memreset low */
}
#define FIRST_CPU 1
-#define SECOND_CPU 0
+#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(void)
{
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-#if 1
+#if 0
dump_pci_devices();
#endif
#if 0
#endif
#if 0
ram_check(0x00000000, msr.lo);
-#else
-#if TOTAL_CPUS < 2
- /* Check 16MB of memory @ 0*/
- ram_check(0x00000000, 0x01000);
-#else
- /* Check 16MB of memory @ 2GB */
- ram_check(0x80000000, 0x81000000);
#endif
+#if 0
+ static const struct {
+ unsigned long lo, hi;
+ } check_addrs[] = {
+ /* Check 16MB of memory @ 0*/
+ { 0x00000000, 0x01000000 },
+#if TOTAL_CPUS > 1
+ /* Check 16MB of memory @ 2GB */
+ { 0x80000000, 0x81000000 },
+#endif
+ };
+ int i;
+ for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+ ram_check(check_addrs[i].lo, check_addrs[i].hi);
+ }
#endif
}
#include "chip.h"
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
-uses AMD8111_DEV
uses MAINBOARD
uses ARCH
-uses ENABLE_IOMMU
#
#
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
else
- print "NO FALLBACK USED!"
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
#
if USE_FALLBACK_IMAGE
mainboardinit ./failover.inc
-# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
end
#
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
mainboardinit cpu/k8/disable_mmx_sse.inc
#
###
-### Setup RAM
-###
-#mainboardinit ram/ramtest.inc
-#mainboardinit southbridge/amd/amd8111/smbus.inc
-#mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
cpu k8 "cpu1"
end
-option ENABLE_IOMMU=1
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
+#define SIO_BASE 0x2e
+
static void memreset_setup(void)
{
/* Set the memreset low */
#include "chip.h"
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
-uses AMD8111_DEV
uses MAINBOARD
uses ARCH
-uses ENABLE_IOMMU
#
#
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
else
-# print "NO FALLBACK USED!"
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
#
if USE_FALLBACK_IMAGE
mainboardinit ./failover.inc
-# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
end
#
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
mainboardinit cpu/k8/disable_mmx_sse.inc
#
###
-### Setup RAM
-###
-#mainboardinit ram/ramtest.inc
-#mainboardinit southbridge/amd/amd8111/smbus.inc
-#mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
cpu k8 "cpu1"
end
-
-option ENABLE_IOMMU=1
#include "chip.h"
//#include <part/mainboard.h>
//#include "lsi_scsi.c"
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0,1
};
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
-uses AMD8111_DEV
uses MAINBOARD
uses ARCH
-uses ENABLE_IOMMU
#
#
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
else
-# print "NO FALLBACK USED!"
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
#
if USE_FALLBACK_IMAGE
mainboardinit ./failover.inc
-# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
end
#
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
mainboardinit cpu/k8/disable_mmx_sse.inc
#
###
-### Setup RAM
-###
-#mainboardinit ram/ramtest.inc
-#mainboardinit southbridge/amd/amd8111/smbus.inc
-#mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
cpu k8 "cpu1"
end
-
-option ENABLE_IOMMU=1
#include "chip.h"
//#include <part/mainboard.h>
//#include "lsi_scsi.c"
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0,1
};
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
-uses AMD8111_DEV
uses MAINBOARD
uses ARCH
-uses ENABLE_IOMMU
#
#
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
else
-# print "NO FALLBACK USED!"
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
#
if USE_FALLBACK_IMAGE
mainboardinit ./failover.inc
-# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
end
#
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
mainboardinit cpu/k8/disable_mmx_sse.inc
#
###
-### Setup RAM
-###
-#mainboardinit ram/ramtest.inc
-#mainboardinit southbridge/amd/amd8111/smbus.inc
-#mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
cpu k8 "cpu1"
end
-option ENABLE_IOMMU=0
-
#include "chip.h"
//#include <part/mainboard.h>
//#include "lsi_scsi.c"
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0,1
};
print_debug(" done.\r\n");
}
-#if MAX_CPUS > 1
+#if CONFIG_MAX_CPUS > 1
static void rename_temp_node(u8 node)
{
#endif
-#if MAX_CPUS > 2
+#if CONFIG_MAX_CPUS > 2
static void setup_temp_node(u8 node, u8 cpus)
{
u8 row;
return 1;
}
-#if MAX_CPUS > 1
+#if CONFIG_MAX_CPUS > 1
static u8 setup_smp(void)
{
u8 cpus=2;
clear_temp_row(0); /* delete temporary connection */
-#if MAX_CPUS > 2
+#if CONFIG_MAX_CPUS > 2
cpus=4;
/* Setup and check temporary connection from Node 0 to Node 2 */
}
#endif
-#if MAX_CPUS > 1
+#if CONFIG_MAX_CPUS > 1
static unsigned detect_mp_capabilities(unsigned cpus)
{
unsigned node, row, mask;
enable_bsp_routing();
-#if MAX_CPUS == 1
+#if CONFIG_MAX_CPUS == 1
cpus=setup_uniprocessor();
#else
cpus=setup_smp();
#include <cpu/k8/mtrr.h>
#include "raminit.h"
+#define ENABLE_IOMMU 1
+
/* Function 2 */
#define DRAM_CSBASE 0x40
#define DRAM_CSMASK 0x60
target hdama
-uses AMD8111_DEV
uses ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
-uses ENABLE_FIXED_AND_VARIABLE_MTRRS
uses FALLBACK_SIZE
-uses FINAL_MAINBOARD_FIXUP
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
+uses HAVE_HARD_RESET
uses i586
uses i686
uses INTEL_PPRO_MTRR
-uses IRQ_SLOT_COUNT
uses HEAP_SIZE
+uses IRQ_SLOT_COUNT
uses k7
uses k8
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
-uses MAX_CPUS
+uses CONFIG_SMP
+uses CONFIG_MAX_CPUS
uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
-uses SIO_BASE
-uses SIO_SYSTEM_CLK_INPUT
uses STACK_SIZE
-uses USE_ELF_BOOT
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses MAINBOARD
uses CONFIG_CHIP_CONFIGURE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses LINUXBIOS_EXTRA_VERSION
option CONFIG_CHIP_CONFIGURE=1
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-option DEFAULT_CONSOLE_LOGLEVEL=7
+option MAXIMUM_CONSOLE_LOGLEVEL=8
+option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
option CPU_FIXUP=1
option CONFIG_UDELAY_TSC=0
option i686=1
option INTEL_PPRO_MTRR=1
option k7=1
option k8=1
-option ROM_SIZE=0x100000
-### Customize our winbond superio chip for this motherboard
-###
-option SIO_BASE=0x2e
-option SIO_SYSTEM_CLK_INPUT=0
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=18
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option MAX_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-option MEMORY_HOLE=0
-#
-###
-### Enable both fixed and variable MTRRS
-### When we setup MTRRs in mtrr.c
-###
-### We must setup the fixed mtrrs or we confuse SMP secondary
-### processor identification
-###
-option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
+option ROM_SIZE=524288
-###
-### Call the final_mainboard_fixup function
-###
-option FINAL_MAINBOARD_FIXUP=1
+
+option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_STREAM=1
+option HAVE_FALLBACK_BOOT=1
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
-option FALLBACK_SIZE=0x100000
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-### Compute a range of ROM that can cached to speed up linuxBIOS,
-### execution speed.
-###
-##expr XIP_ROM_SIZE = 65536
-##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
-##option XIP_ROM_SIZE=65536
-##option XIP_ROM_BASE=0xffff0000
-#
-## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
-##option XIP_ROM_SIZE=0x8000
-##option XIP_ROM_BASE=0xffff8000
-
-## We don't use compressed image
-option CONFIG_COMPRESS=1
-
-option USE_ELF_BOOT=1
+option FALLBACK_SIZE=131072
## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x4000
-
-##
-## Use a 64K stack
-##
-option STACK_SIZE=0x10000
-
-##
-## Use a 64K heap
-##
-option HEAP_SIZE=0x10000
+option _RAMBASE=0x00004000
#
###
#
# Arima hdama
-#romimage "normal"
-# option USE_FALLBACK_IMAGE=0
-# option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
-# option ROM_SECTION_OFFSET= 0
-# option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-# option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-# option CONFIG_ROM_STREAM = 1
-# option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-# mainboard arima/hdama
-# payload ../eepro100.ebi
-#end
+romimage "normal"
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ mainboard arima/hdama
+ payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+end
romimage "fallback"
- option ROM_IMAGE_SIZE=0x10000
-# option ROM_IMAGE_SIZE=120*1024
option USE_FALLBACK_IMAGE=1
- option HAVE_FALLBACK_BOOT=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option CONFIG_ROM_STREAM = 1
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION=".0Fallback"
mainboard arima/hdama
- payload ../../../../tg3--ide_disk.zelf
-# payload ../../../../opteron_phase1_p4_noapic
+ payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
end
buildrom ROM_SIZE "normal" "fallback"
uses CONFIG_IDE_STREAM
uses CONFIG_SYS_CLK_FREQ
uses IDE_BOOT_DRIVE
-uses USE_ELF_BOOT
uses IDE_SWAB IDE_OFFSET
uses ROM_SIZE ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
## Boot linux from IDE
option CONFIG_IDE_STREAM=1
option IDE_BOOT_DRIVE=0
-option USE_ELF_BOOT=1
option IDE_SWAB=1
option IDE_OFFSET=0
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_IDE_STREAM
uses IDE_BOOT_DRIVE
-uses USE_ELF_BOOT
uses IDE_SWAB IDE_OFFSET
uses ROM_SIZE ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
## Boot linux from IDE
option CONFIG_IDE_STREAM=1
option IDE_BOOT_DRIVE=0
-option USE_ELF_BOOT=1
option IDE_SWAB=1
option IDE_OFFSET=0
target s2880
-uses AMD8111_DEV
uses ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
-uses ENABLE_FIXED_AND_VARIABLE_MTRRS
uses FALLBACK_SIZE
-uses FINAL_MAINBOARD_FIXUP
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
-uses MAX_CPUS
#uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
-uses SIO_BASE
-uses SIO_SYSTEM_CLK_INPUT
uses STACK_SIZE
-uses USE_ELF_BOOT
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses CONFIG_CHIP_CONFIGURE
uses DEBUG
uses CONFIG_MAX_CPUS
uses CONFIG_LOGICAL_CPUS
-uses MAX_PHYSICAL_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
uses LINUXBIOS_EXTRA_VERSION
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
#option CONFIG_LSI_SCSI_FW_FIXUP=1
-### Customize our winbond superio chip for this motherboard
-###
-option SIO_BASE=0x2e
-option SIO_SYSTEM_CLK_INPUT=0
#
###
### Build code to export a programmable irq routing table
###
option CONFIG_SMP=1
option CONFIG_MAX_CPUS=2
-option MAX_CPUS=2
option CONFIG_LOGICAL_CPUS=0
-option MAX_PHYSICAL_CPUS=2
+option CONFIG_MAX_PHYSICAL_CPUS=2
#
###
### Build code to setup a generic IOAPIC
#option MEMORY_HOLE=0
#
###
-### Enable both fixed and variable MTRRS
-### When we setup MTRRs in mtrr.c
-###
-### We must setup the fixed mtrrs or we confuse SMP secondary
-### processor identification
-###
-option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
-#
-###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="S2880"
option MAINBOARD_VENDOR="Tyan"
#
-###
-### Call the final_mainboard_fixup function
-###
-option FINAL_MAINBOARD_FIXUP=1
-
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
## We do use compressed image
option CONFIG_COMPRESS=1
-option USE_ELF_BOOT=1
-
-
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BAUD=115200
option DEBUG=1
-option AMD8111_DEV=0x5
-
#
## LinuxBIOS C code runs at this location in RAM
target s2882
-uses AMD8111_DEV
uses ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
-uses ENABLE_FIXED_AND_VARIABLE_MTRRS
uses FALLBACK_SIZE
-uses FINAL_MAINBOARD_FIXUP
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
-uses MAX_CPUS
#uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
-uses SIO_BASE
-uses SIO_SYSTEM_CLK_INPUT
uses STACK_SIZE
-uses USE_ELF_BOOT
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses CONFIG_CHIP_CONFIGURE
uses DEBUG
uses CONFIG_MAX_CPUS
uses CONFIG_LOGICAL_CPUS
-uses MAX_PHYSICAL_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
uses LINUXBIOS_EXTRA_VERSION
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
#option CONFIG_LSI_SCSI_FW_FIXUP=1
-### Customize our winbond superio chip for this motherboard
-###
-option SIO_BASE=0x2e
-option SIO_SYSTEM_CLK_INPUT=0
#
###
### Build code to export a programmable irq routing table
###
option CONFIG_SMP=1
option CONFIG_MAX_CPUS=2
-option MAX_CPUS=2
option CONFIG_LOGICAL_CPUS=0
-option MAX_PHYSICAL_CPUS=2
+option CONFIG_MAX_PHYSICAL_CPUS=2
#
###
### Build code to setup a generic IOAPIC
#option MEMORY_HOLE=0
#
###
-### Enable both fixed and variable MTRRS
-### When we setup MTRRs in mtrr.c
-###
-### We must setup the fixed mtrrs or we confuse SMP secondary
-### processor identification
-###
-option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
-#
-###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="S2882"
option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Call the final_mainboard_fixup function
-###
-option FINAL_MAINBOARD_FIXUP=1
-
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
## We do use compressed image
option CONFIG_COMPRESS=1
-option USE_ELF_BOOT=1
-
-
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BAUD=115200
option DEBUG=1
-option AMD8111_DEV=0x5
-
#
## LinuxBIOS C code runs at this location in RAM
target s2885
-uses AMD8111_DEV
uses ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
-uses ENABLE_FIXED_AND_VARIABLE_MTRRS
uses FALLBACK_SIZE
-uses FINAL_MAINBOARD_FIXUP
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
-uses MAX_CPUS
#uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
-uses SIO_BASE
-uses SIO_SYSTEM_CLK_INPUT
uses STACK_SIZE
-uses USE_ELF_BOOT
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses CONFIG_CHIP_CONFIGURE
uses DEBUG
uses CONFIG_MAX_CPUS
uses CONFIG_LOGICAL_CPUS
-uses MAX_PHYSICAL_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
uses LINUXBIOS_EXTRA_VERSION
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
#option CONFIG_LSI_SCSI_FW_FIXUP=1
-### Customize our winbond superio chip for this motherboard
-###
-option SIO_BASE=0x2e
-option SIO_SYSTEM_CLK_INPUT=0
-#
###
### Build code to export a programmable irq routing table
###
###
option CONFIG_SMP=1
option CONFIG_MAX_CPUS=2
-option MAX_CPUS=2
option CONFIG_LOGICAL_CPUS=0
-option MAX_PHYSICAL_CPUS=2
+option CONFIG_MAX_PHYSICAL_CPUS=2
#
###
### Build code to setup a generic IOAPIC
#option MEMORY_HOLE=0
#
###
-### Enable both fixed and variable MTRRS
-### When we setup MTRRs in mtrr.c
-###
-### We must setup the fixed mtrrs or we confuse SMP secondary
-### processor identification
-###
-option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
-#
-###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="S2885"
option MAINBOARD_VENDOR="Tyan"
#
-###
-### Call the final_mainboard_fixup function
-###
-option FINAL_MAINBOARD_FIXUP=1
-
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
## We do use compressed image
option CONFIG_COMPRESS=1
-option USE_ELF_BOOT=1
-
-
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BAUD=115200
option DEBUG=1
-option AMD8111_DEV=0x5
-
#
## LinuxBIOS C code runs at this location in RAM
import string
import types
+import traceback
+
warnings = 0
errors = 0
return len(self.stack)
def __getitem__ (self, i):
- try:
- return self.stack[i]
- except IndexError:
- return 0
+ return self.stack[i]
def __iter__ (self):
return self.__stack_iter(self.stack)
# definitions for this part (only want to do it once)
self.done_types = 0
+ # Path to the device
+ self.path = ""
+
# If no instance name is supplied then generate
# a unique name
if (instance_name == 0):
# me as the child.
if (parent.children):
debug.info(debug.gencode, "add %s (%d) as sibling" % (parent.children.dir, parent.children.instance))
- self.siblings = parent.children
- parent.children = self
+ youngest = parent.children;
+ while(youngest.siblings):
+ youngest = youngest.siblings
+ youngest.siblings = self
+ else:
+ parent.children = self
else:
self.parent = self
print "%d: siblings %s" % (lvl, self.siblings.dir)
print "%d: initcode " % lvl
for i in self.initcode:
- print " %s" % i
+ print "\t%s" % i
print "%d: registercode " % lvl
for f, v in self.registercode.items():
- print " %s = %s" % (f, v)
+ print "\t%s = %s" % (f, v)
print "\n"
def gencode(self, file, pass_num):
if (self.registercode):
file.write("\t= {\n")
for f, v in self.registercode.items():
- file.write( " .%s = %s,\n" % (f, v))
+ file.write( "\t.%s = %s,\n" % (f, v))
file.write("};\n")
else:
file.write(";")
file.write("struct chip %s = {\n" % self.instance_name)
else:
file.write("struct chip static_root = {\n")
- file.write("/* %s %s */\n" % (self.part, self.dir))
+ file.write("\t/* %s %s */\n" % (self.part, self.dir))
+ if (self.path != ""):
+ file.write("\t.path = { %s\n\t},\n" % (self.path) );
if (self.siblings):
debug.info(debug.gencode, "gencode: siblings(%d)" \
% self.siblings.instance)
- file.write(" .next = &%s,\n" \
+ file.write("\t.next = &%s,\n" \
% self.siblings.instance_name)
else:
- file.write(" .next = 0,\n")
+ file.write("\t.next = 0,\n")
if (self.children):
debug.info(debug.gencode, "gencode: children(%d)" \
% self.children.instance)
- file.write(" .children = &%s,\n" \
+ file.write("\t.children = &%s,\n" \
% self.children.instance_name)
else:
- file.write(" .children = 0,\n")
+ file.write("\t.children = 0,\n")
if (self.chipconfig):
# set the pointer to the structure for all this
# type of part
- file.write(" .control= &%s_control,\n" % \
+ file.write("\t.control= &%s_control,\n" % \
self.type_name )
# generate the pointer to the isntance
# of the chip struct
- file.write(" .chip_info = (void *) &%s,\n" \
+ file.write("\t.chip_info = (void *) &%s,\n" \
% self.config_name)
else:
- file.write(" .control= 0,\n")
- file.write(" .chip_info= 0,\n")
+ file.write("\t.control= 0,\n")
+ file.write("\t.chip_info= 0,\n")
file.write("};\n")
def addinit(self, code):
value = dequote(value)
setdict(self.registercode, field, value)
+ def addpcipath(self, enable, channel, slot, function):
+ """ Add a relative pci style path from our parent to this device """
+ if (channel < 0):
+ fatal("Invalid channel")
+ if ((slot < 0) or (slot > 0x1f)):
+ fatal("Invalid device id")
+ if ((function < 0) or (function > 7)):
+ fatal("Invalid function")
+ self.path = "%s\n\t\t{ .channel = %d, .enable = %d, .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x%x,%d) }}}}," % (self.path, channel, enable, slot, function)
+
+ def addpnppath(self, enable, channel, port, device):
+ """ Add a relative path to a pnp device hanging off our parent """
+ if (channel < 0):
+ fatal("Invalid channel")
+ if ((port < 0) or (port > 65536)):
+ fatal("Invalid port")
+ if ((device < 0) or (device > 0xff)):
+ fatal("Invalid device")
+ self.path = "%s\n\t\t{ .channel = %d, .enable = %d, .path={.type=DEVICE_PATH_PNP,.u={.pnp={ .port = 0x%x, .device = 0x%x }}}}," % (self.path, channel, enable, port, device)
+
+ def addi2cpath(self, enable, channel, device):
+ """ Add a relative path to a i2c device hanging off our parent """
+ if (channel < 0):
+ fatal("Invalid channel")
+ if ((device < 0) or (device > 0x7f)):
+ fatal("Invalid device")
+ self.path = "%s\n\t\t{ .channel = %d, .enable = %d, .path = {.type=DEVICE_PATH_I2C,.u={.i2c={ .device = 0x%x }}}}, " % (self.path, channel, enable, device)
+
def usesoption(self, name):
"""Declare option that can be used by this part"""
global global_options
global cpu_type
if (cpu_type and (cpu_type != path)):
fatal("Two different CPU types: %s and %s" % (cpu_type, path))
- if (not cpu_type):
- srcdir = "/cpu/%s" % path
- dodir(srcdir, "Config.lb")
- cpu_type = path
+ srcdir = "/cpu/%s" % path
+ dodir(srcdir, "Config.lb")
+ cpu_type = path
def part(type, path, file, name):
global curimage, dirstack, partstack
def IsInt( str ):
""" Is the given string an integer?"""
try:
- num = int(str)
+ num = long(str)
return 1
except ValueError:
return 0
token TARGET: 'target'
token USED: 'used'
token USES: 'uses'
- token NUM: r'[0-9]+'
- token XNUM: r'0x[0-9a-fA-F]+'
+ token NUM: '[0-9]+'
+ token HEX_NUM: '[0-9a-fA-F]+'
+ token HEX_PREFIX: '0x'
# Why is path separate? Because paths to resources have to at least
# have a slash, we thinks
token PATH: r'[a-zA-Z0-9_.][a-zA-Z0-9/_.]+[a-zA-Z0-9_.]+'
token DELEXPR: r'{([^}]+|\\.)*}'
token STR: r'"([^\\"]+|\\.)*"'
token RAWTEXT: r'.*'
+ token ON: 'on'
+ token OFF: 'off'
+ token PCI: 'pci'
+ token PNP: 'pnp'
+ token I2C: 'i2c'
+
rule expr: logical {{ l = logical }}
( "&&" logical {{ l = l and logical }}
)* {{ return v }}
# A term is a number, variable, or an expression surrounded by parentheses
- rule term: NUM {{ return atoi(NUM) }}
- | XNUM {{ return tohex(XNUM) }}
+ rule term: NUM {{ return long(NUM, 10) }}
+ | HEX_PREFIX HEX_NUM {{ return long(HEX_NUM, 16) }}
| ID {{ return lookup(ID) }}
| unop {{ return unop }}
| "\\(" expr "\\)" {{ return expr }}
rule register<<C>>: REGISTER field '=' STR {{ if (C): addregister(field, STR) }}
+ rule enable: {{ val = 1 }}
+ [ ( ON {{ val = 1 }}
+ | OFF {{ val = 0 }}
+ ) ] {{ return val }}
+
+ rule pci<<C>>: PCI HEX_NUM {{ channel = int(HEX_NUM,16) }}
+ ':' HEX_NUM {{ slot = int(HEX_NUM,16) }}
+ '.' HEX_NUM {{ function = int(HEX_NUM, 16) }}
+ enable
+ {{ if (C): partstack.tos().addpcipath(enable, channel, slot, function) }}
+
+ rule pnp<<C>>: PNP HEX_NUM {{ channel = int(HEX_NUM,16) }}
+ ':' HEX_NUM {{ port = int(HEX_NUM,16) }}
+ '.' HEX_NUM {{ device = int(HEX_NUM, 16) }}
+ enable
+ {{ if (C): partstack.tos().addpnppath(enable, channel, port, device) }}
+
+ rule i2c<<C>>: I2C HEX_NUM {{ channel = int(HEX_NUM, 16) }}
+ ':' HEX_NUM {{ device = int(HEX_NUM, 16) }}
+ enable
+ {{ if (C): partstatck.tos().addi2cpath(enable, channel, device) }}
+
rule prtval: expr {{ return str(expr) }}
| STR {{ return STR }}
| object<<C>> {{ return object }}
| option<<C>> {{ return option }}
| partdef<<C>> {{ return partdef }}
- | prtstmt<<C>> {{ return prtstmt}}
- | register<<C>> {{ return register}}
+ | prtstmt<<C>> {{ return prtstmt }}
+ | register<<C>> {{ return register }}
+ | pci<<C>> {{ return pci }}
+ | pnp<<C>> {{ return pnp }}
# ENTRY for parsing Config.lb file
rule cfgfile: (uses<<1>>)*
# Instead, let make do the work of computing CPUFLAGS:
file.write("# Get the value of TOP, VARIABLES, and several other variables.\n")
file.write("include Makefile.settings\n\n")
- file.write("# Function to create an item like -Di586 or -DMAX_CPUS='1' or -Ui686\n")
+ file.write("# Function to create an item like -Di586 or -DCONFIG_MAX_CPUS='1' or -Ui686\n")
file.write("D_item = $(if $(subst undefined,,$(origin $1)),-D$1$(if $($1),='$($1)',),-U$1)\n\n")
file.write("# Compute the value of CPUFLAGS here during make's first pass.\n")
file.write("CPUFLAGS := $(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))\n\n")
#file.write("\tpython $(TOP)/util/config/NLBConfig.py %s $(TOP)\n"
# % top_config_file)
- keys = image.getroot().uses_options.keys()
+ #keys = image.getroot().uses_options.keys()
+ keys = global_options_by_order
keys.sort()
file.write("\necho:\n")
for key in keys:
print "Creating", filename
file = safe_open(filename, 'w+')
file.write("#include <device/chip.h>\n")
+ file.write("#include <device/pci.h>\n")
for path in image.getconfigincludes().values():
file.write("#include \"%s\"\n" % path)
gencode(image.getroot(), file, 0)
projects / coreboot.git / commitdiff