No warnings day, next round.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/Kconfig b/src/Kconfig
index 2eb8cd82031921894eece2f37e4b667773827fed..8b07fe39fe85e24c2d06d6005eb8b6e87a446600 100644 (file)
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -621,7 +621,8 @@ config DEBUG_SMBUS
        depends on (SOUTHBRIDGE_VIA_VT8237R \
                 || NORTHBRIDGE_VIA_VX800 \
                 || NORTHBRIDGE_VIA_CX700 \
-                || NORTHBRIDGE_AMD_AMDK8)
+                || NORTHBRIDGE_AMD_AMDK8 \
+                || NORTHBRIDGE_AMD_AMDFAM10)
        help
          This option enables additional SMBus (and SPD) debug messages.
 

diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 0061706e3f280cf6623fe7f1e2763037616af5a7..e701b4e8dbdcbafad8fd6b7c3cb77dac7ee76097 100644 (file)
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -91,7 +91,7 @@ static void set_pci_mmio_conf_reg(void)
        wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
 
        //mtrr for that range?
-//     set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
+       // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
 
        set_wrap32dis();
 
@@ -293,7 +293,7 @@ static void enable_apic_ext_id(u32 node)
 }
 
 
-static void STOP_CAR_AND_CPU()
+static void STOP_CAR_AND_CPU(void)
 {
        msr_t msr;
 
@@ -529,7 +529,7 @@ static void setup_remote_node(u8 node)
 }
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
-void AMD_Errata281(u8 node, u32 revision, u32 platform)
+static void AMD_Errata281(u8 node, u32 revision, u32 platform)
 {
        /* Workaround for Transaction Scheduling Conflict in
         * Northbridge Cross Bar.  Implement XCS Token adjustment
@@ -591,7 +591,7 @@ void AMD_Errata281(u8 node, u32 revision, u32 platform)
 }
 
 
-void AMD_Errata298(void)
+static void AMD_Errata298(void)
 {
        /* Workaround for L2 Eviction May Occur during operation to
         * set Accessed or dirty bit.

diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 165155f2ed7d7e19618ede0413a5fc7d88c750f7..ed1a168ba3dd0f908486e0fa41ec7311b9ef080f 100644 (file)
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -244,7 +244,6 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
 static void init_ecc_memory(unsigned node_id)
 {
        unsigned long startk, begink, endk;
-       unsigned long hole_startk = 0;
        unsigned long basek;
        struct mtrr_state mtrr_state;
 
@@ -291,6 +290,8 @@ static void init_ecc_memory(unsigned node_id)
        endk   = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
+       unsigned long hole_startk = 0;
+
        #if CONFIG_K8_REV_F_SUPPORT == 0
         if (!is_cpu_pre_e0())
        {

diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index a80c0922c05418dbcdcb02d4cf76340d1678eb3e..492ee8fac0f74a25bd690406448825e4fd6a9d1a 100644 (file)
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -25,7 +25,7 @@
 ;*     SetDelayControl
 ;*
 ;*************************************************************************/
-void SetDelayControl(void)
+static void SetDelayControl(void)
 {
        unsigned int msrnum, glspeed;
        unsigned char spdbyte0, spdbyte1;

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index af9d56871aa1a825a6d958dc4bc73de94fe3e022..8a7ecbc54c2dba7412e3918759378e5100d8d5d8 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -4,37 +4,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
-#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
-# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
-#endif
-#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
-# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
-#endif
-#if !defined(CONFIG_RAMTOP)
-# error "CONFIG_RAMTOP not defined"
-#endif
-
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
-# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
-#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
-# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
-#endif
-
-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
-#if defined(CONFIG_XIP_ROM_SIZE)
-# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-   extern unsigned long AUTO_XIP_ROM_BASE;
-#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-# else
-#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-# endif
-#endif
-
+#if 0
 static void disable_var_mtrr(unsigned reg)
 {
        /* The invalid bit is kept in the mask so we simply
@@ -45,6 +15,7 @@ static void disable_var_mtrr(unsigned reg)
        zero.lo = zero.hi = 0;
        wrmsr(MTRRphysMask_MSR(reg), zero);
 }
+#endif
 
 static void set_var_mtrr(
        unsigned reg, unsigned base, unsigned size, unsigned type)
@@ -61,6 +32,7 @@ static void set_var_mtrr(
        wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+#if 0
 static void set_var_mtrr_x(
         unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
 
@@ -79,6 +51,7 @@ static void set_var_mtrr_x(
        }
         wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
+#endif
 
 static void cache_lbmem(int type)
 {

diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 55d39382dbd6fa751c568042621065b050c6935f..be27f1d9eac60965f0b4ca4d25bd6d781e73ed52 100644 (file)
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2004 Eric W. Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #ifndef CPU_X86_CACHE
 #define CPU_X86_CACHE
 
@@ -17,6 +36,7 @@ static inline void invd(void)
 {
        asm volatile("invd" ::: "memory");
 }
+
 static inline void wbinvd(void)
 {
        asm volatile ("wbinvd");

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 2da2beefc92a31bff67d6cf5277fb6ecf1daacf7..667c7ad9169d4b99cac89de90ba1fd6954ced316 100644 (file)
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -31,7 +31,6 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
-
 #if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
@@ -42,5 +41,39 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);
 #endif
 
+/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
+#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
+# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
+#endif
+#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
+# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
+#endif
+#if !defined(CONFIG_RAMTOP)
+# error "CONFIG_RAMTOP not defined"
+#endif
+
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
+#endif
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
+# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
+#endif
+
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
+#endif
+
+
+#if !defined (ASSEMBLY)
+#if defined(CONFIG_XIP_ROM_SIZE)
+# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+   extern unsigned long AUTO_XIP_ROM_BASE;
+#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+# else
+#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+# endif
+#endif
+
+#endif
 
 #endif /* CPU_X86_MTRR_H */

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index a167228b4470df89e9ff24bb47e0f5f53fd9ec50..3ae2d7663d3721770a68fdbd6697ab3b624d4478 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -58,18 +58,13 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 
 #include <console/loglevel.h>
-#if 0
-void die(const char *msg);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
-#endif
-#define printk(BIOS_INFO, fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
 #include "cpu/x86/bist.h"
 
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #include "southbridge/amd/rs780/rs780_early_setup.c"

diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index b45e4f671641b894bb88d368d90bbd89df3cb9ce..8bc3c0aaf3d1f57f7911edc531a7531953b6ea8b 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -29,20 +29,11 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if 0 
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
 #include "pc80/serial.c"
 #include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 
@@ -54,7 +45,8 @@ static void post_code(uint8_t value) {
 #include "lib/delay.c"
 
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index 29305bbcda63c543061a45b69aa50ef22d8eb3c1..8be47f79a22b5d686080ff4c24f2c7b085fe5706 100644 (file)
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
        static const char productid[12] = "A8N-E      ";
        struct mp_config_table *mc;
        unsigned sbdn;
-       int i, bus_num;
+       int bus_num;
 
        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
        memset(mc, 0, sizeof(*mc));

diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index eb8ad4f777c7ff4d263964a9247e2a24ae1a5ed3..6f3129941a7d6eacd22beca0e7578f499d31cd68 100644 (file)
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -96,7 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-       unsigned value;
        uint32_t dword;
        uint8_t byte;
 

diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 7f57ddcb1c52f13c09e098bf1a0c62d85c289397..320f23682c7ff16f68cf831ae496f889fdca5269 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -187,7 +187,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        int needs_reset = 0;
        struct sys_info *sysinfo =
            (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-       char *p;
 
        sio_init();
        w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

diff --git a/src/mainboard/intel/d945gclf/Makefile.inc b/src/mainboard/intel/d945gclf/Makefile.inc
index a74b1d7552907ade60e121bd7a740a225d1dab9c..a155c7284fd9c7f16f2e12dac5ecd7fd809684a9 100644 (file)
--- a/src/mainboard/intel/d945gclf/Makefile.inc
+++ b/src/mainboard/intel/d945gclf/Makefile.inc
@@ -17,11 +17,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc
index b6c9383f30334214e3f740fa2e321e9276d6d1fe..b6a23660c811c2fd27d43cbc1dd18ca982f6704f 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/Makefile.inc
+++ b/src/mainboard/kontron/986lcd-m/Makefile.inc
@@ -17,11 +17,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc
index fbf51bc990a85ce15c7f3f7ea33706b8962a3639..cf0241dd5d9ecc45ba616fa39a28baef6f9f04c8 100644 (file)
--- a/src/mainboard/roda/rk886ex/Makefile.inc
+++ b/src/mainboard/roda/rk886ex/Makefile.inc
@@ -17,13 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += m3885.o
 obj-y += ec.o
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 229db170dcf4a02e4488e395b752fef26a7eb8b2..fdfe751ecc5e3f8e5b8c7804e1cc757885a072c3 100644 (file)
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -56,7 +56,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18
-        int ret;
         unsigned device=(ctrl->channel0[0])>>8;
         smbus_write_byte(SMBUS_HUB, 0x01, device);
         smbus_write_byte(SMBUS_HUB, 0x03, 0);

diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 8b1b0a0af1b6a02a144e3871374f649ebac5f433..661e5f348e043be1f60196ecb22fefd29036def8 100644 (file)
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -520,6 +520,8 @@ struct sys_info {
 
 #include <reset.h>
 
+#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
+       ((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
@@ -585,5 +587,6 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
        }
 
 }
+#endif
 
 #endif /* AMDK8_F_H */

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 1b40eb1381b2eaf47cd4fe7e9756e6e30dcae25a..18b3109cf6a005b46b51968127c6a812d10be8cf 100644 (file)
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -110,7 +110,7 @@ static void misc_control_init(struct device *dev)
 {
        uint32_t cmd, cmd_ref;
        int needs_reset;
-       struct device *f0_dev, *f2_dev;
+       struct device *f0_dev;
        
        printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
        needs_reset = 0;
@@ -161,6 +161,7 @@ static void misc_control_init(struct device *dev)
                }
        }
        else if(is_cpu_pre_d0()) {
+               struct device *f2_dev;
                uint32_t dcl;
                f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
                /* Errata 98 

diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index b02e9a0058bbddb4176a838035dee86f65d08801..577e7fd4bb2b889c16266c920fc8e37ff8dce883 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -18,10 +18,6 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#if defined (__GNUC__)
-static void hard_reset(void);
-#endif
-
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
        int i;

diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index e34187154c9632526602d4858248d38ac3645241..cac9f800977e2cb8e4299c5c0bfed3900e8232f2 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -707,12 +707,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
        printk(BIOS_SPEW, "done.\n");
 }
 
+#if 0
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
        uint32_t dcl;
        dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
        return dcl & DCL_Width128;
 }
+#endif
 
 static int is_opteron(const struct mem_controller *ctrl)
 {
@@ -727,6 +729,7 @@ static int is_opteron(const struct mem_controller *ctrl)
        return !!(nbcap & NBCAP_128Bit);
 }
 
+#if 0
 static int is_registered(const struct mem_controller *ctrl)
 {
        /* Test to see if we are dealing with registered SDRAM.
@@ -737,7 +740,7 @@ static int is_registered(const struct mem_controller *ctrl)
        dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
        return !(dcl & DCL_UnBuffDimm);
 }
-
+#endif
 
 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 {
@@ -2481,6 +2484,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
        pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
 static void set_SlowAccessMode(const struct mem_controller *ctrl)
 {
        uint32_t dch;
@@ -2491,6 +2495,7 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl)
 
        pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
+#endif
 
 /*
        DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20

diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 3372474ac519f757b84c170a11be9585779ab641..5cd6d53688725b089e9d556722a0bc2b275f29f7 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1872,6 +1872,7 @@ static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
        return pos;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 {
        /* 30 bytes per channel */
@@ -1902,6 +1903,7 @@ static void dqs_save_MC_NVRAM(unsigned int dev)
        reg = pci_read_config32(dev, DRAM_CONFIG_HIGH);
        pos = s3_save_nvram_early(reg, 4, pos);
 }
+#endif
 
 static void dqs_restore_MC_NVRAM(unsigned int dev)
 {

diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 68fd0bfdbe0e9126a2e76d5f712d38c2e4ef5867..bf7a817c801bb8e78fae68a27d5f6aae08b760be 100644 (file)
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -35,7 +35,7 @@ static void banner(const char *s)
        print_debug("======================================\n");
 }
 
-void hcf(void)
+static void hcf(void)
 {
        print_emerg("DIE\n");
        /* this guarantees we flush the UART fifos (if any) and also 

diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
index 0e34c31c1e79c87619cc83bff65971fd9bbc67f4..5490777d42a6c9cc885faa86f83395e53adbc681 100644 (file)
--- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
+++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
@@ -35,7 +35,7 @@ static void enable_cf9(void)
        enable_cf9_x(sbbusn, sbdn);
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
         set_bios_reset();
         /* reset */
@@ -68,7 +68,7 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 
        unsigned sblk = get_sblk();

diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/cs5536_ide.c
index 4acf3ed61ae828f28fcc66a70f54d90eae001f7c..c4cc652e938914d9ce03b5e03a473ad0a5e2bd3d 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536_ide.c
+++ b/src/southbridge/amd/cs5536/cs5536_ide.c
@@ -46,13 +46,6 @@ static void ide_init(struct device *dev)
        pci_write_config32(dev, IDE_CFG, ide_cfg);
 }
 
-static void ide_enable(struct device *dev)
-{
-
-       printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
-
-}
-
 static struct device_operations ide_ops = {
        .read_resources = pci_dev_read_resources,
        .set_resources = pci_dev_set_resources,

diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/rs780_early_setup.c
index 72ac730cb08958cf4424eb4d9680b2af9d2f1cb7..2ebda9a7dabba203ce2e27f8dc3b874b7b5fada7 100644 (file)
--- a/src/southbridge/amd/rs780/rs780_early_setup.c
+++ b/src/southbridge/amd/rs780/rs780_early_setup.c
@@ -371,10 +371,9 @@ static void k8_optimization(void)
 #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1               /* save some spaces */
-void fam10_optimization(void)
+static void fam10_optimization(void)
 {
        device_t cpu_f0, cpu_f2, cpu_f3;
-       msr_t msr;
        u32 val;
 
        printk(BIOS_INFO, "fam10_optimization()\n");
@@ -634,16 +633,16 @@ static void rs780_por_init(device_t nb_dev)
 }
 
 /* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs780_dev8()
+static void enable_rs780_dev8(void)
 {
        set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
 }
 
-static void rs780_before_pci_init()
+static void rs780_before_pci_init(void)
 {
 }
 
-static void rs780_early_setup()
+static void rs780_early_setup(void)
 {
        device_t nb_dev = PCI_DEV(0, 0, 0);
        printk(BIOS_INFO, "rs780_early_setup()\n");

diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c
index 7ba2a7d26404c66351c6b7d6f6dc7c67cb6f8e9a..ec3f94c7bc4a502efe9f21b1daaacab392ccdcd5 100644 (file)
--- a/src/southbridge/amd/sb700/sb700_smbus.c
+++ b/src/southbridge/amd/sb700/sb700_smbus.c
@@ -205,7 +205,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr,
 /* space = 0: AX_INDXC, AX_DATAC
  * space = 1: AX_INDXP, AX_DATAP
  */
-static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
                          u32 mask, u32 val)
 {
        u32 tmp;

diff --git a/src/southbridge/amd/sb700/sb700_smbus.h b/src/southbridge/amd/sb700/sb700_smbus.h
index 07166a5b52d294e3e95b7632e139294f03e21677..6acfa9909045eb7d27ced8aa130402836fef3df5 100644 (file)
--- a/src/southbridge/amd/sb700/sb700_smbus.h
+++ b/src/southbridge/amd/sb700/sb700_smbus.h
@@ -20,8 +20,6 @@
 #ifndef SB700_SMBUS_H
 #define SB700_SMBUS_H
 
-//#include <stdint.h>
-
 #define SMBHSTSTAT 0x0
 #define SMBSLVSTAT 0x1
 #define SMBHSTCTRL 0x2

diff --git a/src/southbridge/via/vt8237r/vt8237_fadt.c b/src/southbridge/via/vt8237r/vt8237_fadt.c
index 98dfd9a337cc7b82a1d215c99f2bbafc3881f03a..6976f4d447b1ef702903a25bfa64918f55ce421a 100644 (file)
--- a/src/southbridge/via/vt8237r/vt8237_fadt.c
+++ b/src/southbridge/via/vt8237r/vt8237_fadt.c
@@ -51,8 +51,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
        memcpy(header->asl_compiler_id, "CORE", 4);
        header->asl_compiler_revision = 42;
 
-       fadt->firmware_ctrl = facs;
-       fadt->dsdt = dsdt;
+       fadt->firmware_ctrl = (u32)facs;
+       fadt->dsdt = (u32)dsdt;
        fadt->preferred_pm_profile = 0;
        fadt->sci_int = 9;
        fadt->smi_cmd = 0;
@@ -108,9 +108,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
        fadt->reset_reg.addrh = 0x0;
 
        fadt->reset_value = 0;
-       fadt->x_firmware_ctl_l = facs;
+       fadt->x_firmware_ctl_l = (u32)facs;
        fadt->x_firmware_ctl_h = 0;
-       fadt->x_dsdt_l = dsdt;
+       fadt->x_dsdt_l = (u32)dsdt;
        fadt->x_dsdt_h = 0;
 
        fadt->x_pm1a_evt_blk.space_id = 1;