2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 static void pll_reset(char manualconf)
23 msr_t msrGlcpSysRstpll;
25 msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
27 printk(BIOS_DEBUG, "MSR GLCP_SYS_RSTPLL (%08x) value is %08x:%08x\n",
28 GLCP_SYS_RSTPLL, msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
30 post_code(POST_PLL_INIT);
32 if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
33 printk(BIOS_DEBUG, "Configuring PLL.\n");
35 post_code(POST_PLL_MANUAL);
36 /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
37 msrGlcpSysRstpll.hi = PLLMSRhi;
39 /* Hold Count - how long we will sit in reset */
40 msrGlcpSysRstpll.lo = PLLMSRlo;
42 /*automatic configuration (straps) */
43 post_code(POST_PLL_STRAP);
44 msrGlcpSysRstpll.lo &=
45 ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
46 msrGlcpSysRstpll.lo |=
47 (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
48 msrGlcpSysRstpll.lo &=
49 ~(RSTPPL_LOWER_COREBYPASS_SET |
50 RSTPPL_LOWER_MBBYPASS_SET);
51 msrGlcpSysRstpll.lo |=
52 RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
54 /* Use SWFLAGS to remember: "we've already been here" */
55 msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
57 /* "reset the chip" value */
58 msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
59 wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
61 /* You should never get here..... The chip has reset. */
62 printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n");
63 post_code(POST_PLL_RESET_FAIL);
64 __asm__ __volatile__("hlt\n");
67 printk(BIOS_DEBUG, "PLL configured.\n");
72 static unsigned int CPUSpeed(void)
77 msr = rdmsr(GLCP_SYS_RSTPLL);
78 speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
79 if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
86 static unsigned int GeodeLinkSpeed(void)
91 msr = rdmsr(GLCP_SYS_RSTPLL);
92 speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
93 if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
100 static unsigned int PCISpeed(void)
104 msr = rdmsr(GLCP_SYS_RSTPLL);
105 if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {