void console_init(void)
{
static const char console_test[] =
- "\r\n\r\ncoreboot-"
+ "\n\ncoreboot-"
COREBOOT_VERSION
COREBOOT_EXTRA_VERSION
" "
COREBOOT_BUILD
- " starting...\r\n";
+ " starting...\n";
print_info(console_test);
}
#if CONFIG_SERIAL_POST==1
print_emerg("POST: 0x");
print_emerg_hex8(value);
- print_emerg("\r\n");
+ print_emerg("\n");
#endif
outb(value, 0x80);
#endif
static inline void print_debug_pcar(const char *strval, uint32_t val)
{
- printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
+ printk(BIOS_DEBUG, "%s%08x\n", strval, val);
}
/* from linux kernel 2.6.32 asm/string_32.h */
/* We can put data to stack again */
/* only global variable sysinfo in cache need to be offset */
- print_debug("Done\r\n");
+ print_debug("Done\n");
print_debug_pcar("testx = ", testx);
- print_debug("Disabling cache as ram now \r\n");
+ print_debug("Disabling cache as ram now \n");
disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: ");
#else
memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
#endif
- print_debug("Done\r\n");
+ print_debug("Done\n");
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
copy_and_run();
/* We will not return */
- print_debug("should not be here -\r\n");
+ print_debug("should not be here -\n");
}
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
- printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n");
+ printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes);
}
static inline void print_debug_fv(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
- printk(BIOS_DEBUG, "%s%x\r\n", str, val);
+ printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
- printk(BIOS_DEBUG, "%s%02x\r\n", str, val);
+ printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
{
#if K8_SET_FIDVID_DEBUG == 1
- printk(BIOS_DEBUG, "%s%x%x\r\n", str, val, val2);
+ printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
apicidx = lapicid();
if (apicid != apicidx) {
- printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
+ printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx);
return fidvid;
}
if (showmessage) {
if (vid_new != vid_cur) {
- print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n");
+ print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
}
if (fid_new != fid_cur) {
- print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n");
+ print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
}
}
static inline void print_initcpu8 (const char *strval, unsigned val)
{
- printk(BIOS_DEBUG, "%s%02x\r\n", strval, val);
+ printk(BIOS_DEBUG, "%s%02x\n", strval, val);
}
static inline void print_initcpu8_nocr (const char *strval, unsigned val)
static inline void print_initcpu16 (const char *strval, unsigned val)
{
- printk(BIOS_DEBUG, "%s%04x\r\n", strval, val);
+ printk(BIOS_DEBUG, "%s%04x\n", strval, val);
}
static inline void print_initcpu(const char *strval, unsigned val)
{
- printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
+ printk(BIOS_DEBUG, "%s%08x\n", strval, val);
}
typedef void (*process_ap_t)(unsigned apicid, void *gp);
static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
{
- printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
+ printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
}
{
print_debug("started ap apicid: ");
for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
- print_debug("\r\n");
+ print_debug("\n");
}
static void allow_all_aps_stop(unsigned bsp_apicid)
#endif
if (cpu_init_detectedx) {
- print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from ");
- print_debug("\r\nIssuing SOFT_RESET...\r\n");
+ print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from ");
+ print_debug("\nIssuing SOFT_RESET...\n");
soft_reset();
}
while(!is_core0_started(i)) {}
print_initcpu8_nocr(" ", i);
}
- print_debug("\r\n");
+ print_debug("\n");
}
print_debug_hex32(msr.hi);
print_debug(" and lo ");
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
wrmsr(GLCP_DELAY_CONTROLS, msr);
- print_debug("SetDelayControl done\r\n");
+ print_debug("SetDelayControl done\n");
return;
}
/* Castle 2.0 BTM periodic sync period. */
/* [40:37] 1 sync record per 256 bytes */
- print_debug("Castle 2.0 BTM periodic sync period.\r\n");
+ print_debug("Castle 2.0 BTM periodic sync period.\n");
msrnum = CPU_PF_CONF;
msr = rdmsr(msrnum);
msr.hi |= (0x8 << 5);
* LX performance setting.
* Enable Quack for fewer re-RAS on the MC
*/
- print_debug("Enable Quack for fewer re-RAS on the MC\r\n");
+ print_debug("Enable Quack for fewer re-RAS on the MC\n");
msrnum = GLIU0_ARB;
msr = rdmsr(msrnum);
msr.hi &= ~ARB_UPPER_DACK_EN_SET;
/* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction.
*/
- print_debug(" GLIU port active enable\r\n");
+ print_debug(" GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE;
msr = rdmsr(msrnum);
msr.lo &= ~0x880;
wrmsr(msrnum, msr);
/* Set the Delay Control in GLCP */
- print_debug("Set the Delay Control in GLCP\r\n");
+ print_debug("Set the Delay Control in GLCP\n");
SetDelayControl();
/* Enable RSDC */
- print_debug("Enable RSDC\r\n");
+ print_debug("Enable RSDC\n");
msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum);
msr.lo |= SMM_INST_EN_SET;
wrmsr(msrnum, msr);
/* FPU imprecise exceptions bit */
- print_debug("FPU imprecise exceptions bit\r\n");
+ print_debug("FPU imprecise exceptions bit\n");
msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET;
/* Power Savers (Do after BIST) */
/* Enable Suspend on HLT & PAUSE instructions */
- print_debug("Enable Suspend on HLT & PAUSE instructions\r\n");
+ print_debug("Enable Suspend on HLT & PAUSE instructions\n");
msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
wrmsr(msrnum, msr);
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
- print_debug("Enable SUSP and allow TSC to run in Suspend\r\n");
+ print_debug("Enable SUSP and allow TSC to run in Suspend\n");
msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
#endif
/* Setup throttling delays to proper mode if it is ever enabled. */
- print_debug("Setup throttling delays to proper mode\r\n");
+ print_debug("Setup throttling delays to proper mode\n");
msrnum = GLCP_TH_OD;
msr.hi = 0;
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
- print_debug("Done cpuRegInit\r\n");
+ print_debug("Done cpuRegInit\n");
}
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
- printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
+ printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
enable_apic_ext_id(sysconf.nodes);
}
static void dumpram(void){
- print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n");
- print_err("mctl "); print_err_hex8(*drcmctl); print_err("\r\n");
- print_err("cfg "); print_err_hex8(*drccfg); print_err("\r\n");
-
- print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\r\n");
- print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\r\n");
- print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\r\n");
- print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\r\n");
+ print_err("ctl "); print_err_hex8(*drcctl); print_err("\n");
+ print_err("mctl "); print_err_hex8(*drcmctl); print_err("\n");
+ print_err("cfg "); print_err_hex8(*drccfg); print_err("\n");
+
+ print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\n");
+ print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\n");
+ print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\n");
+ print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
}
/* there is a lot of silliness in the amd code, and it is
print_err("NOP\n");
/* 100? 200? */
udelay(100);
- print_err("after sc520_udelay\r\n");
+ print_err("after sc520_udelay\n");
/* issue all banks precharge */
*drcctl=0x02;
- print_err("set *drcctl to 2 \r\n");
+ print_err("set *drcctl to 2 \n");
dummy_write();
print_err("PRE\n");
*drcctl=0x04;
for (i=0; i<8; i++) /* refresh 8 times */{
dummy_write();
- print_err("dummy write\r\n");
+ print_err("dummy write\n");
}
print_err("8 dummy writes\n");
*drcctl=0x00;
print_err("normal\n");
- print_err("HI done normal\r\n");
+ print_err("HI done normal\n");
print_err("sizemem\n");
for(bank = 3; bank >= 0; bank--) {
- print_err("Try to assign to l\r\n");
+ print_err("Try to assign to l\n");
*lp = 0xdeadbeef;
- print_err("assigned l ... \r\n");
+ print_err("assigned l ... \n");
if (*lp != 0xdeadbeef) {
print_err(" no memory at bank ");
// print_err_hex8(bank);
// print_err(" value "); print_err_hex32(*lp);
- print_err("\r\n");
+ print_err("\n");
// continue;
}
*drcctl = 2;
l = *drcbendadr;
l >>= 8;
*drcbendadr = l;
- print_err("loop around\r\n");
+ print_err("loop around\n");
*drcctl = 0;
dummy_write();
}
print_err("NOP\n");
/* 100? 200? */
//sc520_udelay(100);
- print_err("after sc520_udelay\r\n");
+ print_err("after sc520_udelay\n");
/* issue all banks precharge */
*drcctl=0x02;
- print_err("set *drcctl to 2 \r\n");
+ print_err("set *drcctl to 2 \n");
dummy_write();
print_err("PRE\n");
*drcctl=0x04;
for (i=0; i<8; i++) /* refresh 8 times */{
dummy_write();
- print_err("dummy write\r\n");
+ print_err("dummy write\n");
}
print_err("8 dummy writes\n");
*drcctl=0x00;
print_err("normal\n");
- print_err("HI done normal\r\n");
+ print_err("HI done normal\n");
bank = 3;
al -= i&3;
*drcbendaddr = rows >> al;
print_err("computed ending_adr = "); print_err_hex8(ending_adr);
- print_err("\r\n");
+ print_err("\n");
*/
bad_reinit:
return bank;
bad_ram:
- print_info("bad ram!\r\n");
+ print_info("bad ram!\n");
/* you are here because the read-after-write failed,
* in most cases because: no ram in that bank!
* set badbank to 1 and go to reinit
ending_adr = 0;
goto bad_reinit;
while(1)
- print_err("DONE NEXTBANK\r\n");
+ print_err("DONE NEXTBANK\n");
#endif
}
/* two autorefreshes */
*drcctl = 4;
*zero = 0;
- print_debug("one zero out on refresh\r\n");
+ print_debug("one zero out on refresh\n");
*zero = 0;
- print_debug("two zero out on refresh\r\n");
+ print_debug("two zero out on refresh\n");
/* load mode register */
*drcctl = 3;
*zero = 0;
- print_debug("DONE the load mode reg\r\n");
+ print_debug("DONE the load mode reg\n");
/* normal mode */
*drcctl = 0x0;
*zero = 0;
- print_debug("DONE one last write and then turn on refresh etc\r\n");
+ print_debug("DONE one last write and then turn on refresh etc\n");
*drcctl = 0x18;
*zero = 0;
- print_debug("DONE the normal\r\n");
+ print_debug("DONE the normal\n");
*zero = 0xdeadbeef;
if (*zero != 0xdeadbeef)
- print_debug("NO LUCK\r\n");
+ print_debug("NO LUCK\n");
else
- print_debug("did a store and load ...\r\n");
+ print_debug("did a store and load ...\n");
//print_err_hex32(*zero);
- // print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
+ // print_err(" zero is now "); print_err_hex32(*zero); print_err("\n");
}
print_debug_hex32(pf);
print_debug(" rev = 0x");
print_debug_hex32(rev);
- print_debug("\r\n");
+ print_debug("\n");
m = microcode_updates;
for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
print_debug_hex32(new_rev);
print_debug(" from revision ");
print_debug_hex32(rev);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
if (m->total_size) {
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
- printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp);
+ printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
}
- printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset);
+ printk(BIOS_SPEW, "cpu_reset = %08x\n",cpu_reset);
if(cpu_reset == 0) {
print_spew("Clearing initial memory region: ");
#ifdef CONFIG_DEACTIVATE_CAR
print_debug("Deactivating CAR");
#include CONFIG_DEACTIVATE_CAR_FILE
- print_debug(" - Done.\r\n");
+ print_debug(" - Done.\n");
#endif
/* Copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
- print_debug("sorry. parachute did not open.\r\n");
+ print_debug("sorry. parachute did not open.\n");
}
#endif
#if 0
- printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
+ printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
#endif
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
return ;
found:
- printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
+ printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
#if 0
if (M64_HAS(INTEGRATED)) {
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
unsigned char byte;
status = smbus_read_byte(dev, j);
if (status < 0) {
- // printk(BIOS_DEBUG, "bad device status= %08x\r\n", status);
+ // printk(BIOS_DEBUG, "bad device status= %08x\n", status);
break;
}
if ((j & 0xf) == 0) {
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
}
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- printk(BIOS_DEBUG, "\r\n");
+ printk(BIOS_DEBUG, "\n");
}
static void print_smbus_regs_all(struct device *dev)
result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
if (!(result & CFG1_RDY)) {
- printk(BIOS_DEBUG, "ADM1027: monitoring not ready\r\n");
+ printk(BIOS_DEBUG, "ADM1027: monitoring not ready\n");
return;
}
result = (result | CFG1_STRT);
result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
if (!(result & CFG1_STRT)) {
- printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\r\n");
+ printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\n");
}
- printk(BIOS_DEBUG, "ADM1027: monitoring enabled\r\n");
+ printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n");
}
static void adm1027_init(device_t dev)
print_emerg(__FILE__); \
print_emerg("', line 0x"); \
print_debug_hex32(__LINE__); \
- print_emerg("\r\n"); \
+ print_emerg("\n"); \
/* die(""); */ \
} \
}
print_emerg(__FILE__); \
print_emerg("', line 0x"); \
print_debug_hex32(__LINE__); \
- print_emerg("\r\n"); \
+ print_emerg("\n"); \
/* die(""); */ \
}
print_emerg("BIST failed: ");
print_emerg_hex32(bist);
#endif
- die("\r\n");
+ die("\n");
}
}
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = spd_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = spd_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%s%02x\n", strval, val);
#else
- print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
+ print_debug(strval); print_debug_hex8(val); print_debug("\n");
#endif
}
* Some chipsets do the work for us while on others
* we need to it by hand.
*/
- print_debug("Ram3\r\n");
+ print_debug("Ram3\n");
#if RAMINIT_SYSINFO == 1
sdram_enable(controllers, ctrl, sysinfo);
sdram_enable(controllers, ctrl);
#endif
- print_debug("Ram4\r\n");
+ print_debug("Ram4\n");
}
* Fill.
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop);
+ printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM fill: ");
print_debug_hex32(start);
print_debug("-");
print_debug_hex32(stop);
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(addr = start; addr < stop ; addr += 4) {
/* Display address being filled */
};
/* Display final address */
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "%08lx\r\nDRAM filled\r\n", addr);
+ printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr);
#else
print_debug_hex32(addr);
- print_debug("\r\nDRAM filled\r\n");
+ print_debug("\nDRAM filled\n");
#endif
}
* Verify.
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop);
+ printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM verify: ");
print_debug_hex32(start);
print_debug_char('-');
print_debug_hex32(stop);
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(addr = start; addr < stop ; addr += 4) {
unsigned long value;
if (value != addr) {
/* Display address with error */
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value);
+ printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value);
#else
print_err("Fail: @0x");
print_err_hex32(addr);
print_err(" Read value=0x");
print_err_hex32(value);
- print_err("\r\n");
+ print_err("\n");
#endif
i++;
if(i>256) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "Aborting.\n\r");
+ printk(BIOS_DEBUG, "Aborting.\n");
#else
- print_debug("Aborting.\n\r");
+ print_debug("Aborting.\n");
#endif
break;
}
if (i) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\nDRAM did _NOT_ verify!\r\n");
+ printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
#else
- print_debug("\r\nDRAM did _NOT_ verify!\r\n");
+ print_debug("\nDRAM did _NOT_ verify!\n");
#endif
die("DRAM ERROR");
}
else {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\nDRAM range verified.\r\n");
+ printk(BIOS_DEBUG, "\nDRAM range verified.\n");
#else
- print_debug("\r\nDRAM range verified.\r\n");
+ print_debug("\nDRAM range verified.\n");
#endif
}
}
* are tested. -Tyson
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\r\n", start, stop);
+ printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
#else
print_debug("Testing DRAM : ");
print_debug_hex32(start);
print_debug("-");
print_debug_hex32(stop);
- print_debug("\r\n");
+ print_debug("\n");
#endif
ram_fill(start, stop);
/* Make sure we don't read before we wrote */
phys_memory_barrier();
ram_verify(start, stop);
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "Done.\r\n");
+ printk(BIOS_DEBUG, "Done.\n");
#else
- print_debug("Done.\r\n");
+ print_debug("Done.\n");
#endif
}
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
post_code(0x06);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
/* get module banks (sides) per dimm, SPD byte 5 */
module_banks = spd_read_byte(0xA0, 5);
if (module_banks < 1 || module_banks > 2)
- print_err("Module banks per dimm\r\n");
+ print_err("Module banks per dimm\n");
module_banks >>= 1;
msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
/* get component banks per module bank, SPD byte 17 */
val = spd_read_byte(0xA0, 17);
if (val < 2 || val > 4)
- print_err("Component banks per module bank\r\n");
+ print_err("Component banks per module bank\n");
val >>= 2;
msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
print_debug("computed msr.hi ");
print_debug_hex32(msr.hi);
- print_debug("\r\n");
+ print_debug("\n");
msr.lo = 0x00003000;
wrmsr(MC_CF07_DATA, msr);
#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
#else
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
#endif
train_ram(id.nodeid, sysinfo, sysinfox);
{
#define SMBUS_HUB 0x18
int ret, i;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
} while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
#endif
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int n;
for(n = 0; n < controllers; n++) {
int i;
- print_debug("\r\n");
+ print_debug("\n");
activate_spd_rom(&ctrl[n]);
for(i = 0; i < 4; i++) {
unsigned device;
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = spd_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
#if 0
#endif
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl[n].channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = spd_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
#if 0
#endif
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset \r\n");
+ print_debug("soft reset \n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
console_init();
enable_rom_decode();
- print_info("now booting... fallback\r\n");
+ print_info("now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
console_init();
enable_rom_decode();
- print_info("now booting... real_main\r\n");
+ print_info("now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\r\n");
+ print_info("now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched. */
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\r\n");
+ print_debug("ht reset -\n");
soft_reset();
}
/* this function might fail on some K8 CPUs with errata #181 */
static void ldtstop_sb(void)
{
- print_debug("toggle LDTSTP#\r\n");
+ print_debug("toggle LDTSTP#\n");
u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
reg = reg ^ (1 << 0);
outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
- print_debug("done\r\n");
+ print_debug("done\n");
}
#include "cpu/amd/model_fxx/fidvid.c"
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset \r\n");
+ print_debug("soft reset \n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
console_init();
enable_rom_decode();
- print_info("now booting... real_main\r\n");
+ print_info("now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\r\n");
+ print_info("now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched. */
if (needs_reset) {
print_debug_hex8(needs_reset);
- print_debug("Xht reset -\r\n");
+ print_debug("Xht reset -\n");
soft_reset();
- print_debug("NO reset\r\n");
+ print_debug("NO reset\n");
}
vt8237_sb_enable_fid_vid();
enable_fid_change();
- print_debug("after enable_fid_change\r\n");
+ print_debug("after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
uart_init();
console_init();
- print_spew("In romstage.c:main()\r\n");
+ print_spew("In romstage.c:main()\n");
enable_smbus();
smbus_fixup(&ctrl);
if (bist == 0) {
- print_debug("doing early_mtrr\r\n");
+ print_debug("doing early_mtrr\n");
early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
- print_spew("Leaving romstage.c:main()\r\n");
+ print_spew("Leaving romstage.c:main()\n");
}
{
#define SMBUS_HUB 0x71
int ret;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
ret = smbus_send_byte(SMBUS_HUB, device);
- print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
}
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_blast_resource_map();
bcm5785_early_setup();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
print_debug("present: ");
}
print_debug_hex8(status);
- print_debug("\r\n");
+ print_debug("\n");
device += SMBUS_MEM_DEVICE_INC;
print_debug("\n");
}
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
{
// disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog();
- print_debug("Watchdogs disabled\r\n");
+ print_debug("Watchdogs disabled\n");
}
print_err_hex8(c);
print_err(" ");
}
- print_err("\r\n");
+ print_err("\n");
}
}
uart_init();
console_init();
for(i = 0; i < 100; i++)
- print_err("fill usart\r\n");
+ print_err("fill usart\n");
// while(1)
- print_err("HI THERE!\r\n");
+ print_err("HI THERE!\n");
// sizemem();
staticmem();
print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60);
print_err("\n");
// while(1)
- print_err("STATIC MEM DONE\r\n");
+ print_err("STATIC MEM DONE\n");
outb(0xee, 0x80);
print_err("loop forever ...\n");
#endif
#if 0
- print_err("RAM CHECK!\r\n");
+ print_err("RAM CHECK!\n");
// Check 16MB of memory @ 0
ram_check(0x00000000, 0x01000000);
#endif
#if 0
- print_err("RAM CHECK for 32 MB!\r\n");
+ print_err("RAM CHECK for 32 MB!\n");
// Check 32MB of memory @ 0
ram_check(0x00000000, 0x02000000);
#endif
for(i = 0; i < 0x20000; i++) {
/*
print_err("Set dst "); print_err_hex32((unsigned long) dst);
- print_err(" to "); print_err_hex32(*src); print_err("\r\n");
+ print_err(" to "); print_err_hex32(*src); print_err("\n");
*/
*dst = *src;
- //print_err(" dst is now "); print_err_hex32(*dst); print_err("\r\n");
+ //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
dst++, src++;
outb((unsigned char)i, 0x80);
}
}
dumpmem();
outb(0, 0x80);
- print_err("loop forever\r\n");
+ print_err("loop forever\n");
outb(0xdd, 0x80);
__asm__ volatile(
"movl %0, %%edi\n\t"
: "a" (0x4000)
);
- print_err("Oh dear, I'm afraid it didn't work...\r\n");
+ print_err("Oh dear, I'm afraid it didn't work...\n");
while(1);
#endif
id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
/* set gpio 42,44 signal levels */
data = inb(gpio_index + PC87427_GPDO_4);
if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
- print_debug("set_pllsel: correct settings detected!\r\n");
+ print_debug("set_pllsel: correct settings detected!\n");
return; /* settings already configured */
} else {
outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
/* reset */
- print_debug("set_pllsel: settings adjusted, now resetting...\r\n");
+ print_debug("set_pllsel: settings adjusted, now resetting...\n");
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
// mch_reset();
full_reset();
cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
print_debug("Boot byte = ");
print_debug_hex8(cmos);
- print_debug("\r\n");
+ print_debug("\n");
if((cmos>2)&&(cmos&1)) full_reset();
}
disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog();
disable_jarell_frb3();
- print_debug("Watchdogs disabled\r\n");
+ print_debug("Watchdogs disabled\n");
}
static void ich5_watchdog_on(void)
value &= ~(1 << 11);
outw(value, base + 0x08);
- print_debug("Watchdog ICH5 enabled\r\n");
+ print_debug("Watchdog ICH5 enabled\n");
}
// NOTE: ROMCC dies with an internal compiler error
// if the following line is removed.
- print_debug("SDRAM is up.\r\n");
+ print_debug("SDRAM is up.\n");
}
setup_mb_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
setup_default_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
setup_default_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
uart_init();
console_init();
- print_spew("In romstage.c:main()\r\n");
+ print_spew("In romstage.c:main()\n");
enable_smbus();
smbus_fixup(&ctrl);
if (bist == 0) {
- print_debug("doing early_mtrr\r\n");
+ print_debug("doing early_mtrr\n");
early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
- print_spew("Leaving romstage.c:main()\r\n");
+ print_spew("Leaving romstage.c:main()\n");
}
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
msr_t msr;
/* 1. Initialize GLMC registers base on SPD values,
* Hard coded as XpressROM for now */
- //print_debug("sdram_enable step 1\r\n");
+ //print_debug("sdram_enable step 1\n");
msr = rdmsr(0x20000018);
msr.hi = 0x10076013;
msr.lo = 0x3400;
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
print_err("ERROR: spd_read_byte(DIMM0, 0x");
print_err_hex8(address);
- print_err(") returns 0xff\r\n");
+ print_err(") returns 0xff\n");
}
#endif
if ((err = smc_send_config(SMC_CONFIG))) {
print_err("ERROR ");
print_err_char('0'+err);
- print_err(" sending config data to SMC\r\n");
+ print_err(" sending config data to SMC\n");
}
sdram_initialize(1, memctrl);
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
*/
print_debug("CODE IN CACHE ON NODE:");
print_debug_hex8(id.nodeid);
- print_debug("\r\n");
+ print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
- print_debug("\r\n");
+ print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
enable_fid_change();
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_coherent_ht_domain();
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
#endif
needs_reset |= mcp55_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
print_debug("computed msr.hi ");
print_debug_hex32(msr.hi);
- print_debug("\r\n");
+ print_debug("\n");
/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
/* well, it may be close. It's about 200,000 ticks */
print_debug("computed msr.hi ");
print_debug_hex32(msr.hi);
- print_debug("\r\n");
+ print_debug("\n");
/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
/* well, it may be close. It's about 200,000 ticks */
print_debug_hex8(address);
print_debug(" returns ");
print_debug_hex8(spdbytes[address]);
- print_debug("\r\n");
+ print_debug("\n");
return spdbytes[address];
}
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
id = get_node_core_id_x();
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
{
u32 device;
- print_debug("\r\n");
+ print_debug("\n");
for (device = 1; device < 0x80; device++) {
int j;
if (smbus_read_byte(device, 0) < 0)
break;
}
if ((j & 0xf) == 0) {
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
}
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f);
int ret;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
dump_smbus_registers();
ret = smbus_send_byte(SMBUS_SWITCH1, device);
- print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
dump_smbus_registers();
ret = smbus_send_byte_one(SMBUS_SWITCH2, device);
- print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
dump_smbus_registers();
}
*/
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
- print_debug("\r\n");
+ print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
#endif
id = get_node_core_id_x();
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
setup_mb_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
#endif
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
static void disable_watchdogs(void)
{
disable_esb6300_watchdog();
- print_debug("Watchdogs disabled\r\n");
+ print_debug("Watchdogs disabled\n");
}
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
// disable_sio_watchdog(NSC_WD_DEV);
disable_esb6300_watchdog();
// disable_jarell_frb3();
- print_debug("Watchdogs disabled\r\n");
+ print_debug("Watchdogs disabled\n");
}
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
// disable_sio_watchdog(NSC_WD_DEV);
disable_esb6300_watchdog();
// disable_jarell_frb3();
- print_debug("Watchdogs disabled\r\n");
+ print_debug("Watchdogs disabled\n");
}
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
// disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog();
// disable_jarell_frb3();
- print_debug("Watchdogs disabled\r\n");
+ print_debug("Watchdogs disabled\n");
}
print_debug_hex8(index);
print_debug(": 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
return;
}
int i;
unsigned char data;
- print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\r\n*** GPIO VALUES ***\r\n");
+ print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\r\nGPDO 4: 0x");
+ print_debug("\nGPDO 4: 0x");
print_debug_hex8(data);
data = inb(0x68b);
- print_debug("\r\nGPDI 4: 0x");
+ print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
- print_debug("\r\n");
+ print_debug("\n");
#if 0
- print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
print_reg(0xfe);
print_reg(0xff);
- print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\r\n");
+ print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
val = pci_read_config8(dev, i);
#endif
if((i%4)==0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug_char(' ');
}
print_debug_hex32(read32(bar + i));
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\r\n");
+ print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
if (status < 0) {
print_debug("bad device: ");
print_debug_hex8(-status);
- print_debug("\r\n");
+ print_debug("\n");
break;
}
print_debug_hex8(status);
// disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog();
// disable_jarell_frb3();
- print_debug("Watchdogs disabled\r\n");
+ print_debug("Watchdogs disabled\n");
}
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
TS9500_LED_ON;
- print_err("TS-9500 add-on found:\r\n");
+ print_err("TS-9500 add-on found:\n");
val=inb(0x19b);
for (i=0; i<8; i++) {
print_err(" DIP");
print_err_char(i+0x31);
print_err(": ");
if((val&(1<<i))!=0)
- print_err("on\r\n");
+ print_err("on\n");
else
- print_err("off\r\n");
+ print_err("off\n");
}
- print_err("\r\n");
+ print_err("\n");
val=inb(0x19a);
print_err_char(i+0x30-5);
print_err(": ");
if((val&(1<<i))!=0)
- print_err("on\r\n");
+ print_err("on\n");
else
- print_err("off\r\n");
+ print_err("off\n");
}
- print_err("\r\n");
+ print_err("\n");
TS9500_LED_OFF;
}
print_err("Mainboard: ");
val=inb(0x74);
switch(val) {
- case 0x50: print_err("TS-5300\r\n"); break;
- case 0x40: print_err("TS-5400\r\n"); break;
- case 0x60: print_err("TS-5500\r\n"); break;
- case 0x20: print_err("TS-5600\r\n"); break;
- case 0x70: print_err("TS-5700\r\n"); break;
- default: print_err("unknown\r\n"); break;
+ case 0x50: print_err("TS-5300\n"); break;
+ case 0x40: print_err("TS-5400\n"); break;
+ case 0x60: print_err("TS-5500\n"); break;
+ case 0x20: print_err("TS-5600\n"); break;
+ case 0x70: print_err("TS-5700\n"); break;
+ default: print_err("unknown\n"); break;
}
val=inb(0x75);
print_err(" SRAM option: ");
if((val&1)==0) print_err("not ");
- print_err("installed\r\n");
+ print_err("installed\n");
print_err(" RS-485 option: ");
if((val&2)==0) print_err("not ");
- print_err("installed\r\n");
+ print_err("installed\n");
val=inb(0x76);
print_err(" Temp. range: ");
- if((val&2)==0) print_err("commercial\r\n");
- else print_err("industrial\r\n");
+ if((val&2)==0) print_err("commercial\n");
+ else print_err("industrial\n");
- print_err("\r\n");
+ print_err("\n");
val=inb(0x77);
for (i=1; i<8; i++) {
print_err_char(i+0x30);
print_err(": ");
if((val&(1<<i))!=0)
- print_err("on\r\n");
+ print_err("on\n");
else
- print_err("off\r\n");
+ print_err("off\n");
}
- print_err("\r\n");
+ print_err("\n");
/* Detect TS-9500 */
val=inb(0x19d);
console_init();
- print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\r\n");
+ print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n");
staticmem();
- print_err("Memory initialized: 32MB\r\n");
+ print_err("Memory initialized: 32MB\n");
#if 1
identify_system();
#if 0
// Check 32MB of memory @ 0 (very slow!)
- print_err("Checking memory:\r\n");
+ print_err("Checking memory:\n");
ram_check(0x00000000, 0x000a0000);
ram_check(0x000b0000, 0x02000000);
#endif
: "=a" (v_esp)
);
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
+ printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
#else
- print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
+ print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\n");
#endif
}
cpu_reset_x:
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset);
+ printk(BIOS_DEBUG, "cpu_reset = %08x\n",cpu_reset);
#else
- print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
+ print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\n");
#endif
if(cpu_reset == 0) {
/* We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
- print_debug("Use Ram as Stack now - done\r\n");
+ print_debug("Use Ram as Stack now - done\n");
} else
{
- print_debug("Use Ram as Stack now - \r\n");
+ print_debug("Use Ram as Stack now - \n");
}
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
+ printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
#else
- print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
+ print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\n");
#endif
#ifdef DEACTIVATE_CAR
print_debug("Deactivating CAR");
#include DEACTIVATE_CAR_FILE
- print_debug(" - Done.\r\n");
+ print_debug(" - Done.\n");
#endif
/*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
}
#endif
- print_debug("should not be here -\r\n");
+ print_debug("should not be here -\n");
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\r\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
{
#define SMBUS_HUB 0x18
int ret;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
{
#define SMBUS_HUB 0x18
int ret, i;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
} while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
uart_init();
console_init();
- print_spew("In romstage.c:main()\r\n");
+ print_spew("In romstage.c:main()\n");
enable_smbus();
smbus_fixup(&ctrl);
if (bist == 0) {
- print_debug("doing early_mtrr\r\n");
+ print_debug("doing early_mtrr\n");
early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
- print_spew("Leaving romstage.c:main()\r\n");
+ print_spew("Leaving romstage.c:main()\n");
}
enable_smbus();
- print_spew("In romstage.c:main()\r\n");
+ print_spew("In romstage.c:main()\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
outb(5, 0x80);
- print_debug(" Enabling mainboard devices\r\n");
+ print_debug(" Enabling mainboard devices\n");
enable_mainboard_devices();
- print_debug(" Enabling shadow ram\r\n");
+ print_debug(" Enabling shadow ram\n");
enable_shadow_ram();
ddr_ram_setup((const struct mem_controller *)0);
#endif
if (bist == 0) {
- print_debug(" Doing MTRR init.\r\n");
+ print_debug(" Doing MTRR init.\n");
early_mtrr_init();
}
//dump_pci_devices();
- print_spew("Leaving romstage.c:main()\r\n");
+ print_spew("Leaving romstage.c:main()\n");
}
device_t dev;
u16 tmp, result;
- print_debug("In acpi_is_wakeup_early_via_vx800\r\n");
+ print_debug("In acpi_is_wakeup_early_via_vx800\n");
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\r\n");
+ die("Power management controller not found\n");
/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
print_debug(" boot_mode=");
print_debug_hex16(result);
- print_debug("\r\n");
+ print_debug("\n");
return result;
}
pci_write_config8(dev, 0x5b, 0x01);
#endif
- print_debug("In enable_mainboard_devices \r\n");
+ print_debug("In enable_mainboard_devices \n");
/* Enable P2P Bridge Header for external PCI bus. */
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
* early_mtrr_init() call.
*/
#if 0
- print_debug("doing early_mtrr\r\n");
+ print_debug("doing early_mtrr\n");
early_mtrr_init();
#endif
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
/*
Data = pci_read_config8(device, 0xf6);
print_debug("NB chip revision =");
print_debug_hex8(Data);
- print_debug("\r\n");
+ print_debug("\n");
/* Make NB ready before DRAM init. */
via_pci_inittable(Data, mNbStage1InitTbl);
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
DRAM_SYS_ATTR DramAttr;
- print_debug("This is an S3 wakeup\r\n");
+ print_debug("This is an S3 wakeup\n");
memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
/*
/* Just copy this function from draminit to here! */
SetUMARam();
- print_debug("Resume from S3, RAM init was ignored\r\n");
+ print_debug("Resume from S3, RAM init was ignored\n");
} else {
ddr2_ram_setup();
ram_check(0, 640 * 1024);
);
#endif
/* This can have function call, because no variable used before this. */
- print_debug("Copy memory to high memory to protect s3 wakeup vector code \r\n");
+ print_debug("Copy memory to high memory to protect s3 wakeup vector code \n");
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
0x100000), (unsigned char *)0, 0xa0000);
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
unsigned v_esp;
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
+ printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
#else
print_debug("v_esp=");
print_debug_hex32(v_esp);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
#endif
cpu_reset = 0;
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
+ printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
#else
print_debug("cpu_reset = ");
print_debug_hex32(cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
if (cpu_reset == 0)
/* We can't go back anymore, we lost old stack data in CAR. */
if (new_cpu_reset == 0)
- print_debug("Use Ram as Stack now - done\r\n");
+ print_debug("Use Ram as Stack now - done\n");
else
- print_debug("Use Ram as Stack now - \r\n");
+ print_debug("Use Ram as Stack now - \n");
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
+ printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = ");
print_debug_hex32(new_cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
jason_tsc_count_car();
}
#endif
- print_debug("should not be here -\r\n");
+ print_debug("should not be here -\n");
}
uart_init();
console_init();
- print_spew("In romstage.c:main()\r\n");
+ print_spew("In romstage.c:main()\n");
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
- print_debug("Enable F-ROM Shadow RAM\r\n");
+ print_debug("Enable F-ROM Shadow RAM\n");
enable_shadow_ram();
/* setup cpu */
- print_debug("Setup CPU Interface\r\n");
+ print_debug("Setup CPU Interface\n");
c3_cpu_setup(ctrl.d0f2);
ddr_ram_setup();
if (bist == 0) {
- print_debug("doing early_mtrr\r\n");
+ print_debug("doing early_mtrr\n");
early_mtrr_init();
}
//ram_check(0, 640 * 1024);
- print_spew("Leaving romstage.c:main()\r\n");
+ print_spew("Leaving romstage.c:main()\n");
}
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for (i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
int i;
udelay(2000);
print_debug_hex16(port);
- print_debug(":\r\n");
+ print_debug(":\n");
for (i = 0; i < 256; i++) {
u8 val;
if ((i & 0x0f) == 0) {
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
port++;
}
#ifdef DEACTIVATE_CAR
print_debug("Deactivating CAR");
#include DEACTIVATE_CAR_FILE
- print_debug(" - Done.\r\n");
+ print_debug(" - Done.\n");
#endif
copy_and_run(0);
}
for(i=0; i<sysinfo->nodes; i++) {
#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
+ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
#else
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
#endif
}
if(needs_reset) {
#ifdef __PRE_RAM__
- print_debug("mem trained failed\r\n");
+ print_debug("mem trained failed\n");
soft_reset();
#else
printk(BIOS_DEBUG, "mem trained failed\n");
static inline void print_linkn (const char *strval, uint8_t byteval)
{
- printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
+ printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
}
static void disable_probes(void)
HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
val &= ~((1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
- print_spew(" done.\r\n");
+ print_spew(" done.\n");
}
static void fill_row(u8 node, u8 row, u32 value)
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
- print_spew(" done.\r\n");
+ print_spew(" done.\n");
}
static int verify_connection(u8 dest)
pci_write_config32(NODE_MP(7), reg, value);
}
- print_spew("done\r\n");
+ print_spew("done\n");
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
static void setup_uniprocessor(void)
{
- print_spew("Enabling UP settings\r\n");
+ print_spew("Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS==1
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
{
unsigned nodes;
- print_spew("Enabling SMP settings\r\n");
+ print_spew("Enabling SMP settings\n");
nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2
nodes = setup_smp8();
#endif
- printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes);
+ printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes);
return nodes;
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
case 0x02: /* MPCap */
if(nodes > 2) {
- print_err("Going back to DP\r\n");
+ print_err("Going back to DP\n");
return 2;
}
break;
#endif
case 0x00: /* Non SMP */
if(nodes >1 ) {
- print_err("Going back to UP\r\n");
+ print_err("Going back to UP\n");
return 1;
}
break;
* registers on Hammer A0 revision.
*/
- print_spew("coherent_ht_finalize\r\n");
+ print_spew("coherent_ht_finalize\n");
#if CONFIG_K8_REV_F_SUPPORT == 0
rev_a0 = is_cpu_rev_a0();
#endif
#endif
}
- print_spew("done\r\n");
+ print_spew("done\n");
}
static int apply_cpu_errata_fixes(unsigned nodes)
static inline void print_linkn_in (const char *strval, uint8_t byteval)
{
- printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
+ printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
}
static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
uint32_t id;
freq_cap = pci_read_config16(dev, pos);
- printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
+ printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
id = pci_read_config32(dev, 0);
#endif
}
- printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
- //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n");
+ printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
+ //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\n");
//freq_cap &= 0x3f;
return freq_cap;
}
int needs_reset;
/* Set link width and frequency */
- printk(BIOS_SPEW, "entering ht_optimize_link\r\n");
+ printk(BIOS_SPEW, "entering ht_optimize_link\n");
/* Initially assume everything is already optimized and I don't need a reset */
needs_reset = 0;
/* Get the frequency capabilities */
freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
- printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
+ printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2);
/* Calculate the highest possible frequency */
freq = log2(freq_cap1 & freq_cap2);
old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
old_freq &= 0x0f;
needs_reset |= old_freq != freq;
- printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+ printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
old_freq &= 0x0f;
needs_reset |= old_freq != freq;
- printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+ printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
/* Set the Calculated link frequency */
pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
/* Get the width capabilities */
width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
- printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
+ printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2);
/* Calculate dev1's input width */
ln_width1 = link_width_to_pow2[width_cap1 & 7];
ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
- printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+ printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width = pow2_to_link_width[ln_width1];
- printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev1 input width=0x%x\n", width);
/* Calculate dev1's output width */
ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
ln_width2 = link_width_to_pow2[width_cap2 & 7];
- printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+ printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width |= pow2_to_link_width[ln_width1] << 4;
- printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width);
/* See if I am changing dev1's width */
old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
old_width &= 0x77;
needs_reset |= old_width != width;
- printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width);
/* Set dev1's widths */
pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
/* Calculate dev2's width */
width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
- printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width);
/* See if I am changing dev2's width */
old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
old_width &= 0x77;
needs_reset |= old_width != width;
- printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width);
/* Set dev2's widths */
pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
print_err("udev="); print_err_hex32(udev);
print_err("\tupos="); print_err_hex32(upos);
print_err("\tuoffs="); print_err_hex32(uoffs);
- print_err("\tHT link capability not found\r\n");
+ print_err("\tHT link capability not found\n");
break;
}
unsigned link_pair_num = sysinfo->link_pair_num;
- printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n");
- printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
+ printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n");
+ printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num);
for(i=0; i< link_pair_num; i++) {
struct link_pair_st *link_pair= &sysinfo->link_pair[i];
reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
- printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
+ printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
}
reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
- printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
+ printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed);
return reset_needed;
e0_later_single_core = 0;
}
if(e0_later_single_core) {
- printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
+ printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
j=1;
}
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- printk(BIOS_DEBUG, "%s%x\r\n", str, val);
+ printk(BIOS_DEBUG, "%s%x\n", str, val);
}
#endif
}
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2);
+ printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2);
}
#endif
}
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+ printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2);
}
#endif
}
static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
{
- printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+ printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2);
}
}
}
- print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
+ print_debug_dqs("\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
print_debug_addr("TrainRcvEn: buf_a:", buf_a);
}
- print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a);
static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
{
- print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
if(TrainRcvrEn(ctrl, Pass, sysinfo)) {
return 1;
}
- print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
return 0;
}
static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
{
- print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
- printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
+ printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id);
return 1;
}
else {
SetEccDQSRdWrPos(ctrl, sysinfo);
}
- print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
return 0;
}
}
sizek = 1 << align;
#if CONFIG_MEM_TRAIN_SEQ != 1
- printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\r\n",
+ printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"UC":
((type==MTRR_TYPE_WRBACK)?"WB":"Other")
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
}
tsc[1] = rdtsc();
printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
if(train_DqsPos(ctrl+i, sysinfo)) goto out;
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
}
tsc[3] = rdtsc();
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
sysinfo->mem_trained[i]=1;
dqs_save_MC_NVRAM((ctrl+i)->f2);
}
}
if(v) {
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
tsc[1] = rdtsc();
printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i);
}
}
if(v) {
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
tsc[2] = rdtsc();
printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
}
if(v) {
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
tsc[3] = rdtsc();
}
#if 0
print_debug("spd_count: ");
print_debug_hex32(spd_count);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
reset_tests();
spd_fail_count = i;
- print_debug("\r\nSPD will fail after: ");
+ print_debug("\nSPD will fail after: ");
print_debug_hex32(spd_fail_count);
- print_debug(" accesses.\r\n");
+ print_debug(" accesses.\n");
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
int i;
// print_debug("setting up resource map offset....");
#if 0
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
#if 0
- prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]);
+ prink_debug("%08x <- %08x\n", register_values[i] + offset_pci_dev, register_values[i+2]);
#endif
dev = (register_values[i] & ~0xfff) + offset_pci_dev;
where = register_values[i] & 0xfff;
pci_write_config32(register_values[i], reg);
#endif
}
-// print_debug("done.\r\n");
+// print_debug("done.\n");
}
#define RES_PCI_IO 0x10
#endif
#if RES_DEBUG
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
- printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
+ printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i>>2, register_values[i],
register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
register_values[i+2],
}
#if RES_DEBUG
- print_debug("done.\r\n");
+ print_debug("done.\n");
#endif
}
static void setup_resource_map_x(const unsigned int *register_values, int max)
#endif
#if RES_DEBUG
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
- printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
+ printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#endif
switch (register_values[i]) {
}
#if RES_DEBUG
- print_debug("done.\r\n");
+ print_debug("done.\n");
#endif
}
print_debug(" -> ");
reg = inb(where);
print_debug_hex8(reg);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
}
print_debug(" -> ");
reg = inl(where);
print_debug_hex32(reg);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
}
print_debug(" RB ");
reg = read32(where);
print_debug_hex32(reg);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
}
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
/* retrieve the page size from the MC register */
#if 0
print_debug(" page_size = ");
print_debug_hex32(page_size);
- print_debug("\r\n");
+ print_debug("\n");
#endif
comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12);
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift));
}
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
#if 0
print_debug(" page_size = ");
print_debug_hex32(page_size);
- print_debug("\r\n");
+ print_debug("\n");
#endif
setGX1Mem(0, TEST_DATA1);
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift));
}
#if 0
print_debug(" Page size Config = ");
print_debug_hex32(page_size_config << dimm_shift);
- print_debug("\r\n");
+ print_debug("\n");
#endif
return(page_size_config << dimm_shift);
}
print_debug("Probing for DIMM");
print_debug_char((dimm_shift >> 4) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
setGX1Mem(0, TEST_DATA1);
setGX1Mem(0x100, 0);
print_debug(" Found DIMM");
print_debug_char((dimm_shift >> 4) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
return 1;
}
print_debug(" Page Size: ");
print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4)));
- print_debug("\r\n");
+ print_debug("\n");
/* Now do component banks detection */
print_debug(" Component Banks: ");
print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
/* Now do module banks */
print_debug(" Module Banks: ");
print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
mem_config &= (~(DIMM_SZ << dimm_shift));
mem_config |= (size_dimm(dimm_shift));
print_debug(" DIMM size: ");
print_debug_hex32(1 <<
((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
- print_debug("\r\n");
+ print_debug("\n");
return (mem_config);
}
{
unsigned int mem_config = 0x00700070;
- print_debug("Setting up default parameters for memory\r\n");
+ print_debug("Setting up default parameters for memory\n");
outb(0x70, 0x80);
setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
enable_dimm();
- print_debug("Sizing memory\r\n");
+ print_debug("Sizing memory\n");
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740);
do_refresh();
print_debug("MC_BANK_CFG = ");
print_debug_hex32(mem_config);
- print_debug("\r\n");
+ print_debug("\n");
setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config);
enable_dimm();
msr.lo |= PLLMSRlo1;
wrmsr(GLCP_SYS_RSTPLL, msr);
- print_debug("Reset PLL\n\r");
+ print_debug("Reset PLL\n");
msr.lo |= PLLMSRlo2;
wrmsr(GLCP_SYS_RSTPLL,msr);
- print_debug("should not be here\n\r");
+ print_debug("should not be here\n");
#endif
print_err("shit");
while (1)
if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
/* PLL is already set and we are reboot from PLL reset */
- print_debug("reboot from BIOS reset\n\r");
+ print_debug("reboot from BIOS reset\n");
return;
}
msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
wrmsr(0x4c000014, msr);
- print_debug("Reset PLL\n\r");
+ print_debug("Reset PLL\n");
msr.lo |= ((1<<14) |(1<<13) | (1<<0));
wrmsr(0x4c000014,msr);
- print_debug("should not be here\n\r");
+ print_debug("should not be here\n");
}
#endif // #if USE_GOODRICH_VERSION
msr = rdmsr(0x2000001a);
msr.lo = 0x0101;
wrmsr(0x2000001a, msr);
- //print_debug("sdram_enable step 2\r\n");
+ //print_debug("sdram_enable step 2\n");
/* 3. release CKE mask to enable CKE */
msr = rdmsr(0x2000001d);
msr.lo &= ~(0x03 << 8);
wrmsr(0x2000201d, msr);
- //print_debug("sdram_enable step 3\r\n");
+ //print_debug("sdram_enable step 3\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
msr.lo &= ~(0x01 << 3);
wrmsr(0x20000018, msr);
}
- //print_debug("sdram_enable step 4\r\n");
+ //print_debug("sdram_enable step 4\n");
/* 5. set refresh interval */
msr = rdmsr(0x20000018);
msr.lo &= ~(0x03 << 6);
msr.lo |= (0x00 << 6);
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 5\r\n");
+ //print_debug("sdram_enable step 5\n");
/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018);
wrmsr(0x20000018, msr);
msr.lo &= ~((0x01 << 28) | 0x01);
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 6\r\n");
+ //print_debug("sdram_enable step 6\n");
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
wrmsr(0x20000018, msr);
msr.lo &= ~((0x01 << 27) | 0x01);
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 7\r\n");
+ //print_debug("sdram_enable step 7\n");
/* 8. load Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018);
wrmsr(0x20000018, msr);
msr.lo &= ~0x01;
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 8\r\n");
+ //print_debug("sdram_enable step 8\n");
/* wait 200 SDCLKs */
for (i = 0; i < 200; i++)
/* make sure there is nothing stale in the cache */
__asm__("wbinvd\n");
- print_debug("RAM DLL lock\r\n");
+ print_debug("RAM DLL lock\n");
/* The RAM dll needs a write to lock on so generate a few dummy writes */
volatile unsigned long *ptr;
for (i=0;i<5;i++) {
__asm__ __volatile__("hlt\n");
}
- print_debug("Done pll_reset\r\n");
+ print_debug("Done pll_reset\n");
return;
}
/* This is so ugly. */
print_debug("===========================");
print_debug(s);
- print_debug("======================================\r\n");
+ print_debug("======================================\n");
}
void hcf(void)
{
- print_emerg("DIE\r\n");
+ print_emerg("DIE\n");
/* this guarantees we flush the UART fifos (if any) and also
* ensures that things, in general, keep going so no debug output
* is lost
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
- print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n");
+ print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
POST_CODE(POST_PLL_MEM_FAIL);
hcf();
}
} else if ((casmap0 &= casmap1)) {
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
} else {
- print_emerg("DIMM CAS Latencies not compatible\r\n");
+ print_emerg("DIMM CAS Latencies not compatible\n");
POST_CODE(ERROR_DIFF_DIMMS);
hcf();
}
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
- print_info("Enabled MTest for TLA debug\r\n");
+ print_info("Enabled MTest for TLA debug\n");
}
static void sdram_set_registers(const struct mem_controller *ctrl)
banner("Check DIMM 0");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM0 NOT COMPATIBLE\r\n");
+ print_emerg("DIMM0 NOT COMPATIBLE\n");
POST_CODE(ERROR_UNSUPPORTED_DIMM);
hcf();
}
msr = rdmsr(MC_CF07_DATA);
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
- print_emerg("No memory in the system\r\n");
+ print_emerg("No memory in the system\n");
POST_CODE(ERROR_NO_DIMMS);
hcf();
}
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x:",i);
+ printk(BIOS_DEBUG, "\n%02x:",i);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug_char(':');
#endif
print_debug_hex8(val);
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
static void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\r\n");
+ print_debug("\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ",j);
+ printk(BIOS_DEBUG, "\n%02x: ",j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
int i;
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "%04x:\r\n", port);
+ printk(BIOS_DEBUG, "%04x:\n", port);
#else
print_debug_hex16(port);
- print_debug(":\r\n");
+ print_debug(":\n");
#endif
for(i=0;i<256;i++) {
uint8_t val;
print_debug_hex8(val);
#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
port++;
}
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%08x:", i);
+ printk(BIOS_DEBUG, "\n%08x:", i);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex32(i);
print_debug(":");
#endif
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
#endif
#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
-#define SPD_ERROR "Error reading SPD info\r\n"
+#define SPD_ERROR "Error reading SPD info\n"
// NOTE: This used to be 0x100000.
// That doesn't work on systems where A20M# is asserted, because
static void die_on_spd_error(int spd_return_value)
{
if (spd_return_value < 0)
- die("Error reading SPD info\r\n");
+ die("Error reading SPD info\n");
}
//----------------------------------------------------------------------------------
value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
if (value < 0) goto hw_err;
if (value > 2)
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
if (value == 2) {
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
}
else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
- RAM_DEBUG_MESSAGE("\r\n");
+ RAM_DEBUG_MESSAGE("\n");
read32(dimm_start_address + e7501_mode_bits);
// Set the start of the next DIMM
RAM_DEBUG_HEX32(sz.side1);
RAM_DEBUG_MESSAGE(" ");
RAM_DEBUG_HEX32(sz.side2);
- RAM_DEBUG_MESSAGE("\r\n");
+ RAM_DEBUG_MESSAGE("\n");
if (sz.side1 == 0)
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
}
uint8_t byte;
- RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
+ RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
/* Initialize ECC bits , use ECC zero mode (new to 7501)*/
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
} while ( (byte & 0x08 ) == 0);
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
- RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");
+ RAM_DEBUG_MESSAGE("ECC state initialized.\n");
/* Clear the ECC error bits */
pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
}
}
else
- die("No CAS# latencies compatible with all DIMMs!!\r\n");
+ die("No CAS# latencies compatible with all DIMMs!!\n");
pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if(value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\r\n");
+ print_err("unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\r\n");
+ print_err("unsupported refresh rate\n");
continue;
}
uint32_t dword;
uint8_t maybe_strength_control;
- RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n");
+ RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
/*enable access to the rcomp bar*/
dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
return;
/* 1 & 2 Power up and start clocks */
- RAM_DEBUG_MESSAGE("Ram Enable 1\r\n");
- RAM_DEBUG_MESSAGE("Ram Enable 2\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 1\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 2\n");
/* A 200us delay is needed */
EXTRA_DELAY
/* 3. Apply NOP */
- RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 3\n");
do_ram_command(RAM_COMMAND_NOP, 0);
EXTRA_DELAY
/* 4 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 4\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
/* wait until the all banks idle state... */
/* 5. Issue EMRS to enable DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 5\n");
do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
EXTRA_DELAY
/* 6. Reset DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 6\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
EXTRA_DELAY
EXTRA_DELAY
/* 7 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 7\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
- RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 8\n");
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
/* 9 mode register set */
- RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 9\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
EXTRA_DELAY
/* 10 DDR Receive FIFO RE-Sync */
- RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 10\n");
RAM_RESET_DDR_PTR();
EXTRA_DELAY
/* 11 normal operation */
- RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 11\n");
do_ram_command(RAM_COMMAND_NORMAL, 0);
EXTRA_DELAY
dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit
pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
- RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
+ RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
DUMPNORTH();
// verify_ram();
{
uint8_t dimm_mask;
- RAM_DEBUG_MESSAGE("Reading SPD data...\r\n");
+ RAM_DEBUG_MESSAGE("Reading SPD data...\n");
//activate_spd_rom(ctrl); Not necessary for this chipset
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\r\n");
+ print_debug("No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
- RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
+ RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
configure_e7501_row_attributes(ctrl, dimm_mask);
configure_e7501_dram_controller_mode(ctrl, dimm_mask);
configure_e7501_dram_timing(ctrl, dimm_mask);
DO_DELAY
- RAM_DEBUG_MESSAGE("done\r\n");
+ RAM_DEBUG_MESSAGE("done\n");
}
// NOTE: configure_e7501_ram_addresses() is NOT called here.
//
static void sdram_set_registers(const struct mem_controller *ctrl)
{
- RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n");
+ RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
ram_set_rcomp_regs();
drc = pci_read_config32(NB_DEV, DRC);
//print_debug("memory_initialized: DRC: ");
//print_debug_hex32(drc);
- //print_debug("\r\n");
+ //print_debug("\n");
return (drc & (1<<29));
}
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
ecc = 2;
}
else if (ecc == 1) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else if ( reg == 7 ) {
ecc = 1;
}
else if ( ecc > 1 ) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else {
- die("ERROR - RAM not DDR\r\n");
+ die("ERROR - RAM not DDR\n");
}
}
else {
- die("ERROR - Non ECC memory dimm\r\n");
+ die("ERROR - Non ECC memory dimm\n");
}
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
ecc = 2;
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
- print_debug("ECC off\r\n");
+ print_debug("ECC off\n");
}
else {
- print_debug("ECC on\r\n");
+ print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
drc |= (ecc << 20); /* or in the calculated ecc bits */
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32);
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(BAR+DCALDATA+(16*4), 0x00000000);
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
pll_setup(drc);
data32 = drc & ~(3 << 20); /* clear ECC mode */
for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(BAR+DCALDATA+i, 0x00000000);
}
data32 |= (1 << 31);
pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
ecc = 2;
}
else if (ecc == 1) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else if ( reg == 7 ) {
ecc = 1;
}
else if ( ecc > 1 ) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else {
- die("ERROR - RAM not DDR\r\n");
+ die("ERROR - RAM not DDR\n");
}
}
else {
- die("ERROR - Non ECC memory dimm\r\n");
+ die("ERROR - Non ECC memory dimm\n");
}
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
ecc = 2;
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
- print_debug("ECC off\r\n");
+ print_debug("ECC off\n");
}
else {
- print_debug("ECC on\r\n");
+ print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
drc |= (ecc << 20); /* or in the calculated ecc bits */
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, 0xb0, data32);
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(BAR+DCALDATA+(16*4), 0x00000000);
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 & ~(7 << 8); /* clear refresh rates */
for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(BAR+DCALDATA+i, 0x00000000);
}
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
struct dimm_size {
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
continue;
}
value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
- if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
+ if (value != 2) die("ERROR - Non ECC memory dimm\n");
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
value &= 0x0f; /* clip self refresh bit */
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(MCBAR+DCALDATA+(16*4), 0x00000000);
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 & ~(7 << 8); /* clear refresh rates */
for(i=0;i<8;i+=2) { /* loop through each dimm to test */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
write32(MCBAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
print_debug_hex8(sz.side1);
print_debug(".");
print_debug_hex8(sz.side2);
- print_debug("\r\n");
+ print_debug("\n");
return sz;
}
}
print_debug("DRB = ");
print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
- print_debug("\r\n");
+ print_debug("\n");
cum >>= 1;
/* set TOM top of memory */
pci_write_config16(ctrl->f0, TOM, cum);
print_debug("TOM = ");
print_debug_hex16(cum);
- print_debug("\r\n");
+ print_debug("\n");
/* set TOLM top of low memory */
if (cum > 0x18) {
cum = 0x18;
pci_write_config16(ctrl->f0, TOLM, cum);
print_debug("TOLM = ");
print_debug_hex16(cum);
- print_debug("\r\n");
+ print_debug("\n");
return 0;
}
print_debug_hex8(device);
print_debug(" = ");
print_debug_hex8(byte);
- print_debug("\r\n");
+ print_debug("\n");
if (byte == 8) {
dimm_mask |= (1 << i);
}
}
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xf) == 0) die("Invalid # of rows\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xf) == 0) die("Invalid # of rows\n");
dra |= (((value-13) & 0x7) << 23);
dra |= (((value-13) & 0x7) << 29);
reg += value & 0xf;
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xf) == 0) die("Invalid # of columns\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xf) == 0) die("Invalid # of columns\n");
dra |= (((value-10) & 0x7) << 20);
dra |= (((value-10) & 0x7) << 26);
reg += value & 0xf;
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xff) == 0) die("Invalid # of banks\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xff) == 0) die("Invalid # of banks\n");
reg += log2(value & 0xff);
print_debug("dimm ");
print_debug_hex8(i);
print_debug(" reg = ");
print_debug_hex8(reg);
- print_debug("\r\n");
+ print_debug("\n");
/* set device density */
dra |= ((31-reg));
print_debug_hex8(i);
print_debug(" = ");
print_debug_hex32(dra);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRA + (i*4), dra);
}
else if (val & 0x40)
cl = 6;
else
- die("CAS latency mismatch\r\n");
+ die("CAS latency mismatch\n");
print_debug("cl = ");
print_debug_hex8(cl);
- print_debug("\r\n");
+ print_debug("\n");
ci = cycle[index];
}
print_debug("trc = ");
print_debug_hex8(trc);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("trfc = ");
print_debug_hex8(trfc);
- print_debug("\r\n");
+ print_debug("\n");
/* Tras, Trtp, Twtr in cycles */
for (i = 0; i < DIMM_SOCKETS; i++) {
}
print_debug("tras = ");
print_debug_hex8(tras);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("trtp = ");
print_debug_hex8(trtp);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("twtr = ");
print_debug_hex8(twtr);
- print_debug("\r\n");
+ print_debug("\n");
val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
| ((cl - 3) << 6) | ((cl - 3) << 3));
print_debug("drt0 = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRT0, val);
val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
| (twtr << 15));
print_debug("drt1 = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRT1, val);
val = (magic[index]);
print_debug("magic = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
val = (mrs[index] | (cl << 20));
print_debug("mrs = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
return val;
}
if (!(dimm_mask & (1 << i)))
continue;
if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)
- die("ERROR: Only 64-bit DIMMs supported\r\n");
+ die("ERROR: Only 64-bit DIMMs supported\n");
if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))
- die("ERROR: Only ECC DIMMs supported\r\n");
+ die("ERROR: Only ECC DIMMs supported\n");
if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)
- die("ERROR: Only x8 DIMMs supported\r\n");
+ die("ERROR: Only x8 DIMMs supported\n");
value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if (value > cycle)
}
print_debug("cycle = ");
print_debug_hex8(cycle);
- print_debug("\r\n");
+ print_debug("\n");
drc |= (1 << 20); /* enable ECC */
drc |= (3 << 30); /* enable CKE on each DIMM */
print_debug("msr 0xcd = ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
/* TODO check that this msr really indicates fsb speed! */
if (msr.lo & 0x07) {
- print_info("533 MHz FSB\r\n");
+ print_info("533 MHz FSB\n");
if (cycle <= 0x25) {
drc |= 0x5;
- print_info("400 MHz DDR\r\n");
+ print_info("400 MHz DDR\n");
} else if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\r\n");
+ print_info("333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x4;
- print_info("266 MHz DDR\r\n");
+ print_info("266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\r\n");
+ print_info("200 MHz DDR\n");
}
}
else {
- print_info("400 MHz FSB\r\n");
+ print_info("400 MHz FSB\n");
if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\r\n");
+ print_info("333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x0;
- print_info("266 MHz DDR\r\n");
+ print_info("266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\r\n");
+ print_info("200 MHz DDR\n");
}
}
print_debug("DRC = ");
print_debug_hex32(drc);
- print_debug("\r\n");
+ print_debug("\n");
return drc;
}
/* Test if we can read the SPD */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
for (i = 0; i < 2; i++) {
print_debug("ODT CS");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
int i;
for (i = 0x0; i < 0x2a0; i += 4) {
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug(": ");
}
print_debug_hex32(read32(BAR+i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
u16 data16;
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* Set DRAM type and Front Side Bus frequency */
drc = spd_set_dram_controller_mode(ctrl, mask);
if (drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 | (3 << 5); /* temp turn off ODT */
for (cs = 0; cs < 2; cs++) {
print_debug("NOP CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
udelay(16);
write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
for (cs = 0; cs < 2; cs++) {
print_debug("NOP CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
for (cs = 0; cs < 2; cs++) {
print_debug("Precharge CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
for (cs = 0; cs < 2; cs++) {
print_debug("EMRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
for (cs = 0; cs < 2; cs++) {
print_debug("MRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, mode_reg);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
for (cs = 0; cs < 2; cs++) {
print_debug("Precharge CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
for (cs = 0; cs < 2; cs++) {
print_debug("Refresh CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
for (cs = 0; cs < 2; cs++) {
print_debug("MRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
for (cs = 0; cs < 2; cs++) {
print_debug("EMRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
for (cs = 0; cs < 1; cs++) {
print_debug("receive enable calibration CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
continue;
print_debug("clear memory CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
data32 = read32(BAR+MBCSR);
while (data32 & 0x80000000)
data32 = read32(BAR+MBCSR);
if (data32 & 0x40000000)
- print_debug("failed!\r\n");
+ print_debug("failed!\n");
}
/* Clear read/write FIFO pointers */
- print_debug("clear read/write fifo pointers\r\n");
+ print_debug("clear read/write fifo pointers\n");
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
udelay(16);
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
dump_dcal_regs();
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
drc |= (1 << 29);
static void dump_spd_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = spd_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
PRINT_DEBUG_HEX16(reg16);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
PRINT_DEBUG_HEX8(reg);
PRINT_DEBUG(") for DIMM ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
pci_write_config8(NB, DRAMC, reg);
int i, max;
uint8_t reg;
- PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
max = ARRAY_SIZE(register_values);
PRINT_DEBUG_HEX8(register_values[i]);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX8(reg);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
}
}
PRINT_DEBUG("DIMM in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
if (edosd == 0x06) {
- print_err("Mixing EDO/SDRAM unsupported!\r\n");
- die("HALT\r\n");
+ print_err("Mixing EDO/SDRAM unsupported!\n");
+ die("HALT\n");
}
/* "DRA" is our RPS for the two rows on this DIMM. */
if (col == 4)
bpr |= 0xc0;
} else {
- print_err("# of banks of DIMM unsupported!\r\n");
- die("HALT\r\n");
+ print_err("# of banks of DIMM unsupported!\n");
+ die("HALT\n");
}
if (dra == -1) {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
/*
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- print_err("DIMMs smaller than 8MB per side\r\n"
- "are not supported on this NB.\r\n");
- die("HALT\r\n");
+ print_err("DIMMs smaller than 8MB per side\n"
+ "are not supported on this NB.\n");
+ die("HALT\n");
}
if ((sz.side1 > 128)) {
- print_err("DIMMs > 128MB per side\r\n"
- "are not supported on this NB\r\n");
- die("HALT\r\n");
+ print_err("DIMMs > 128MB per side\n"
+ "are not supported on this NB\n");
+ die("HALT\n");
}
/* Divide size by 8 to set up the DRB registers. */
#if 0
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
/* If there's no DIMM in the slot, set dra to 0x00. */
#if 0
PRINT_DEBUG("DRB has been set to 0x");
PRINT_DEBUG_HEX16(drb);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
/* Brings the upper DRB back down to be base for
pci_write_config8(NB, PGPOL + 1, bpr);
PRINT_DEBUG("PGPOL[BPR] has been set to 0x");
PRINT_DEBUG_HEX8(bpr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* Set DRAM row page size register. */
pci_write_config16(NB, RPS, rps);
PRINT_DEBUG("RPS has been set to 0x");
PRINT_DEBUG_HEX16(rps);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* ### ECC */
pci_write_config8(NB, NBXCFG + 3, nbxecc);
PRINT_DEBUG("NBXECC[31:24] has been set to 0x");
PRINT_DEBUG_HEX8(nbxecc);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
* TODO: Registered SDRAM support.
pci_write_config8(NB, DRAMC, value);
PRINT_DEBUG("DRAMC has been set to 0x");
PRINT_DEBUG_HEX8(value);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
static void sdram_set_spd_registers(void)
udelay(200);
/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation. */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
/* 6. Finally enable refresh. */
- PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
+ PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
// pci_write_config8(NB, PMCR, 0x10);
spd_enable_refresh();
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
PRINT_DEBUG_HEX16(reg16);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
PRINT_DEBUG("spd_enable_refresh: dramc = 0x");
PRINT_DEBUG_HEX8(reg);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
/*-----------------------------------------------------------------------------
reg32 = pci_read_config32(NB, APBASE);
PRINT_DEBUG("APBASE ");
PRINT_DEBUG_HEX32(reg32);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
#if 0
uint16_t reg16;
reg16 = pci_read_config16(NB, PACCFG);
- printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
+ printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6');
#endif
- PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
northbridge_init();
} else {
PRINT_DEBUG(" FAIL ");
}
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
- PRINT_DEBUG("Northbridge atexit sdram set registers\r\n");
+ PRINT_DEBUG("Northbridge atexit sdram set registers\n");
DUMPNORTH();
}
*/
PRINT_DEBUG_HEX16(ds);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
memsize += ds;
PRINT_DEBUG(" ");
PRINT_DEBUG_HEX16(ds);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/*
* modify DRT register if current row isn't empty
#if 0
PRINT_DEBUG("Mem: 0x");
PRINT_DEBUG_HEX16(memsize * 8);
- PRINT_DEBUG(" MB\r\n");
+ PRINT_DEBUG(" MB\n");
if (memsize == 0) {
/* maybe we should use some nice die/hlt sequence with printing on console
* maybe such event_handler can be commonly defined routine to decrease
* code duplication?
*/
- PRINT_DEBUG("No memory detected via SPD\r\n");
- PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\r\n");
+ PRINT_DEBUG("No memory detected via SPD\n");
+ PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\n");
}
#endif
udelay(200);
/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation. */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
/* 6. Finally enable refresh. */
- PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
+ PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
pci_write_config8(NB, DRAMC, 0x01);
spd_enable_refresh();
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
}
static void dump_spd_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
}
if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex8(dimm_size * 4);
- print_debug("MB\r\n");
+ print_debug("MB\n");
/* The i810 can't handle DIMMs larger than 128MB per
* side. This will fail if the DIMM uses a
*/
if (dimm_size > 32) {
print_err("DIMM row sizes larger than 128MB not"
- "supported on i810\r\n");
+ "supported on i810\n");
print_err
- ("Attempting to treat as 128MB DIMM\r\n");
+ ("Attempting to treat as 128MB DIMM\n");
dimm_size = 32;
}
print_debug("After translation, dimm_size is 0x");
print_debug_hex8(dimm_size);
- print_debug("\r\n");
+ print_debug("\n");
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations. */
if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
0xff) {
- print_debug("DIMM is dual-sided\r\n");
+ print_debug("DIMM is dual-sided\n");
dimm_size += 2;
}
} else {
print_debug("No DIMM found in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* If there's no DIMM in the slot, set value to 0. */
dimm_size = 0x00;
print_debug("DRP calculated to 0x");
print_debug_hex8(drp);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
}
print_debug("BUFF_SC calculated to 0x");
print_debug_hex16(buff_sc);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
}
int i;
/* 1. Apply NOP. */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation (enables refresh at 15.6usec). */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
pci_write_config32(NORTHBRIDGE, DRC, reg32);
PRINT_DEBUG("RAM command 0x");
PRINT_DEBUG_HEX32(reg32);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
static void ram_read32(u8 dimm_start, u32 offset)
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" => 0x");
PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG(" Writing RAM at 0x");
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" <= 0x");
PRINT_DEBUG_HEX32(offset);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
write32(dimm_start * 32 * 1024 * 1024, offset);
PRINT_DEBUG(" Reading RAM at 0x");
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" => 0x");
PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
} else {
PRINT_DEBUG(" Sending RAM command to 0x");
PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
read32((dimm_start * 32 * 1024 * 1024) + offset);
}
}
if (dimm_end > dimm_start) {
print_debug("Initializing SDRAM Row ");
print_debug_hex8(row);
- print_debug("\r\n");
+ print_debug("\n");
/* NOP command */
PRINT_DEBUG(" NOP ");
udelay(1);
/* Perform a dummy memory read/write cycle */
- PRINT_DEBUG(" Performing dummy read/write\r\n");
+ PRINT_DEBUG(" Performing dummy read/write\n");
ram_read32(dimm_start, 0x55aa55aa);
udelay(1);
}
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
sz = spd_get_dimm_size(device);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex16(sz.side1);
- print_debug(" on side 1\r\n");
+ print_debug(" on side 1\n");
print_debug("DIMM is 0x");
print_debug_hex16(sz.side2);
- print_debug(" on side 2\r\n");
+ print_debug(" on side 2\n");
/* - Memory compatibility checks - */
/* Test for PC133 (i82830 only supports PC133) */
/* PC133 SPD9 - cycle time is always 75 */
if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
- print_err("SPD9 DIMM Is Not PC133 Compatable\r\n");
- die("HALT\r\n");
+ print_err("SPD9 DIMM Is Not PC133 Compatable\n");
+ die("HALT\n");
}
/* PC133 SPD10 - access time is always 54 */
if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
- print_err("SPD10 DIMM Is Not PC133 Compatable\r\n");
- die("HALT\r\n");
+ print_err("SPD10 DIMM Is Not PC133 Compatable\n");
+ die("HALT\n");
}
/* The i82830 only supports a symmetrical dual-sided dimms
* side or larger than 256MB per side.
*/
if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
- print_err("This northbridge only supports\r\n");
- print_err("symmetrical dual-sided DIMMs\r\n");
- print_err("booting as a single-sided DIMM\r\n");
+ print_err("This northbridge only supports\n");
+ print_err("symmetrical dual-sided DIMMs\n");
+ print_err("booting as a single-sided DIMM\n");
sz.side2 = 0;
}
if ((sz.side1 < 32)) {
- print_err("DIMMs smaller than 32MB per side\r\n");
- print_err("are not supported on this northbridge\r\n");
- die("HALT\r\n");
+ print_err("DIMMs smaller than 32MB per side\n");
+ print_err("are not supported on this northbridge\n");
+ die("HALT\n");
}
if ((sz.side1 > 256)) {
print_err
- ("DIMMs larger than 256MB per side\r\n");
+ ("DIMMs larger than 256MB per side\n");
print_err
- ("are not supported on this northbridge\r\n");
- die("HALT\r\n");
+ ("are not supported on this northbridge\n");
+ die("HALT\n");
}
/* - End Memory compatibility checks - */
} else {
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* If there's no DIMM in the slot, set value to 0. */
drb1 = 0;
PRINT_DEBUG_HEX8(DRB);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(drb1);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG("DRB1 0x");
PRINT_DEBUG_HEX8(DRB + 1);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(drb1 + drb2);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
} else if (i == 1) {
value = pci_read_config8(NORTHBRIDGE, DRB + 1);
pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
PRINT_DEBUG_HEX8(DRB + 2);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(value + drb1);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG("DRB3 0x");
PRINT_DEBUG_HEX8(DRB + 3);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(value + drb1 + drb2);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* We need to set the highest DRB value to 0x64 and 0x65.
* These are supposed to be "Reserved" but memory will
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug(", setting DRA...\r\n");
+ print_debug(", setting DRA...\n");
dra = 0x00;
} else if (dra == 16) {
dra = 0xF3; /* 16KB */
} else {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
} else if (value == 2) {
if (dra == 2) {
} else if (dra == 16) {
dra = 0x33; /* 16KB */
} else {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
} else {
- print_err("# of banks of DIMM not supported\r\n");
- die("HALT\r\n");
+ print_err("# of banks of DIMM not supported\n");
+ die("HALT\n");
}
} else {
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG(", setting DRA to 0xFF\r\n");
+ PRINT_DEBUG(", setting DRA to 0xFF\n");
/* If there's no DIMM in the slot, set dra value to 0xFF. */
dra = 0xFF;
PRINT_DEBUG_HEX8(DRA + i);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(dra);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
}
static void sdram_set_registers(void)
{
- PRINT_DEBUG("Setting initial sdram registers....\r\n");
+ PRINT_DEBUG("Setting initial sdram registers....\n");
/* Calculate the value for DRT DRAM Timing Register */
set_dram_timing();
/* Setup DRAM Row Attribute Registers */
set_dram_row_attributes();
- PRINT_DEBUG("Initial sdram registers have been set.\r\n");
+ PRINT_DEBUG("Initial sdram registers have been set.\n");
}
static void northbridge_set_registers(void)
u16 value;
int igd_memory = 0;
- PRINT_DEBUG("Setting initial nothbridge registers....\r\n");
+ PRINT_DEBUG("Setting initial nothbridge registers....\n");
/* Set the value for Fixed DRAM Hole Control Register */
pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
value |= 1; // 64MB aperture
pci_write_config16(NORTHBRIDGE, GCC1, value);
- PRINT_DEBUG("Initial northbridge registers have been set.\r\n");
+ PRINT_DEBUG("Initial northbridge registers have been set.\n");
}
static void sdram_initialize(void)
initialize_dimm_rows();
/* Enable Refresh */
- PRINT_DEBUG("Enabling Refresh\r\n");
+ PRINT_DEBUG("Enabling Refresh\n");
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
reg32 |= (RAM_COMMAND_REFRESH << 8);
pci_write_config32(NORTHBRIDGE, DRC, reg32);
/* Set initialization complete */
- PRINT_DEBUG("Setting initialization complete\r\n");
+ PRINT_DEBUG("Setting initialization complete\n");
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
reg32 |= (RAM_COMMAND_IC << 29);
pci_write_config32(NORTHBRIDGE, DRC, reg32);
/* Setup Initial Northbridge Registers */
northbridge_set_registers();
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 2; i++) {
unsigned device;
device = ctrl->channel0[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
#if 0
device = ctrl->channel1[i];
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
}
static void dump_smbus_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
#endif
static void sdram_set_registers(const struct mem_controller *ctrl)
{
/*
- print_debug("Before configuration:\r\n");
+ print_debug("Before configuration:\n");
dump_pci_devices();
*/
}
adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9));
print_debug("Setting mode: ");
print_debug_hex32(adjusted_mode + addr);
- print_debug("\r\n");
+ print_debug("\n");
read32(adjusted_mode + addr);
}
{
int i;
uint32_t rank1 = (1 << 30) / 2;
- print_debug("Ram enable 1\r\n");
+ print_debug("Ram enable 1\n");
delay();
delay();
- print_debug("Ram enable 2\r\n");
+ print_debug("Ram enable 2\n");
ram_command(ctrl, 1, 0);
ram_command(ctrl, 1, rank1);
delay();
delay();
- print_debug("Ram enable 3\r\n");
+ print_debug("Ram enable 3\n");
ram_command(ctrl, 2, 0);
ram_command(ctrl, 2, rank1);
delay();
delay();
- print_debug("Ram enable 4\r\n");
+ print_debug("Ram enable 4\n");
ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, 0);
ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1);
delay();
delay();
- print_debug("Ram enable 5\r\n");
+ print_debug("Ram enable 5\n");
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0);
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1);
- print_debug("Ram enable 6\r\n");
+ print_debug("Ram enable 6\n");
ram_command(ctrl, 2, 0);
ram_command(ctrl, 2, rank1);
delay();
delay();
- print_debug("Ram enable 7\r\n");
+ print_debug("Ram enable 7\n");
for(i = 0; i < 8; i++) {
ram_command(ctrl, 6, 0);
ram_command(ctrl, 6, rank1);
delay();
}
- print_debug("Ram enable 8\r\n");
+ print_debug("Ram enable 8\n");
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, 0);
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, rank1);
- print_debug("Ram enable 9\r\n");
+ print_debug("Ram enable 9\n");
ram_command(ctrl, 7, 0);
ram_command(ctrl, 7, rank1);
delay();
delay();
- print_debug("Ram enable 9\r\n");
+ print_debug("Ram enable 9\n");
set_initialize_complete(ctrl);
delay();
delay();
delay();
- print_debug("After configuration:\r\n");
+ print_debug("After configuration:\n");
/* dump_pci_devices(); */
/*
- print_debug("\n\n***** RAM TEST *****\r\n");
+ print_debug("\n\n***** RAM TEST *****\n");
ram_check(0, 0xa0000);
ram_check(0x100000, 0x40000000);
*/
unsigned long bank_address;
- print_debug("CN400 RAM init starting\r\n");
+ print_debug("CN400 RAM init starting\n");
pci_write_config8(ctrl.d0f7, 0x75, 0x08);
*/
c = 0;
b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
- //print_val("Detecting Memory\r\nNumber of Banks ",b);
+ //print_val("Detecting Memory\nNumber of Banks ",b);
// Only supporting 4 bank chips just now
if( b == 4 ){
c = 0x01;
bank = 0x40;
b = smbus_read_byte(0x50, SPD_NUM_ROWS);
- //print_val("\r\nNumber of Rows ", b);
+ //print_val("\nNumber of Rows ", b);
if( b >= 0x0d ){ // 256/512Mb
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
- //print_val("\r\nPrimary DRAM width", b);
+ //print_val("\nPrimary DRAM width", b);
if( b != 4 ) // not 64/128Mb (x4)
c = 0x81; // 256Mb
}
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
- //print_val("\r\nNo Columns ",b);
+ //print_val("\nNo Columns ",b);
if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
- //print_val("\r\nMA type ", c);
+ //print_val("\nMA type ", c);
pci_write_config8(ctrl.d0f3, 0x50, c);
}
/* else
{
- die("DRAM module size is not supported by CN400\r\n");
+ die("DRAM module size is not supported by CN400\n");
}
*/
// SPD byte 5 # of physical banks
b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
- //print_val("\r\nNo Physical Banks ",b);
+ //print_val("\nNo Physical Banks ",b);
if( b == 2)
{
c <<=1;
}
/* else
{
- die("Only a single DIMM is supported by EPIA-N(L)\r\n");
+ die("Only a single DIMM is supported by EPIA-N(L)\n");
}
*/
// set banks 1,2,3...
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
-/* print_debug("\r\nCAS Supported ");
+/* print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
print_debug("3");
c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- print_val("\r\nCycle time at CL X (nS)", c);
+ print_val("\nCycle time at CL X (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
- print_val("\r\nCycle time at CL X-0.5 (nS)", c);
+ print_val("\nCycle time at CL X-0.5 (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
- print_val("\r\nCycle time at CL X-1 (nS)", c);
+ print_val("\nCycle time at CL X-1 (nS)", c);
*/
/* Scaling of Cycle Time SPD data */
/* 7 4 3 0 */
bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if( b & 0x10 ){ // DDR offering optional CAS 3
- //print_debug("\r\nStarting at CAS 3");
+ //print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
- //print_debug("\r\nWe can do CAS 2.5");
+ //print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
- //print_debug("\r\nWe can do CAS 2");
+ //print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
- //print_debug("\r\nStarting at CAS 2.5");
+ //print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
- //print_debug("\r\nWe can do CAS 2");
+ //print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
- //print_val("\r\ntRP ",b);
+ //print_val("\ntRP ",b);
if ( b >= (5 * bank)) {
c |= 0x03; // set tRP = 5T
}
*/
b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
- //print_val("\r\ntRCD ",b);
+ //print_val("\ntRCD ",b);
if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
bank = bank >> 2;
b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
- //print_val("\r\ntRAS ",b);
- //print_val("\r\nBank ", bank);
+ //print_val("\ntRAS ",b);
+ //print_val("\nBank ", bank);
if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
c &= 0x08;
if ( c == 0x08 )
{
- print_debug("Setting Burst Length 8\r\n");
+ print_debug("Setting Burst Length 8\n");
/*
CPU Frequency Device 0 Function 2 Offset 54
break;
}
- print_val("\r\nLow Bond ",i);
+ print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
print_val(" High Bond ",i);
c = ((i - c)<<1)/3 + c;
print_val(" Setting DQS delay",c);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(ctrl.d0f3,0x70,c);
}else{
pci_write_config8(ctrl.d0f3,0x70,0x67);
/* VGA device. */
pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
- print_debug("CN400 raminit.c done\r\n");
+ print_debug("CN400 raminit.c done\n");
}
}
if (result == 0xff)
- die("DRAM module size too big, not supported by CN700\r\n");
+ die("DRAM module size too big, not supported by CN700\n");
pci_write_config8(ctrl->d0f3, 0x40, result);
pci_write_config8(ctrl->d0f3, 0x48, 0x00);
u8 i;
/* 1. Apply NOP. */
- PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
do_ram_command(dev, RAM_COMMAND_NOP);
udelay(100);
read32(rank_address + 0x10);
/* 2. Precharge all. */
udelay(400);
- PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
read32(rank_address + 0x10);
/* 3. Mode register set. */
- PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS);
read32(rank_address + 0x120000); /* EMRS DLL Enable */
read32(rank_address + 0x800); /* MRS DLL Reset */
/* 4. Precharge all again. */
- PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
read32(rank_address + 0x0);
/* 5. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
do_ram_command(dev, RAM_COMMAND_CBR);
for (i = 0; i < 8; i++) {
read32(rank_address + 0x20);
}
/* 6. Mode register set. */
- PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
/* Safe value for now, BL=8, WR=5, CAS=4 */
/*
* (E)MRS values are from the BPG. No direct explanation is given, but
read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
/* 8. Normal operation */
- PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
do_ram_command(dev, RAM_COMMAND_NORMAL);
read32(rank_address + 0x30);
}
print_err("SMBus Error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\r\n");
+ print_err("SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\r\n");
+ print_debug("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
print_debug("SPD Data for DIMM ");
print_debug_hex8(dimm);
- print_debug("\r\n");
+ print_debug("\n");
val = get_spd_data(ctrl, dimm, 0);
if (val == 0xff) {
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\r\n");
+ print_debug("No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
print_debug_hex8(offset);
print_debug(" = 0x");
print_debug_hex8(get_spd_data(ctrl, dimm, offset));
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
print_debug_hex8(pci_read_config8(north, r + c));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
if (r >= 240)
break;
}
device_t north = (device_t) PCI_DEV(0, 0, 0);
uint8_t c, r;
- print_err("vt8601 init starting\r\n");
+ print_err("vt8601 init starting\n");
print_debug_hex32(north);
print_debug(" is the north\n");
print_debug_hex16(pci_read_config16(north, 0));
print_debug(" ");
print_debug_hex16(pci_read_config16(north, 2));
- print_debug("\r\n");
+ print_debug("\n");
/* All we are doing now is setting initial known-good values that will
* be revised later as we read SPD
print_info("Slot ");
print_info_hex8(slot);
if (smbus_read_byte(module, 2) != 4) {
- print_info(" is empty\r\n");
+ print_info(" is empty\n");
return 0;
}
print_info(" is SDRAM ");
print_info("x2");
value = (value << 16) | value;
}
- print_info("\r\n");
+ print_info("\n");
return value;
}
/* set NOP */
pci_write_config8(north, 0x6C, 0x01);
- print_debug("NOP\r\n");
+ print_debug("NOP\n");
/* wait 200us */
// You need to do the memory reference. That causes the nop cycle.
dimms_read(0);
udelay(400);
- print_debug("PRECHARGE\r\n");
+ print_debug("PRECHARGE\n");
/* set precharge */
pci_write_config8(north, 0x6C, 0x02);
- print_debug("DUMMY READS\r\n");
+ print_debug("DUMMY READS\n");
/* dummy reads */
dimms_read(0);
udelay(200);
- print_debug("CBR\r\n");
+ print_debug("CBR\n");
/* set CBR */
pci_write_config8(north, 0x6C, 0x04);
udelay(200);
dimms_read(0);
udelay(200);
- print_debug("MRS\r\n");
+ print_debug("MRS\n");
/* set MRS */
pci_write_config8(north, 0x6c, 0x03);
#if DIMM_CL2
dimms_read(0x1d0);
#endif
udelay(200);
- print_debug("NORMAL\r\n");
+ print_debug("NORMAL\n");
/* set to normal mode */
pci_write_config8(north, 0x6C, 0x08);
dimms_write(0x55aa55aa);
dimms_read(0);
udelay(200);
- print_debug("set ref. rate\r\n");
+ print_debug("set ref. rate\n");
// Set the refresh rate.
#if DIMM_PC133
pci_write_config8(north, 0x6A, 0x86);
#else
pci_write_config8(north, 0x6A, 0x65);
#endif
- print_debug("enable multi-page open\r\n");
+ print_debug("enable multi-page open\n");
// enable multi-page open
pci_write_config8(north, 0x6B, 0x0d);
else /* 256MB or more per side */
ma = 0xe;
print_debug_hex16(ma);
- print_debug(" is the MA type\r\n");
+ print_debug(" is the MA type\n");
set_ma_mapping(north, slot, ma);
}
- print_err("vt8601 done\r\n");
+ print_err("vt8601 done\n");
}
print_debug_hex8(pci_read_config8(north, r+c));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
void print_val(char *str, int val)
uint16_t i,j;
unsigned long bank_address;
- print_debug("vt8623 init starting\r\n");
+ print_debug("vt8623 init starting\n");
north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
north = 0;
*/
c = 0;
b = smbus_read_byte(0xa0,17);
- print_val("Detecting Memory\r\nNumber of Banks ",b);
+ print_val("Detecting Memory\nNumber of Banks ",b);
if( b != 2 ){ // not 16 Mb type
Read SPD byte 3, Number of row addresses.
*/
b = smbus_read_byte(0xa0,3);
- print_val("\r\nNumber of Rows ",b);
+ print_val("\nNumber of Rows ",b);
if( b >= 0x0d ){ // not 64/128Mb (rows <=12)
/*
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0xa0,13);
- print_val("\r\nPriamry DRAM width",b);
+ print_val("\nPriamry DRAM width",b);
if( b != 4 ) // mot 64/128Mb (x4)
c = 0x80; // 256Mb
}
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0xa0,4);
- print_val("\r\nNo Columns ",b);
+ print_val("\nNo Columns ",b);
if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
}
- print_val("\r\nMA type ",c);
+ print_val("\nMA type ",c);
pci_write_config8(north,0x58,c);
/*
else c = 0x01; // Error, use default
- print_val("\r\nBank 0 (*16 Mb) ",c);
+ print_val("\nBank 0 (*16 Mb) ",c);
// set bank zero size
pci_write_config8(north,0x5a,c);
// SPD byte 5 # of physical banks
b = smbus_read_byte(0xa0,5);
- print_val("\r\nNo Physical Banks ",b);
+ print_val("\nNo Physical Banks ",b);
if( b == 2)
c <<=1;
- print_val("\r\nTotal Memory (*16 Mb) ",c);
+ print_val("\nTotal Memory (*16 Mb) ",c);
// set banks 1,2,3
pci_write_config8(north,0x5b,c);
pci_write_config8(north,0x5c,c);
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0xa0,18);
- print_debug("\r\nCAS Supported ");
+ print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
print_debug("2.5 ");
if(b & 0x10)
print_debug("3");
- print_val("\r\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
- print_val("\r\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
- print_val("\r\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
+ print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
+ print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
+ print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
if( b & 0x10 ){ // DDR offering optional CAS 3
- print_debug("\r\nStarting at CAS 3");
+ print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
- print_debug("\r\nWe can do CAS 2.5");
+ print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
- print_debug("\r\nWe can do CAS 2");
+ print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
- print_debug("\r\nStarting at CAS 2.5");
+ print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
- print_debug("\r\nWe can do CAS 2");
+ print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
*/
b = smbus_read_byte(0xa0,27);
- print_val("\r\ntRP ",b);
+ print_val("\ntRP ",b);
if( b > 0x3c ) // set tRP = 3T
c |= 0x80;
*/
b = smbus_read_byte(0xa0,29);
- print_val("\r\ntRCD ",b);
+ print_val("\ntRCD ",b);
if( b > 0x3c ) // set tRCD = 3T
c |= 0x04;
*/
b = smbus_read_byte(0xa0,30);
- print_val("\r\ntRAS ",b);
+ print_val("\ntRAS ",b);
if( b > 0x25 ) // set tRAS = 6T
c |= 0x40;
break;
}
- print_val("\r\nLow Bond ",i);
+ print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
pci_write_config8(north,0x68,c);
pci_write_config8(north,0x68,0x42);
}else{
- print_debug("Unable to determine low bond - Setting default\r\n");
+ print_debug("Unable to determine low bond - Setting default\n");
pci_write_config8(north,0x68,0x59);
}
pci_write_config8(north,0xac,0x2f);
pci_write_config8(north,0xae,0x04);
- print_debug("vt8623 done\r\n");
+ print_debug("vt8623 done\n");
dumpnorth(north);
- print_debug("AGP\r\n");
+ print_debug("AGP\n");
north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
pci_write_config32(north,0x20,0xddf0dc00);
pci_write_config32(north,0x24,0xdbf0d800);
device_t dev;
u16 tmp, result;
- print_debug("In acpi_is_wakeup_early_via_vx800\r\n");
+ print_debug("In acpi_is_wakeup_early_via_vx800\n");
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\r\n");
+ die("Power management controller not found\n");
/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
print_debug(" boot_mode=");
print_debug_hex16(result);
- print_debug("\r\n");
+ print_debug("\n");
return result;
}
device_t dev;
uint16_t values;
- print_debug("In enable_mainboard_devices \r\n");
+ print_debug("In enable_mainboard_devices \n");
/*
Enable P2P Bridge Header for External PCI BUS.
if (bist == 0) {
// CAR need mtrr untill mem is ok, so i disable this early_mtrr_init();
- //print_debug("doing early_mtrr\r\n");
+ //print_debug("doing early_mtrr\n");
//early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
u8 Data;
Data = pci_read_config8(device, 0xf6);
print_debug("NB chip revision =");
print_debug_hex8(Data);
- print_debug("\r\n");
+ print_debug("\n");
/* make NB ready before draminit */
via_pci_inittable(Data, mNbStage1InitTbl);
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
DRAM_SYS_ATTR DramAttr;
- print_debug("This is a S3 wakeup\r\n");
+ print_debug("This is a S3 wakeup\n");
memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
/*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */
DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here!
SetUMARam(); // I just copy this function from draminit to here!
- print_debug("Resume from S3, RAM init was ignored\r\n");
+ print_debug("Resume from S3, RAM init was ignored\n");
} else {
ddr2_ram_setup();
ram_check(0, 640 * 1024);
"rep movsd\n\t"
::"g"(memtop4)
);*/
- print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n"); //this can have function call, because no variable used before this
+ print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this
memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
64 * 1024 - 0x100000),
(unsigned char *) 0, 0xa0000);
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)
);
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
+ printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
#else
print_debug("v_esp=");
print_debug_hex32(v_esp);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
//stack
cpu_reset = 0;
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
+ printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
#else
print_debug("cpu_reset = ");
print_debug_hex32(cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
if (cpu_reset == 0) {
/* We can not go back any more, we lost old stack data in cache as ram */
if (new_cpu_reset == 0) {
- print_debug("Use Ram as Stack now - done\r\n");
+ print_debug("Use Ram as Stack now - done\n");
} else {
- print_debug("Use Ram as Stack now - \r\n");
+ print_debug("Use Ram as Stack now - \n");
}
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
+ printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = ");
print_debug_hex32(new_cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
/*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
#endif
- print_debug("should not be here -\r\n");
+ print_debug("should not be here -\n");
}
}
#else
/* Attempt to manually force the rom to load */
- printk(BIOS_DEBUG, "Forcing rom load\r\n");
+ printk(BIOS_DEBUG, "Forcing rom load\n");
pci_rom_load(dev, 0xfff80000);
run_bios(dev, 0xc0000);
#endif
/* Internal functions */
static void smbus_print_error(unsigned char host_status_register, int loops)
{
-// print_err("some i2c error\r\n");
+// print_err("some i2c error\n");
/* Check if there actually was an error */
if (host_status_register == 0x00 || host_status_register == 0x40 ||
host_status_register == 0x42)
return;
print_err("smbus_error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\r\n");
+ print_err("SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\r\n");
+ print_debug("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
if (dev == PCI_DEV_INVALID) {
/* This won't display text if enable_smbus() is before serial init */
- die("Power Managment Controller not found\r\n");
+ die("Power Managment Controller not found\n");
}
/* Set clock source */
ram_slots = ARRAY_SIZE(ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
+ print_err("smbus_fixup() thinks there are no RAM slots!\n");
return;
}
}
if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\r\n");
+ print_err("SMBus timed out while warming up\n");
else
- PRINT_DEBUG("Done\r\n");
+ PRINT_DEBUG("Done\n");
}
/* Debugging Function */
for (dimm = 0; dimm < 8; dimm++) {
print_debug("SPD Data for DIMM ");
print_debug_hex8(dimm);
- print_debug("\r\n");
+ print_debug("\n");
val = get_spd_data(dimm, 0);
if (val == 0xff) {
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\r\n");
+ print_debug("No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
print_debug_hex8(offset);
print_debug(" = 0x");
print_debug_hex8(get_spd_data(dimm, offset));
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
}
pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
/* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
- print_spew("SMBus controller enabled\r\n");
+ print_spew("SMBus controller enabled\n");
}
static int smbus_recv_byte(unsigned device)
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
- print_debug("reboot from BIOS reset\n\r");
+ print_debug("reboot from BIOS reset\n");
return;
}
- print_debug("Setup idsel\r\n");
+ print_debug("Setup idsel\n");
cs5535_setup_idsel();
- print_debug("Setup iobase\r\n");
+ print_debug("Setup iobase\n");
cs5535_usb_swapsif();
cs5535_setup_iobase();
- print_debug("Setup gpio\r\n");
+ print_debug("Setup gpio\n");
cs5535_setup_gpio();
- print_debug("Setup cis_mode\r\n");
+ print_debug("Setup cis_mode\n");
cs5535_setup_cis_mode();
- print_debug("Setup smbus\r\n");
+ print_debug("Setup smbus\n");
cs5535_enable_smbus();
dummy();
}
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
- //print_debug("reboot from BIOS reset\n\r");
+ //print_debug("reboot from BIOS reset\n");
return;
}
- //print_debug("Setup idsel\r\n");
+ //print_debug("Setup idsel\n");
cs5536_setup_idsel();
- //print_debug("Setup iobase\r\n");
+ //print_debug("Setup iobase\n");
cs5536_usb_swapsif();
cs5536_setup_iobase();
- //print_debug("Setup gpio\r\n");
+ //print_debug("Setup gpio\n");
cs5536_setup_gpio();
- //print_debug("Setup smbus\r\n");
+ //print_debug("Setup smbus\n");
cs5536_enable_smbus();
- //print_debug("Setup power button\r\n");
+ //print_debug("Setup power button\n");
cs5536_setup_power_button();
}
print_debug_hex8(error);
print_debug(" device:");
print_debug_hex8(device);
- print_debug("\r\n");
+ print_debug("\n");
/* stop, clean up the error, and leave */
smbus_stop_condition(smbus_io_base);
outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
/* NOT REACHED */
}
return pci_read_config8(dev, 0x08);
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
/* NOT REACHED */
}
- printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n",
+ printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision());
/* sbPorAtStartOfTblCfg */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
/* NOT REACHED */
}
rev_id = pci_read_config8(dev, 0x08);
} else if (rev_id == 0x3D) {
rev = 0x15;
} else
- die("It is not SB700 or SB710\r\n");
+ die("It is not SB700 or SB710\n");
return rev;
}
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
/* NOT REACHED */
}
- printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\r\n",
+ printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n",
set_sb700_revision());
/* sbPorAtStartOfTblCfg */
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
}
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* Set smbus iospace enable */
if(!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
- printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n",dev_path(child),base, end);
+ printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) {
case 0x60: //KBC
case 0x64:
for(i=0; i<4; i++) {
mmio = base + 0x100 * i;
byte = read8(mmio + 0x40);
- printk(BIOS_DEBUG, "port %d PHY status = %02x\r\n", i, byte);
+ printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
if(byte & 0x4) {// bit 2 is set
byte = read8(mmio+0x48);
write8(mmio + 0x48, byte | 1);
write8(mmio + 0x48, byte & (~1));
byte = read8(mmio + 0x40);
- printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\r\n", i, byte);
+ printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
}
}
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\r\n");
+ print_spew("SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
pci_write_config8(dev, 0x40, 1);
pci_write_config8(dev, 0x4, 1);
SMBUS_IO_BASE + SMBHSTSTAT);
}
- print_debug("SMBUS Block complete\r\n");
+ print_debug("SMBUS Block complete\n");
return 0;
}
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\r\n");
+ print_spew("SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
pci_write_config8(dev, 0x40, 1);
pci_write_config8(dev, 0x4, 1);
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
if (dev == PCI_DEV_INVALID)
- die("SMBus controller not found\r\n");
+ die("SMBus controller not found\n");
- print_spew("SMBus controller enabled\r\n");
+ print_spew("SMBus controller enabled\n");
/* Set the SMBus I/O base. */
pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
#if 0
print_debug("Read fail ");
print_debug_hex16(status_register);
- print_debug("\r\n");
+ print_debug("\n");
#endif
return SMBUS_ERROR;
}
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
}
static inline int smbus_read_byte(unsigned device, unsigned address)
static void smbus_write_byte(unsigned device, unsigned address,
unsigned char val)
{
- print_err("Unimplemented smbus_write_byte() called\r\n");
+ print_err("Unimplemented smbus_write_byte() called\n");
return;
}
unsigned data1, unsigned data2)
{
#warning "do_smbus_write_block is commented out"
- print_err("Untested smbus_write_block called\r\n");
+ print_err("Untested smbus_write_block called\n");
#if 0
unsigned char global_control_register;
unsigned char global_status_register;
SMBUS_IO_BASE + SMBHSTSTAT);
}
- print_debug("SMBUS Block complete\r\n");
+ print_debug("SMBUS Block complete\n");
return 0;
#endif
}
outw(0x0008, base + 0x04);
outw(0x0002, base + 0x06);
- printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n");
+ printk(BIOS_DEBUG, "ICH Watchdog disabled\n");
}
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
}
static inline int smbus_read_byte(unsigned device, unsigned address)
static void smbus_write_byte(unsigned device, unsigned address,
unsigned char val)
{
- print_err("Unimplemented smbus_write_byte() called\r\n");
+ print_err("Unimplemented smbus_write_byte() called\n");
return;
}
unsigned data1, unsigned data2)
{
#warning "do_smbus_write_block is commented out"
- print_err("Untested smbus_write_block called\r\n");
+ print_err("Untested smbus_write_block called\n");
#if 0
unsigned char global_control_register;
unsigned char global_status_register;
SMBUS_IO_BASE + SMBHSTSTAT);
}
- print_debug("SMBUS Block complete\r\n");
+ print_debug("SMBUS Block complete\n");
return 0;
#endif
}
outw(0x0008, base + 0x04);
outw(0x0002, base + 0x06);
- printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n");
+ printk(BIOS_DEBUG, "ICH Watchdog disabled\n");
}
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* Set smbus enable */
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
/* Set smbus enable */
unsigned char global_status_register;
unsigned char byte;
- /*print_err("smbus_read_byte\r\n"); */
+ /*print_err("smbus_read_byte\n"); */
if (smbus_wait_until_ready() < 0) {
print_err_hex8(-2);
return -2;
/*
print_err("smbus_read_byte: ");
print_err_hex32(device); print_err(" ad "); print_err_hex32(address);
- print_err("value "); print_err_hex8(byte); print_err("\r\n");
+ print_err("value "); print_err_hex8(byte); print_err("\n");
*/
return byte;
}
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\r\n");
+ print_spew("SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
print_debug_hex32(pci_read_config32(dev, 0x20));
return;
}
- print_debug("Unimplemented smbus_write_byte() called.\r\n");
+ print_debug("Unimplemented smbus_write_byte() called.\n");
#if 0
/* setup transaction */
SMBUS_IO_BASE + SMBHSTSTAT);
}
- print_debug("SMBUS Block complete\r\n");
+ print_debug("SMBUS Block complete\n");
return 0;
}
/* Clear TCO timeout status */
outw(0x0008, base + 0x04);
outw(0x0002, base + 0x06);
- printk(BIOS_DEBUG, "Watchdog ICH5 disabled\r\n");
+ printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
}
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\r\n");
+ print_debug("SMBus controller enabled.\n");
}
static inline int smbus_read_byte(unsigned device, unsigned address)
outw(0x0008, base + 0x04);
outw(0x0002, base + 0x06);
- printk(BIOS_DEBUG, "ICH7 watchdog disabled\r\n");
+ printk(BIOS_DEBUG, "ICH7 watchdog disabled\n");
}
device_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0);
if (dev == PCI_DEV_INVALID)
- die("SMBus controller not found\r\n");
+ die("SMBus controller not found\n");
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
/* Set SMBus I/O base. */
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
continue;
base = res->base;
end = resource_end(res);
- printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
+ printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end);
switch (base) {
case 0x3f8: // COM1
reg |= (1 << 0);
return;
dword = *(base + 0);
- printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword);
+ printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword);
if (dword == 0x113) {
loop = 200000; // 2
do {
break;
udelay(10);
} while (--loop > 0);
- printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword);
+ printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword);
}
dword = *(base + 0x40);
- printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword);
+ printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword);
if (dword == 0x113) {
loop = 200000; //2
do {
break;
udelay(10);
} while (--loop > 0);
- printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
+ printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword);
}
}
#endif
}
out:
- print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n");
+ print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n");
mcp55_early_set_port(mcp55_num, busn, devn, io_base);
mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
#if 0
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
}
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
#endif
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
for(i=0;i<0xff;i+=4){
if((i%16)==0){
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
for(i=0;i<0xff;i+=4){
if((i%16)==0){
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
print_debug("IDE_INIT:<----------\n");
if(!res)
{
- printk(BIOS_DEBUG, "NIC Cannot find resource..\r\n");
+ printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
}
base = res->base;
if(!(val=phy_detect(base,&PhyAddr)))
{
- printk(BIOS_DEBUG, "PHY detect fail !!!!\r\n");
+ printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
return;
}
for(i=0;i<0xff;i+=4){
if((i%16)==0){
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
for(i=0;i<0xff;i+=4){
if((i%16)==0){
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
for(i=0;i<0xff;i+=4){
if((i%16)==0){
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
print_debug("USB 1.1 INIT:<----------\n");
for(i=0;i<0xff;i+=4){
if((i%16)==0){
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
print_debug("USB 2.0 INIT:<----------\n");
if (dev == PCI_DEV_INVALID) {
outb(7, 0x80);
- die("Serial controller not found\r\n");
+ die("Serial controller not found\n");
}
/* first, you have to enable the superio and superio config.
dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
}
// set IO base address to SMBUS_IO_BASE
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
c |= 1;
pci_write_config8(dev, 4, c);
print_debug_hex8(c);
- print_debug(" is the comm register\r\n");
+ print_debug(" is the comm register\n");
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
}
smbus_wait_until_ready();
print_debug("After reset status ");
print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
- print_debug("\r\n");
+ print_debug("\n");
}
static void smbus_print_error(unsigned char host_status_register)
print_err("smbus_error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
- print_err("Interrupt/SMI# was Successful Completion\r\n");
+ print_err("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
}
// set IO base address to SMBUS_IO_BASE
while((c & 1) == 1) {
print_debug("c is ");
print_debug_hex8(c);
- print_debug("\r\n");
+ print_debug("\n");
c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
/* nop */
}
smbus_wait_until_ready();
print_debug("After reset status ");
print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
- print_debug("\r\n");
+ print_debug("\n");
}
print_err("smbus_error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
- print_err("Interrupt/SMI# was Successful Completion\r\n");
+ print_err("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
return;
if (loops >= SMBUS_TIMEOUT)
- print_err("SMBus timeout\r\n");
+ print_err("SMBus timeout\n");
if (host_status & (1 << 4))
- print_err("Interrupt/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrupt/SMI# was Failed Bus Transaction\n");
if (host_status & (1 << 3))
- print_err("Bus error\r\n");
+ print_err("Bus error\n");
if (host_status & (1 << 2))
- print_err("Device error\r\n");
+ print_err("Device error\n");
if (host_status & (1 << 1))
- print_debug("Interrupt/SMI# completed successfully\r\n");
+ print_debug("Interrupt/SMI# completed successfully\n");
if (host_status & (1 << 0))
- print_err("Host busy\r\n");
+ print_err("Host busy\n");
}
/**
{
int loops;
- PRINT_DEBUG("Waiting until SMBus ready\r\n");
+ PRINT_DEBUG("Waiting until SMBus ready\n");
loops = 0;
/* Yes, this is a mess, but it's the easiest way to do it. */
PRINT_DEBUG("After reset status: ");
PRINT_DEBUG_HEX16(inb(SMBHSTSTAT));
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
/**
PRINT_DEBUG_HEX16(dimm);
PRINT_DEBUG(" OFFSET ");
PRINT_DEBUG_HEX16(offset);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
smbus_reset();
val = inb(SMBHSTDAT0);
PRINT_DEBUG("Read: ");
PRINT_DEBUG_HEX16(val);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* Probably don't have to do this, but it can't hurt. */
smbus_reset();
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\r\n");
+ die("Power management controller not found\n");
}
/*
ram_slots = ARRAY_SIZE(ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
+ print_err("smbus_fixup() thinks there are no RAM slots!\n");
return;
}
}
if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\r\n");
+ print_err("SMBus timed out while warming up\n");
else
- PRINT_DEBUG("Done\r\n");
+ PRINT_DEBUG("Done\n");
}
/* FIXME: Better separate the NB and SB, will be done once it works. */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\r\n");
+ die("Power management controller not found\n");
}
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("SB not found\r\n");
+ die("SB not found\n");
/* Put SPI base 20 d0 fe. */
tmp = pci_read_config32(dev, 0xbc);
if (sbdev == PCI_DEV_INVALID) {
/* Serial output is not yet working at this point, but
* die() emits the POST code 0xff and halts the CPU, too. */
- die("Southbridge not found.\r\n");
+ die("Southbridge not found.\n");
}
/* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */
/* Read out current value of FAN_CTL control register (0x14). */
value = pnp_read_index(base, 0x14);
- printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
+ printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n",
base + 0x14, value);
/* Set FAN_CTL control register (0x14) polarity to high, and
activate fans 1, 2 and 3. */
pnp_write_index(base, 0x14, value | 0x87);
- printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
+ printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n",
base + 0x14, value | 0x87);
}
#endif
print_debug("Using port: ");
print_debug_hex16(port);
- print_debug("\r\n");
+ print_debug("\n");
pilot_disable_serial(PNP_DEV(port, 0x1));
- print_debug("disable serial 1\r\n");
+ print_debug("disable serial 1\n");
/*
pnp_enter_ext_func_mode(dev);
static void dump_pnp_device(device_t dev)
{
int register_index;
- print_debug("\r\n");
+ print_debug("\n");
for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
uint8_t register_value;
print_debug_char(' ');
print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
switch(dev->path.pnp.device) {
case LPC47B397_HWM:
- printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\r\n");
+ printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\n");
pnp_set_logical_device(dev);
enable_hwm_smbus(dev);
break;
static void dump_pnp_device(device_t dev)
{
int register_index;
- print_debug("\r\n");
+ print_debug("\n");
for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) {
uint8_t register_value;
print_debug_char(' ');
print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
static void dump_pnp_device(device_t dev)
{
int register_index;
- print_debug("\r\n");
+ print_debug("\n");
for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
uint8_t register_value;
print_debug_char(' ');
print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
value = pnp_read_index(base, reg);
value &= 0xff & (~(hwm_reg_values[i + 1]));
value |= 0xff & hwm_reg_values[i + 2];
- /* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); */
+ /* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value); */
pnp_write_index(base, reg, value);
}
}
value &= 0xff & hwm_reg_values[i+1];
value |= 0xff & hwm_reg_values[i+2];
#if 0
- printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
+ printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value);
#endif
pnp_write_index(base, reg, value);
}
projects / coreboot.git / commitdiff