- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1

- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/include/ehci.h b/src/include/ehci.h
index 5dc2bb3935a5465792173f20b121e2ba9462cb2d..4b8c94cd24f98f32db654b28a31e73a67e781e32 100644 (file)
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -23,6 +23,8 @@
 #ifndef EHCI_H
 #define EHCI_H
 
+#define EHCI_BAR_INDEX         0x10
+
 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 
 /* Section 2.2 Host Controller Capability Registers */

diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 54d817afe533bd9749c4a0c4799929efc48e8682..710675f4d47aeb4ef68a4bb33369649998167ead 100644 (file)
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -41,6 +41,7 @@ void set_ehci_base(unsigned ehci_base);
 void set_ehci_debug(unsigned ehci_deug);
 unsigned get_ehci_debug(void);
 void set_debug_port(unsigned port);
+void early_usbdebug_init(void);
 void usbdebug_ram_tx_byte(unsigned char data);
 void usbdebug_tx_byte(unsigned char data);
 

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index f7f40536f4dbb29e9e188ef896c2ea86b6cfeede..9635e39fd00a7bdd1020ac011d62f342c79e41bd 100644 (file)
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -51,10 +51,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 16ea5f204fd0dbffb9d7510cfbc337e9d3850399..702b97965e6f935bce4b04e8cc6d0461b57c1d1a 100644 (file)
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -50,11 +50,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index d5a907c64ed6d2aafabbecacaf5c5aa5f45580c5..64e02f49e029ce8cec89c3a064caa011d811424a 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index a3909f47995ff2bc2d82d102195f8312fb7c39e0..51269b1cf65264e3e864d37ed4c6efc605ac3256 100644 (file)
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -45,11 +45,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 1e331fe7170f8897b5475a28bc75aa353d0c54d0..b0da2aec6c62a54faad8a60083c2f5efae372e22 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index dac230734ba9cbe3aa5aa301bc5dade6737609ea..1a01e5d0f5a0cc1b0dc5ea3a24c7877e0415d1e4 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -51,11 +51,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index cae04485a62d2fbdca09e60bc0a2a89169362188..4d16ab703625b0ddf4c535b672959e5a16ef869f 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index bf11cb5227d013610219ab392c5c9945330c9afc..5416d0cdae9036580a95c834fd90471d520a7d39 100644 (file)
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -27,6 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <usbdebug.h>
 
 #include <pc80/mc146818rtc.h>
 

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 7692c08bcf07f6d9ed3b7dea17ab7ce4a9efbb0b..9e186eba560763cdd579c9b20562423ef1760b85 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -51,13 +51,11 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/sis/sis966/sis966_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
+#include "southbridge/sis/sis966/sis966.h"
 #include "southbridge/sis/sis966/sis966_early_smbus.c"
 #include "southbridge/sis/sis966/sis966_enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 59174d7e5642484f8fd0614a42bbe36ba6e1b13b..01c989ab258461e513e2bec9c499124cc35c6c1d 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -49,10 +49,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index c97f275027401a04b57bdb9c15aec422ff7af943..b32fea8271ccb493b6cb3b8bb74cc91785efc108 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -55,11 +55,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 9225e2616e7b8eaabacf7359190205e64169fe49..ca39156b35d90cacbf21727bbe5a6d72970d8374 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index cd131705b9b4aa47989235db8b33f5978a6bbf6e..a97b0a1e2ea656f300acd469116c72ecbe84dcfd 100644 (file)
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
 
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index d9790b37cd33298dc65194d087ec209c72d35e81..c623297bbd388a7be00dc0fc5c178a7cf504bf8a 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -62,11 +62,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/fintek/f71859/f71859_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 9b7f2deeee9550c6a3e1e8ec5d7f7f36c098fac6..237642b74726082942ad9e6a99f6d03dac65434f 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
 
 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index fc18ba98875d5612b8b375251b25557f2fca99aa..0ccfaccb5c0cdb40969a239cf1e744dfad2ed8ed 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -66,10 +66,7 @@ static int smbus_read_byte(u32 device, u32 address);
 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
 #endif
 
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 201d90378fe28f5c0cc6cccb7b3751f6fb22b90d..f974128604992c93cbed7707c4a19e5076cf9415 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -27,6 +27,7 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <usbdebug.h>
 
 #include "superio/winbond/w83627thg/w83627thg.h"
 

diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index c756af6d1ca9246a53115bf0af177a6e777707f8..6b65b4db6ed0d4ea23c819eb576e3786791e7972 100644 (file)
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -53,10 +53,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
 
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 53a6aae241a9bbc8a895267376ffcb809e718577..762da8ced5812f0fdac125ac65da15f898143395 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -52,10 +52,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 0bc38368095352e12c331a1ed2f2f54dbcc1d5e4..a7dcaedb3d2f18f098c9a13435660e42a6f5c2c9 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -42,10 +42,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>

diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 7917a3db014afff1fab7e7a4f52814427eda7894..dc76e0a32ed7573a10dd0900ddecb36e0ef2c824 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -49,10 +49,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 4942788420b025bf4fdf377f578ffd2414bde792..78f041f3a7fbf17cf757ff5dc6e727cf3747a2d9 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
 
 #include "northbridge/intel/i945/i945.h"

diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index ddcb2ba474447cece611605604a85331ada7f15d..3291d55c80aa681c874e432499d28378841896cc 100644 (file)
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -51,11 +51,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 863b8e6f3fc04d5b56c18371e53e5d2cf962eafa..3bf157409c1591ec04e06e60ea7a86eb1b91cafe 100644 (file)
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -51,11 +51,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 2d3e12643e427d7ec48b23609e3c228541d0f075..c7078bbb3417ab231c8ada32d3d3886cefbf0ee3 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -49,11 +49,8 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
 #include <lib.h>
+#include <usbdebug.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index b294c7e51c5ac232124d9050bc6c5d2abd935e4f..d287dc4313ebf4c63a98f736bb5f3f260b682588 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -42,10 +42,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>

diff --git a/src/pc80/usbdebug_serial.c b/src/pc80/usbdebug_serial.c
index c58dce1294d75f9c71a4343aab4c35a55a9798e1..a330ea66952afd45c6a8ae36cddae165d8d572f4 100644 (file)
--- a/src/pc80/usbdebug_serial.c
+++ b/src/pc80/usbdebug_serial.c
@@ -19,13 +19,15 @@
  */
 
 #include "../lib/usbdebug.c"
+#include <arch/io.h>
+#include <ehci.h>
 
-static void early_usbdebug_init(void)
+void early_usbdebug_init(void)
 {
        struct ehci_debug_info *dbg_info = (struct ehci_debug_info *)
            (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info));
 
-       usbdebug_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info);
+       usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
 }
 
 void usbdebug_tx_byte(unsigned char data)

diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index ed4072dc2eecd2abb7afe40bcb3c65441a444705..5af6b134e0914d1ead2dec5445981a242463d451 100644 (file)
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -22,3 +22,11 @@ config SOUTHBRIDGE_AMD_SB600
        select IOAPIC
        select HAVE_USBDEBUG
 
+config EHCI_BAR
+       hex
+       default 0xfef00000 if SOUTHBRIDGE_AMD_SB600
+
+config EHCI_DEBUG_OFFSET
+       hex
+       default 0xe0 if SOUTHBRIDGE_AMD_SB600
+

diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc
index b13d3de01f264c9cc68033d2a5056971ab2bbab9..854539b9b3e2f82c42d86eb3b9569bf13a846ebd 100644 (file)
--- a/src/southbridge/amd/sb600/Makefile.inc
+++ b/src/southbridge/amd/sb600/Makefile.inc
@@ -8,3 +8,4 @@ driver-y += sb600_hda.c
 driver-y += sb600_ac97.c
 driver-y += sb600_pci.c
 ramstage-y += sb600_reset.c
+romstage-y += sb600_enable_usbdebug.c

diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 629f389973c4cb523e8b3fb851b60cc79d06db79..0ba107acc7b9b48637c535d43c2ed08346e5198a 100644 (file)
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -40,4 +40,5 @@ void sb600_enable(device_t dev);
 void sb600_lpc_port80(void);
 void sb600_pci_port80(void);
 
+void sb600_enable_usbdebug(unsigned int port);
 #endif /* SB600_H */

diff --git a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
index 6a150aded0c7b9b4907bb6fab30e75fbe47e187c..b4d97b0da2ae85283c5d5c1c049670543a5b5675 100644 (file)
--- a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
@@ -18,12 +18,11 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
-
-#define EHCI_BAR               0xFEF00000      /* EHCI BAR address */
-#define EHCI_BAR_INDEX         0x10            /* TODO: DBUG_PRT[31:29] */
-#define EHCI_DEBUG_OFFSET      0xE0            /* Hardcoded to 0xE0 */
+#include "sb600.h"
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
@@ -31,7 +30,7 @@ void set_debug_port(unsigned int port)
        /* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-static void sb600_enable_usbdebug(unsigned int port)
+void sb600_enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
 
@@ -39,7 +38,7 @@ static void sb600_enable_usbdebug(unsigned int port)
        set_debug_port(port);
 
        /* Set the EHCI BAR address. */
-       pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+       pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
        /* Enable access to the EHCI memory space registers. */
        pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 5ceb446a82365470e0f3f8ef9ecfedc8fa5ac1d6..97768d18e5da469025f7efa3ee07a30454b8f9be 100644 (file)
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -27,3 +27,11 @@ config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
        default n
        depends on SOUTHBRIDGE_AMD_SB700
 
+config EHCI_BAR
+       hex
+       default 0xfef00000 if SOUTHBRIDGE_AMD_SB700
+
+config EHCI_DEBUG_OFFSET
+       hex
+       default 0xe0 if SOUTHBRIDGE_AMD_SB700
+

diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc
index 8e6868bb172231e22a9c5a25d263b8f37f6d05ad..dd97df31e62ba744a079509ebc961ce8b7a8fb43 100644 (file)
--- a/src/southbridge/amd/sb700/Makefile.inc
+++ b/src/southbridge/amd/sb700/Makefile.inc
@@ -7,3 +7,4 @@ driver-y += sb700_sata.c
 driver-y += sb700_hda.c
 driver-y += sb700_pci.c
 ramstage-y += sb700_reset.c
+romstage-y += sb700_enable_usbdebug.c

diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index d4107a942eb3d94fc056509f42c94ab362fce81d..088bba611dca9279ca6332310ac2190cb74ce8f9 100644 (file)
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -59,4 +59,5 @@ void sb700_setup_sata_phys(struct device *dev);
 
 #endif
 
+void sb700_enable_usbdebug(unsigned int port);
 #endif /* SB700_H */

diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
index 02d3900047120d76d7d406ba71e0431d54df52a7..d74a9bbc9f920fa2bfaa2da502cbf4796bce4701 100644 (file)
--- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
@@ -19,14 +19,13 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "sb700.h"
 
-#define EHCI_BAR               0xFEF00000      /* EHCI BAR address */
-#define EHCI_BAR_INDEX         0x10            /* TODO: DBUG_PRT[31:29] */
-#define EHCI_DEBUG_OFFSET      0xE0            /* Hardcoded to 0xE0 */
-
-#define EHCI_EOR               (EHCI_BAR + 0x20)
+#define EHCI_EOR               (CONFIG_EHCI_BAR + 0x20)
 #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80)
 
 void set_debug_port(unsigned int port)
@@ -46,12 +45,12 @@ void set_debug_port(unsigned int port)
  * This code currently only supports the first one, i.e., USB Debug devices
  * attached to physical USB ports belonging to the first EHCI device.
  */
-static void sb700_enable_usbdebug(unsigned int port)
+void sb700_enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 
        /* Set the EHCI BAR address. */
-       pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+       pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
        /* Enable access to the EHCI memory space registers. */
        pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 556f526735333ea96077319a896430b4393160bd..afee190b2d08e36eec986f8930d346cde8532354 100644 (file)
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,3 +24,11 @@ config SOUTHBRIDGE_INTEL_I82801GX
        select HAVE_USBDEBUG
        select USE_WATCHDOG_ON_BOOT
 
+config EHCI_BAR
+       hex
+       default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX
+
+config EHCI_DEBUG_OFFSET
+       hex
+       default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX
+

diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index b5a2054526df18ad48ddcdf0ca33a3a849cb038e..559c896901c8458e9813ca58f79ab33fc05eba93 100644 (file)
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -39,10 +39,13 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
+#if !defined(ASSEMBLY)
 #if !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801gx_enable(device_t dev);
 #endif
+void i82801gx_enable_usbdebug(unsigned int port);
+#endif
 
 #define MAINBOARD_POWER_OFF    0
 #define MAINBOARD_POWER_ON     1

diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
index 464dac2b926ddddf06b5850443490f7806880a7d..991aa5adaaededf2838dffe207ffd1e7732c3d06 100644 (file)
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
@@ -18,12 +18,12 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
-
-#define EHCI_BAR               0xFEF00000      /* EHCI BAR address */
-#define EHCI_BAR_INDEX         0x10            /* Hardwired 0x10 (>= ICH4). */
-#define EHCI_DEBUG_OFFSET      0xA0            /* Hardwired 0xa0 (>= ICH5). */
+#include "i82801gx.h"
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
@@ -31,20 +31,20 @@ void set_debug_port(unsigned int port)
        /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
 }
 
-static void i82801gx_enable_usbdebug(unsigned int port)
+void i82801gx_enable_usbdebug(unsigned int port)
 {
        u32 dbgctl;
        device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
 
        /* Set the EHCI BAR address. */
-       pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+       pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
        /* Enable access to the EHCI memory space registers. */
        pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
        /* Force ownership of the Debug Port to the EHCI controller. */
        printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
-       dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
+       dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
        dbgctl |= (1 << 30);
-       write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
+       write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
 }

diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index f0cfae718311bf627206eab1ab6e18624d9fc3ed..d4a86507088a3b2abb4b660df15dd5ca79b8ac42 100644 (file)
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -8,3 +8,11 @@ config ID_SECTION_OFFSET
        hex
        default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
 
+config EHCI_BAR
+       hex
+       default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804
+
+config EHCI_DEBUG_OFFSET
+       hex
+       default 0x98 if SOUTHBRIDGE_NVIDIA_CK804
+

diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index bceec85737a3ef3983768eb3abfc35172959a52c..48f7713a8b3870573d579c5c12850d3518c5bf21 100644 (file)
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -15,5 +15,8 @@ ramstage-y += ck804_reset.c
 
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c
 
+romstage-y += ck804_enable_usbdebug.c
+
 chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds
+

diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index fb1b8d80a036f1dd27367fd7fc2cbf10deed6cba..7285d18d0e3a8617bc16b4ce94f3567de0f5a15a 100644 (file)
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -4,5 +4,6 @@
 #include "chip.h"
 
 void ck804_enable(device_t dev);
+void ck804_enable_usbdebug(unsigned int port);
 
 #endif

diff --git a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c b/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
index f82196329e37c4c120454fa969d832e648f50b2a..3cccded343433b3b72017337254499a33b423e6b 100644 (file)
--- a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
@@ -22,8 +22,11 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "ck804.h"
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -31,10 +34,6 @@
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#define EHCI_BAR               0xFEF00000      /* EHCI BAR address */
-#define EHCI_BAR_INDEX         0x10
-#define EHCI_DEBUG_OFFSET      0x98
-
 void set_debug_port(unsigned int port)
 {
        u32 dword;
@@ -47,7 +46,7 @@ void set_debug_port(unsigned int port)
        pci_write_config32(dev, 0x74, dword);
 }
 
-static void ck804_enable_usbdebug(unsigned int port)
+void ck804_enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 
@@ -55,7 +54,7 @@ static void ck804_enable_usbdebug(unsigned int port)
        set_debug_port(port);
 
        /* Set the EHCI BAR address. */
-       pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+       pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
        /* Enable access to the EHCI memory space registers. */
        pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 213b1755f9134ae69bd8c2633d2986501bd075da..6084b1ea449d8a0ba38fae87b31e1327a270d372 100644 (file)
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -6,3 +6,12 @@ config SOUTHBRIDGE_NVIDIA_MCP55
 config ID_SECTION_OFFSET
        hex
        default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
+
+config EHCI_BAR
+       hex
+       default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55
+
+config EHCI_DEBUG_OFFSET
+       hex
+       default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
+

diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index 4388ca8e9a98ffb22ac642e5215c834cb932bcb9..a9dcf7f40f5fceee615fa9d088677b5d26bb9ad3 100644 (file)
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -15,5 +15,7 @@ driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.c
 
 ramstage-y += mcp55_reset.c
 
+romstage-y += mcp55_enable_usbdebug.c
+
 chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds

diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 687232f302d642acadfef5f14169c005e6387bc3..acb291a1d0c21f2ec8877a810156f6ec31587db6 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -29,4 +29,5 @@ void mcp55_enable(device_t dev);
 #else
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
 #endif
+void mcp55_enable_usbdebug(unsigned int port);
 #endif /* MCP55_H */

diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
index f1f5c2ab1121f633986720530104f89fe2f1ca64..e0b293c81a867066d91fdcf8b8f6efefe0a1fcd0 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
@@ -22,8 +22,11 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "mcp55.h"
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -31,10 +34,6 @@
 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#define EHCI_BAR               0xFEF00000      /* EHCI BAR address */
-#define EHCI_BAR_INDEX         0x10
-#define EHCI_DEBUG_OFFSET      0x98
-
 void set_debug_port(unsigned int port)
 {
        u32 dword;
@@ -47,7 +46,7 @@ void set_debug_port(unsigned int port)
        pci_write_config32(dev, 0x74, dword);
 }
 
-static void mcp55_enable_usbdebug(unsigned int port)
+void mcp55_enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
 
@@ -55,7 +54,7 @@ static void mcp55_enable_usbdebug(unsigned int port)
        set_debug_port(port);
 
        /* Set the EHCI BAR address. */
-       pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+       pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
        /* Enable access to the EHCI memory space registers. */
        pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index f84f1506fba2a699552445ef45bafa7cd235667b..bbb5ee971b394f43e4ddf5b804d469b5e4df56d3 100644 (file)
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -6,3 +6,11 @@ config SOUTHBRIDGE_SIS_SIS966
 config ID_SECTION_OFFSET
        hex
        default 0x80 if SOUTHBRIDGE_SIS_SIS966
+
+config EHCI_BAR
+       hex
+       default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+
+config EHCI_DEBUG_OFFSET
+       hex
+       default 0x98 if SOUTHBRIDGE_SIS_SIS966

diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index c3f000c769b49e022e5c916d0006bc78d5f4e120..e51c81fa83a7f76e6c3c3e22bb4b294ee1249fed 100644 (file)
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -9,6 +9,7 @@ driver-y += sis966_sata.c
 driver-y += sis966_pcie.c
 driver-y += sis966_aza.c
 ramstage-y += sis966_reset.c
+romstage-y += sis966_enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds

diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index ee04a65878e244da0baa64add1b6d2a38a59b989..324beef3c9e0f51dc5b06de1c4c1a3697decae76 100644 (file)
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -32,5 +32,6 @@
 #include "chip.h"
 
 void sis966_enable(device_t dev);
+void sis966_enable_usbdebug(unsigned int port);
 
 #endif /* SIS966_H */

diff --git a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c b/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
index 64aa7be27741dffaeab84f4daf924134b2e001e0..a82e941b3a3fbe13e936d891514eb321cbf7ef6f 100644 (file)
--- a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
@@ -24,8 +24,11 @@
 /* TODO: Check whether this actually works (might be copy-paste leftover). */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "sis966.h"
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -33,10 +36,6 @@
 #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#define EHCI_BAR               0xFEF00000      /* EHCI BAR address */
-#define EHCI_BAR_INDEX         0x10
-#define EHCI_DEBUG_OFFSET      0x98
-
 void set_debug_port(unsigned int port)
 {
        u32 dword;
@@ -49,7 +48,7 @@ void set_debug_port(unsigned int port)
        pci_write_config32(dev, 0x74, dword);
 }
 
-static void sis966_enable_usbdebug(unsigned int port)
+void sis966_enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
 
@@ -57,7 +56,7 @@ static void sis966_enable_usbdebug(unsigned int port)
        set_debug_port(port);
 
        /* Set the EHCI BAR address. */
-       pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+       pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
        /* Enable access to the EHCI memory space registers. */
        pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);