2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/stack.h>
22 #include <cpu/x86/mtrr.h>
23 #include <cpu/x86/post_code.h>
25 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
26 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
28 /* Save the BIST result. */
34 /* Send INIT IPI to all excluding ourself. */
35 movl $0x000C4500, %eax
36 movl $0xFEE00300, %esi
39 /* Zero out all fixed range and variable range MTRRs. */
40 movl $mtrr_table, %esi
41 movl $((mtrr_table_end - mtrr_table) / 2), %edi
52 /* Configure the default memory type to uncacheable. */
53 movl $MTRRdefType_MSR, %ecx
55 andl $(~0x00000cff), %eax
58 /* Set Cache-as-RAM base address. */
59 movl $(MTRRphysBase_MSR(0)), %ecx
60 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
64 /* Set Cache-as-RAM mask. */
65 movl $(MTRRphysMask_MSR(0)), %ecx
66 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
67 movl $0x0000000f, %edx
71 movl $MTRRdefType_MSR, %ecx
73 orl $MTRRdefTypeEn, %eax
76 /* Enable L2 cache. */
82 /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
84 andl $(~((1 << 30) | (1 << 29))), %eax
88 /* Clear the cache memory reagion. */
89 movl $CACHE_AS_RAM_BASE, %esi
91 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
92 // movl $0x23322332, %eax
96 /* Enable Cache-as-RAM mode by disabling cache. */
101 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
102 /* Enable cache for our code in Flash because we do XIP here */
103 movl $MTRRphysBase_MSR(1), %ecx
105 #if CONFIG_TINY_BOOTBLOCK
106 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
108 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
111 * IMPORTANT: The two lines below can _not_ be written like this:
112 * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
113 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
115 movl $REAL_XIP_ROM_BASE, %eax
116 orl $MTRR_TYPE_WRBACK, %eax
119 movl $MTRRphysMask_MSR(1), %ecx
120 movl $0x0000000f, %edx
121 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
123 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
127 andl $(~((1 << 30) | (1 << 29))), %eax
130 /* Set up the stack pointer. */
132 /* Leave some space for the struct ehci_debug_info. */
133 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
135 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
139 /* Restore the BIST result. */
146 /* Call romstage.c main function. */
161 movl $MTRRdefType_MSR, %ecx
163 andl $(~MTRRdefTypeEn), %eax
172 movl $MTRRphysBase_MSR(0), %ecx
174 movl $MTRRphysMask_MSR(0), %ecx
176 movl $MTRRphysBase_MSR(1), %ecx
178 movl $MTRRphysMask_MSR(1), %ecx
186 andl $~((1 << 30) | (1 << 29)), %eax
198 /* Enable Write Back and Speculative Reads for the first 1MB. */
199 movl $MTRRphysBase_MSR(0), %ecx
200 movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
203 movl $MTRRphysMask_MSR(0), %ecx
204 movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
205 movl $0x0000000f, %edx // 36bit address space
210 /* And enable cache again after setting MTRRs. */
212 andl $~((1 << 30) | (1 << 29)), %eax
218 movl $MTRRdefType_MSR, %ecx
220 orl $MTRRdefTypeEn, %eax
225 /* Invalidate the cache again. */
230 /* Clear boot_complete flag. */
233 post_code(POST_PREPARE_RAMSTAGE)
234 cld /* Clear direction flag. */
238 movl $ROMSTAGE_STACK, %esp
244 post_code(POST_DEAD_CODE)
250 .word 0x250, 0x258, 0x259
251 .word 0x268, 0x269, 0x26A
252 .word 0x26B, 0x26C, 0x26D
255 .word 0x200, 0x201, 0x202, 0x203
256 .word 0x204, 0x205, 0x206, 0x207
257 .word 0x208, 0x209, 0x20A, 0x20B
258 .word 0x20C, 0x20D, 0x20E, 0x20F