Add AMD C32 support.

It is based on other existing Fam10 code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index 8af95b334f6034f3bc63f38bffe9575adf2ce8e6..0e2683401ce1cbb139adcaa840e9ca03063a5788 100644 (file)
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -8,6 +8,7 @@ source src/cpu/amd/socket_940/Kconfig
 source src/cpu/amd/socket_AM2/Kconfig
 source src/cpu/amd/socket_AM2r2/Kconfig
 source src/cpu/amd/socket_AM3/Kconfig
+source src/cpu/amd/socket_C32/Kconfig
 source src/cpu/amd/socket_ASB2/Kconfig
 source src/cpu/amd/socket_F/Kconfig
 source src/cpu/amd/socket_F_1207/Kconfig

diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index 1734da4b8e5ffa0a7d014d287e19aa3951809276..031e921a2b4e2d56327c5eb0bd2b5a37bbcfd48f 100644 (file)
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -7,6 +7,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
+subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32
 subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1
 subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2
 subdirs-$(CONFIG_CPU_AMD_LX) += model_lx

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index b00ae487cc1c627acd3b3d16cb4a8de1d67ac072..90b83e5bf9c372f2754afad55f436e40b0b64a1a 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -89,9 +89,25 @@ static const struct {
          0x00000000, 1 << (33-32),
          0x00000000, 1 << (33-32) },   /* [ExtendedFeatEn]=1 */
 
-        { BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL,
+       { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
          0x00000000, 1 << (35-32),
          0x00000000, 1 << (35-32) },   /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */  
+
+       { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
+         0x00000004, 0x00000000,
+         0x00000004, 0x00000000},      /* B0 or Above, OSVW_ID_Length is 0004h */
+
+       { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
+         0x0000000C, 0x00000000,
+         0x0000000C, 0x00000000},      /* Cx and Dx multiple-link processor */
+
+       { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL,
+         0x00000000, 1 << (50-32),
+         0x00000000, 1 << (50-32)},    /* D0 or Above, RdMmExtCfgQwEn*/
+
+       { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
+         0x00000000, 1 << (51 - 32),
+         0x00000000, 1 << (51 - 32)},  /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
 };
 
 
@@ -140,28 +156,28 @@ static const struct {
         * program Link Global Extended Control Register[ForceFullT0]
         * (F0x16C[15:13]) to 000b */
 
-       { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */
+       { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
          0x00000000, 0x00000100 },
-       { 0, 0x174,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x178,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x17C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x180,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x184,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x188,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x18C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x170,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+       { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
 
        /* Link Global Extended Control Register */
-       { 0, 0x16C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
-         0x00000014, 0x0000E03F },     /* [15:13] ForceFullT0 = 0b,
+       { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000014, 0x0000003F },     /* [15:13] ForceFullT0 = 0b,
                                                                 * Set T0Time 14h per BKDG */
 
 
@@ -297,7 +313,7 @@ static const struct {
                                           [5] DisPciCfgCpuMstAbtRsp = 1,
                                           [1] SyncFloodOnUsPwDataErr = 1 */
 
-       /* errata 346 - Fam10 C2 -- FIXME at 25.6.2010 should apply to BL-C[23] too but I can't find their constants
+       /* errata 346 - Fam10 C2, C3
         *  System software should set F3x188[22] to 1b. */
        { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
          0x00400000, 0x00400000 },
@@ -324,100 +340,100 @@ static const struct {
        u32 mask;
 } fam10_htphy_default[] = {
 
-       /* Errata 344 - Fam10 C2/D0 -- FIXME at 25.6.2010 should be for ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them
+       /* Errata 344 - Fam10 C2/C3, D0/D1
         * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
-       { 0x60,   AMD_DRBH_Cx , AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       { 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       /* Errata 354 - Fam10 C2 - FIXME at 25.6.2010 affects RB-C2, BL-C2,DA-C2,RB-C3,BL-C3,DA-C3, but BL-C[23] have no constants
+       /* Errata 354 - Fam10 C2, C3
         * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
-       { 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       { 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       /* Errata 327 - Fam10 C2/D0
+       /* Errata 327 - Fam10 C2/C3, D0/D1
         * BIOS should set the Link Phy Impedance Register[RttCtl]
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
         * Link Phy Impedance Register[RttIndex]
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
-       { 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
-       { 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
 
-       { 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
-       { 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
        { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,

diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000c4.h b/src/cpu/amd/model_10xxx/mc_patch_010000c4.h
new file mode 100644 (file)
index 0000000..ce0578b
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_010000c4.h
@@ -0,0 +1,186 @@
+/*
+ ******************************************************************************
+ *
+ * Copyright 2010 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+0x10, 0x20, 0x03, 0x03, 0xc4, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x01,
+0x4a, 0xe0, 0x9c, 0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x81, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xa7, 0x0b, 0x00, 0x00,
+0x14, 0x0c, 0x00, 0x00, 0x55, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+0x51, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0x4f, 0xdf, 0x38, 0x00, 0x81, 0x3f, 0x20, 0xc0,
+0x4e, 0xf0, 0xff, 0xbf, 0x0f, 0xff, 0x5e, 0x3f, 0xf0, 0xdf, 0xad, 0x07,
+0x3d, 0xf8, 0x7b, 0x7b, 0xc0, 0x00, 0xd4, 0x00, 0x13, 0xf1, 0xff, 0xff,
+0xac, 0xe1, 0x1f, 0xe0, 0x4e, 0xfe, 0xbb, 0xff, 0xfe, 0x87, 0x7f, 0xa7,
+0x03, 0xf8, 0x7f, 0xd6, 0x7c, 0x1e, 0xfa, 0xbd, 0x00, 0xe0, 0xff, 0x7b,
+0x0e, 0x00, 0x3d, 0x57, 0xe0, 0x73, 0xd0, 0x0f, 0xff, 0x2e, 0xfe, 0xff,
+0xc0, 0xcf, 0xc3, 0x3f, 0xeb, 0x01, 0xfc, 0x77, 0x5a, 0x3e, 0x0f, 0xfd,
+0x35, 0x00, 0x90, 0x3e, 0xff, 0x9f, 0xe0, 0xfd, 0x65, 0x60, 0x75, 0xf8,
+0x9f, 0xff, 0x97, 0xff, 0x1f, 0xe0, 0xe7, 0xe1, 0x03, 0xf5, 0xde, 0xff,
+0x7e, 0x2c, 0x9f, 0x87, 0xff, 0x1e, 0x00, 0xf8, 0x6f, 0x95, 0x03, 0x50,
+0xf4, 0x03, 0xf8, 0x1c, 0xf8, 0xff, 0x3f, 0x00, 0xf0, 0xee, 0x84, 0xfc,
+0xfe, 0xff, 0xff, 0x22, 0xc3, 0x1f, 0x51, 0x96, 0x38, 0x16, 0x0d, 0x00,
+0xf8, 0xfe, 0xfe, 0x01, 0x0e, 0xfc, 0xb1, 0x01, 0xe5, 0xa6, 0xff, 0x1f,
+0x79, 0xf8, 0x07, 0xf8, 0x80, 0xff, 0xc0, 0x3f, 0xbf, 0xe1, 0x1f, 0xc0,
+0x00, 0xfa, 0xbf, 0x07, 0x01, 0xfc, 0x3f, 0xe3, 0x3e, 0x0f, 0xfd, 0x50,
+0x03, 0xb0, 0xdf, 0x8c, 0xf9, 0x3c, 0xf4, 0x43, 0x0e, 0xc0, 0xfd, 0x32,
+0xe5, 0xf3, 0xd0, 0x0f, 0x03, 0x00, 0x03, 0x25, 0xff, 0x00, 0xfe, 0x03,
+0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe,
+0xf0, 0x0f, 0xe0, 0x3f, 0x07, 0xf0, 0x6f, 0xf8, 0xef, 0x01, 0x80, 0xff,
+0xff, 0xff, 0x00, 0xfd, 0xbb, 0x14, 0xf2, 0xc3, 0x2f, 0xf8, 0x13, 0xcc,
+0x7f, 0x0c, 0xb8, 0x0e, 0x74, 0xf5, 0x03, 0xf0, 0xf8, 0x33, 0x03, 0x1c,
+0x2b, 0xd7, 0x00, 0x00, 0xeb, 0xe5, 0x1f, 0x80, 0xc0, 0x1f, 0x1b, 0xe0,
+0x9e, 0x9b, 0x7f, 0x00, 0x03, 0x7f, 0x6c, 0x80, 0xf8, 0x7d, 0xfe, 0x01,
+0x0e, 0xfc, 0xb1, 0x01, 0x80, 0xd7, 0x62, 0x00, 0xc0, 0x7f, 0xe0, 0x1f,
+0xdf, 0xf0, 0x0f, 0xe0, 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
+0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, 0x00, 0xf0, 0xff, 0x3d,
+0x0f, 0xe0, 0x3f, 0xf0, 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
+0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
+0x1e, 0x00, 0xf8, 0xff, 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
+0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
+0x3f, 0x80, 0x7f, 0xc3, 0x7f, 0x0f, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8,
+0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
+0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0xbf, 0x07, 0x00,
+0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
+0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
+0x00, 0xff, 0xdf, 0x03, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
+0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
+0xf0, 0x6f, 0xf8, 0x07, 0x01, 0x80, 0xff, 0xef, 0x38, 0x00, 0x43, 0xdf,
+0xa0, 0xd7, 0x83, 0x3f, 0xe3, 0x00, 0x3c, 0x75, 0x80, 0x5e, 0x07, 0xfe,
+0xff, 0xef, 0x7a, 0xc1, 0x73, 0xfd, 0x3c, 0xfc, 0xf7, 0x00, 0xc0, 0xff,
+0xff, 0xff, 0x17, 0xff, 0xdf, 0xeb, 0xff, 0xe1, 0xb7, 0xf5, 0x00, 0xfe,
+0x7f, 0x6e, 0x80, 0x07, 0xff, 0xff, 0x6f, 0x11, 0xfe, 0xb5, 0xaa, 0x1f,
+0xff, 0x7b, 0x00, 0xe0, 0xff, 0xff, 0x7f, 0x8b, 0xf0, 0xaf, 0x75, 0xff,
+0xff, 0xdb, 0x7f, 0x2f, 0xc3, 0xbf, 0x57, 0xf5, 0x0c, 0xf1, 0xff, 0xb7,
+0x0f, 0xff, 0x00, 0x3f, 0x70, 0xa2, 0x35, 0x00, 0xe0, 0xff, 0x1b, 0x0f,
+0x79, 0xe8, 0xd7, 0xf2, 0x80, 0xff, 0xc0, 0x3f, 0xbf, 0xe1, 0x1f, 0xc0,
+0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0x1e,
+0x2f, 0x3a, 0xc1, 0xff, 0xfd, 0x3c, 0xfc, 0x6b, 0x1e, 0xc0, 0x7f, 0xb6,
+0x0c, 0xf0, 0xe0, 0x4f, 0xff, 0x2f, 0x43, 0xfc, 0xc0, 0xcf, 0xc3, 0x3f,
+0x0f, 0x00, 0xfc, 0x7f, 0xff, 0x67, 0x81, 0xff, 0xb1, 0xee, 0x1f, 0xfe,
+0x1b, 0x0f, 0xe0, 0xff, 0xf7, 0xf6, 0x7a, 0xf0, 0xef, 0xbf, 0x96, 0xff,
+0x1d, 0xab, 0xfe, 0xe1, 0xbf, 0x07, 0x00, 0xfe, 0x6f, 0xff, 0xb1, 0xfc,
+0x7f, 0x58, 0x59, 0x0e, 0xc0, 0xff, 0x2f, 0x72, 0xfc, 0x03, 0xfc, 0x3c,
+0x7f, 0x31, 0x1e, 0xc0, 0xe0, 0x4f, 0xec, 0x75, 0xff, 0xdf, 0x03, 0x00,
+0xd7, 0xf8, 0xff, 0x45, 0x87, 0x7f, 0xa2, 0x9f, 0x19, 0xff, 0xff, 0x67,
+0x1f, 0xfe, 0xb1, 0xae, 0x65, 0xfc, 0xff, 0xff, 0x7e, 0xf8, 0xf7, 0xba,
+0x80, 0xff, 0xef, 0x01, 0x00, 0xff, 0xdb, 0x7a, 0xc0, 0x83, 0x3f, 0x31,
+0x01, 0xfc, 0x67, 0xff, 0xf4, 0x0f, 0xdf, 0x5a, 0x4f, 0xf0, 0xff, 0xff,
+0xd8, 0x3a, 0xfc, 0x32, 0x00, 0xc0, 0x01, 0x48, 0x7f, 0x97, 0xf1, 0xff,
+0xe0, 0xac, 0xe1, 0x1f, 0xff, 0x5a, 0xfe, 0xbb, 0xad, 0xff, 0x87, 0x7f,
+0xfe, 0x03, 0xf8, 0xff, 0xb5, 0xe8, 0x1f, 0xbe, 0x7b, 0x00, 0xe0, 0xff,
+0xe0, 0x5f, 0xcb, 0x7f, 0xab, 0x75, 0xe5, 0xf0, 0xdb, 0x7a, 0x00, 0xff,
+0x3f, 0x91, 0xcf, 0x43, 0x0f, 0xf8, 0x13, 0x90, 0xbf, 0x0c, 0xb6, 0x0e,
+0xff, 0x3d, 0x00, 0xf0, 0x7f, 0x5b, 0x0f, 0xe0, 0xf0, 0x27, 0x06, 0x78,
+0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x5b, 0x8b, 0xfe, 0xca, 0x07, 0xfc, 0x09,
+0x87, 0x5f, 0x06, 0x5b, 0x20, 0x00, 0x09, 0x00, 0xb0, 0xc0, 0x8d, 0x03,
+0x3c, 0xf8, 0x03, 0x02, 0x80, 0xf8, 0xff, 0x3f, 0xfc, 0xf0, 0xce, 0x85,
+0x04, 0x3a, 0x0e, 0xfe, 0xae, 0xc3, 0x1f, 0x03, 0x00, 0xfc, 0x7f, 0x0f,
+0x77, 0x01, 0x00, 0xf8, 0xee, 0x1f, 0xfe, 0xb9, 0x3f, 0x65, 0x40, 0xe0,
+0xf8, 0x79, 0xf8, 0x07, 0xff, 0x94, 0xf3, 0xff, 0xea, 0xfa, 0xe0, 0x5f,
+0x06, 0x00, 0x7a, 0xbc, 0xff, 0xa5, 0xfe, 0x77, 0x52, 0x3f, 0x0f, 0xff,
+0xff, 0xef, 0xf2, 0xfe, 0x03, 0xfc, 0x3c, 0xfc, 0x77, 0x1f, 0xe0, 0x7f,
+0x2f, 0xe5, 0xf3, 0xd0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
+0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
+0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 9cd6d66e4abf3232241e1a1b9d033054ec2864b2..a92852f521322766be3684a69a35646f91f4ec8d 100644 (file)
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -145,6 +145,7 @@ static struct cpu_device_id cpu_table[] = {
        { X86_VENDOR_AMD, 0x100F62 },           /* DA-C2 */
        { X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
        { X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
+       { X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
        { 0, 0 },
 };
 

diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c
index 3f712e37b46e36f3b2d3f34f8c631edd072cf3eb..62040d9a5194d8a2d3caed0f591ee560e9d22c4f 100644 (file)
--- a/src/cpu/amd/model_10xxx/processor_name.c
+++ b/src/cpu/amd/model_10xxx/processor_name.c
@@ -154,6 +154,25 @@ static const struct str_s String2_socket_AM2[] = {
        {0, 0, 0, NULL}
 };
 
+static const struct str_s String1_socket_C32[] = {
+       {0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"},
+       {0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"},
+       {0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "},
+       {0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "},
+       {0, 0, 0, NULL}
+};
+
+static const struct str_s String2_socket_C32[] = {
+       {0x00, 0x03, 0x00, " HE"},
+       {0x00, 0x03, 0x01, " EE"},
+       {0x00, 0x05, 0x00, " HE"},
+       {0x00, 0x05, 0x01, " EE"},
+       {0x01, 0x03, 0x01, "QS HE"},
+       {0x01, 0x03, 0x02, "LE HE"},
+       {0x01, 0x05, 0x01, "KX HE"},
+       {0x01, 0x05, 0x02, "GL EE"},
+       {0, 0, 0, NULL}
+};
 
 const char const *unknown = "AMD Processor model unknown";
 const char const *unknown2 = " type unknown";
@@ -218,6 +237,10 @@ int init_processor_name(void)
                str = String1_socket_AM2;
                str2 = String2_socket_AM2;
                break;
+       case 5:         /* C32 */
+               str = String1_socket_C32;
+               str2 = String2_socket_C32;
+               break;
        default:
                goto done;
        }

diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index 11c710a3eab78f98a5e8a3f4b8564f42eb535e9b..fa3b4f8a72b38fe95d4aa0c683d3d4844cef837b 100644 (file)
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -50,6 +50,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
  * 00100F43h (RB-C3)     1043h                  010000b6h
  * 00100F62h (DA-C2)     1062h                  0100009Fh
  * 00100F63h (DA-C3)     1043h                  010000b6h
+ * 00100F81h (HY-D1)     1081h                  010000c4h
  */
 
 #include CONFIG_AMD_UCODE_PATCH_FILE
@@ -76,6 +77,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
                0x100f43, 0x1043,
                0x100f62, 0x1062,
                0x100f63, 0x1043,
+               0x100f81, 0x1081,
        };
 
        u32 new_id;

diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
new file mode 100644 (file)
index 0000000..7ffa374
--- /dev/null
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -0,0 +1,42 @@
+config CPU_AMD_SOCKET_C32
+       bool
+       select CPU_AMD_MODEL_10XXX
+       select HT3_SUPPORT
+       select PCI_IO_CFG_EXT
+       select CACHE_AS_RAM
+
+config CPU_SOCKET_TYPE
+       hex
+       default 0x14
+       depends on CPU_AMD_SOCKET_C32
+
+config EXT_RT_TBL_SUPPORT
+       bool
+       default n
+       depends on CPU_AMD_SOCKET_C32
+
+config EXT_CONF_SUPPORT
+       bool
+       default n
+       depends on CPU_AMD_SOCKET_C32
+
+config CBB
+       hex
+       default 0x0
+       depends on CPU_AMD_SOCKET_C32
+
+config CDB
+       hex
+       default 0x18
+       depends on CPU_AMD_SOCKET_C32
+
+config XIP_ROM_BASE
+       hex
+       default 0xfff80000
+       depends on CPU_AMD_SOCKET_C32
+
+config XIP_ROM_SIZE
+       hex
+       default 0x80000
+       depends on CPU_AMD_SOCKET_C32
+

diff --git a/src/cpu/amd/socket_C32/Makefile.inc b/src/cpu/amd/socket_C32/Makefile.inc
new file mode 100644 (file)
index 0000000..8ce43fb
--- /dev/null
+++ b/src/cpu/amd/socket_C32/Makefile.inc
@@ -0,0 +1,14 @@
+ramstage-y += socket_C32.c
+subdirs-y += ../model_10xxx
+subdirs-y += ../quadcore
+subdirs-y += ../mtrr
+subdirs-y += ../microcode
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/pae
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/smm
+subdirs-y += ../smm
+
+cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc

diff --git a/src/cpu/amd/socket_C32/chip.h b/src/cpu/amd/socket_C32/chip.h
new file mode 100644 (file)
index 0000000..0e06de5
--- /dev/null
+++ b/src/cpu/amd/socket_C32/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_amd_socket_C32_ops;
+
+struct cpu_amd_socket_C32_config {
+};

diff --git a/src/cpu/amd/socket_C32/socket_C32.c b/src/cpu/amd/socket_C32/socket_C32.c
new file mode 100644 (file)
index 0000000..266bfa0
--- /dev/null
+++ b/src/cpu/amd/socket_C32/socket_C32.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_amd_socket_C32_ops = {
+       CHIP_NAME("socket C32")
+};

diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 352d90acf1c375eb7b9658564596acaa39967635..0c01cf1a2ec5360b99e8c42592b342c19becab4e 100644 (file)
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -78,6 +78,9 @@ static  void print_t(const char *strval)
 #elif CONFIG_CPU_SOCKET_TYPE == 0x13
 //ASB2
 #include "../amdmct/mct_ddr3/mctardk5.c"
+//C32
+#elif CONFIG_CPU_SOCKET_TYPE == 0x14
+#include "../amdmct/mct_ddr3/mctardk5.c"
 #endif
 
 #else  /* DDR2 */
@@ -205,6 +208,9 @@ u32 mctGetLogicalCPUID(u32 Node)
        case 0x10080:
                ret = AMD_HY_D0;
                break;
+       case 0x10081:
+               ret = AMD_HY_D1;
+               break;
        default:
                /* FIXME: mabe we should die() here. */
                print_err("FIXME! CPU Version unknown or not supported! \n");

diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 92490975fff2627179b251193df7c29d0302e135..78526681b9098628732187ca6e9b05c09fe84610 100644 (file)
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -45,6 +45,7 @@
 #define        AMD_HY_D0       0x04000000      /* Istanbul D0 */
 #define        AMD_RB_C3       0x08000000      /* ??? C3 */
 #define        AMD_DA_C3       0x10000000      /* XXXX C3 */
+#define        AMD_HY_D1       0x20000000      /* Istanbul D1 */
 
 /*
  * Groups - Create as many as you wish, from the above public values
@@ -61,19 +62,18 @@
 #define        AMD_DR_LT_B2    (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
 #define        AMD_DR_LT_B3    (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
 #define        AMD_DR_GT_B0    (AMD_DR_ALL & ~(AMD_DR_B0))
+#define        AMD_DR_GT_Bx    (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
 #define        AMD_DR_ALL      (AMD_DR_Bx)
-#define        AMD_FAM10_ALL   (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
+#define        AMD_FAM10_ALL   (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1)
 #define AMD_FAM10_LT_D  (AMD_FAM10_ALL & ~(AMD_HY_D0))
 #define        AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define        AMD_DA_Cx       (AMD_DA_C2 | AMD_DA_C3)
 #define        AMD_DR_Cx       (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)
 #define        AMD_FAM10_C3       (AMD_RB_C3 | AMD_DA_C3)
-#define        AMD_DR_Dx       (AMD_HY_D0)
-#define        AMD_DRBH_Cx       (AMD_DR_Cx | AMD_HY_D0 )
-#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
-
-#define        AMD_DR_GT_Bx    (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
-#define        AMD_DR_DAC2_OR_C3       (AMD_DA_C2 | AMD_DA_C3)
+#define        AMD_DR_Dx       (AMD_HY_D0 | AMD_HY_D1)
+#define        AMD_DRBH_Cx     (AMD_DR_Cx | AMD_HY_D0 )
+#define        AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
+#define        AMD_DR_DAC2_OR_C3       (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3)
 
 /*
  *  Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 68d16afbf3c3f0fe5539806659711eedae70b276..5abe6d04ddb1a42440f50ee4d776b34355eab1ba 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -2407,7 +2407,7 @@ static void mct_DramInit(struct MCTStatStruc *pMCTstat,
        // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
 
        /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */
-       if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+       if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) {
                if (pDCTstat->GangedMode) {
                        val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
                        val |= 1 << DisAutoRefresh;
@@ -2421,7 +2421,7 @@ static void mct_DramInit(struct MCTStatStruc *pMCTstat,
         * to ensure both DCTs are in sync (Erratum 278)
         */
 
-       if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+       if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) {
                if (pDCTstat->GangedMode) {
                        do {
                                val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));