config HAVE_HARD_RESET
bool
- default n
+ default 0
config HAVE_INIT_TIMER
bool
bool "TeleVideo"
config VENDOR_THOMSON
bool "Thomson"
-config VENDOR_TOTAL_IMPACT
- bool "Total Impact"
config VENDOR_TYAN
bool "Tyan"
config VENDOR_VIA
default "Thomson"
depends on VENDOR_THOMSON
-config MAINBOARD_VENDOR
- string
- default "Total Impact"
- depends on VENDOR_TOTAL_IMPACT
-
config MAINBOARD_VENDOR
string
default "Tyan"
source "src/mainboard/technologic/Kconfig"
source "src/mainboard/televideo/Kconfig"
source "src/mainboard/thomson/Kconfig"
-source "src/mainboard/totalimpact/Kconfig"
source "src/mainboard/tyan/Kconfig"
source "src/mainboard/via/Kconfig"
+++ /dev/null
-##
-## Config file for the Total Impact briQ
-##
-
-##
-## Early board initialization, called from ppc_main()
-##
-initobject init.o
-initobject clock.o
-
-##
-## Stage 2 timer support
-##
-object clock.o
-
-arch ppc end
-
-if CONFIG_BRIQ_750FX
-dir /cpu/ppc/ppc7xx
-end
-if CONFIG_BRIQ_7400
-dir /cpu/ppc/mpc74xx
-end
-
-##
-## Include the secondary Configuration files
-##
-chip northbridge/ibm/cpc710
- device pci_domain 0 on # 32bit pci bridge
- device pci 0.0 on
- chip southbridge/winbond/w83c553
- # FIXME The function numbers are ok but the device id is wrong here!
- device pci 0.0 on end # pci to isa bridge
- device pci 0.1 on end # pci ide controller
- end
- end
- end
- device cpu_bus 0 on
- # chip cpu/ppc/ppc7xx
- # device cpu 0 on end
- # end
- end
-end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
+++ /dev/null
-##
-## Config file for the Total Impact briQ
-##
-
-uses CONFIG_TTYS0_DIV
-uses CONFIG_CBFS
-uses CONFIG_ARCH_X86
-uses CONFIG_TTYS0_BASE
-uses CONFIG_BRIQ_750FX
-uses CONFIG_BRIQ_7400
-uses CONFIG_ISA_IO_BASE
-uses CONFIG_ISA_MEM_BASE
-uses CONFIG_PCIC0_CFGADDR
-uses CONFIG_PCIC0_CFGDATA
-uses CONFIG_IO_BASE
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_USE_INIT
-uses CONFIG_NO_POST
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_IDE_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_IDE_BOOT_DRIVE
-uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_RESET
-uses CONFIG_EXCEPTION_VECTORS
-uses CONFIG_ROMBASE
-uses CONFIG_ROMSTART
-uses CONFIG_RAMBASE
-uses CONFIG_RAMSTART
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_BRIQ_750FX
-uses CONFIG_BRIQ_7400
-uses CONFIG_SYS_CLK_FREQ
-
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-##
-## Set memory map
-##
-default CONFIG_ISA_IO_BASE=0x80000000
-default CONFIG_ISA_MEM_BASE=0xc0000000
-default CONFIG_PCIC0_CFGADDR=0xff5f8000
-default CONFIG_PCIC0_CFGDATA=0xff5f8010
-default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
-
-##
-## The briQ uses weird clocking, 4 = 115200
-##
-default CONFIG_TTYS0_DIV=4
-##
-## Set UART base address
-##
-default CONFIG_TTYS0_BASE=0x3f8
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc"
-default HOSTCC="gcc"
-## use a cross compiler
-#default CONFIG_CROSS_COMPILE="powerpc-eabi-"
-#default CONFIG_CROSS_COMPILE="ppc_74xx-"
-default CONFIG_ARCH_X86=0
-
-## Use stage 1 initialization code
-default CONFIG_USE_INIT=1
-
-## We don't use compressed image
-default CONFIG_COMPRESS=0
-
-## Turn off POST codes
-default CONFIG_NO_POST=1
-
-## Enable serial console
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Boot linux from IDE
-default CONFIG_IDE_PAYLOAD=1
-default CONFIG_IDE_BOOT_DRIVE=0
-default CONFIG_IDE_SWAB=1
-default CONFIG_IDE_OFFSET=0
-
-# ROM is 1Mb
-default CONFIG_ROM_SIZE=1048576
-default CONFIG_ROM_IMAGE_SIZE=128*1024
-
-# Set stack and heap sizes (stage 2)
-default CONFIG_STACK_SIZE=0x10000
-default CONFIG_HEAP_SIZE=0x10000
-
-##
-## System clock
-##
-default CONFIG_SYS_CLK_FREQ=33
-
-# Sandpoint Demo Board
-## Base of ROM
-default CONFIG_ROMBASE=0xfff00000
-
-## Sandpoint reset vector
-default CONFIG_RESET=CONFIG_ROMBASE+0x100
-
-## Exception vectors (other than reset vector)
-default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
-
-## Start of coreboot in the boot rom
-## = CONFIG_RESET + exeception vector table size
-default CONFIG_ROMSTART=CONFIG_RESET+0x3100
-
-## Coreboot C code runs at this location in RAM
-default CONFIG_RAMBASE=0x00100000
-default CONFIG_RAMSTART=0x00100000
-
-default CONFIG_BRIQ_750FX=1
-#default CONFIG_BRIQ_7400=1
-
-### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
-end
+++ /dev/null
-; bdiGDB configuration file for briQ (http://www.totalimpact.com)
-; ---------------------------------------------------------------
-;
-; NOTE: As of June 2004, you will need to install a pull-down
-; on the COP/JTAG QACK line. Without this, the BDI2000
-; is not able to halt the CPU
-; (http://www.ultsol.com/faq-P210.htm)
-;
-[INIT]
-; init core register
-WREG MSR 0x00000000 ;clear MSR
-;
-; init CPC710
-;
-WM32 0xFF000010 0xF0000000 ; RSTR
-WM32 0xFF001020 0x00000000 ; SIOC
-WM32 0xFF001000 0x00780000 ; UCTL (resID=7|TBE)
-WM32 0xFF001030 0x00000000 ; ABCNTL
-WM32 0xFF001040 0x00000000 ; SRST
-WM32 0xFF001050 0x00000000 ; ERRC
-WM32 0xFF001060 0x00000000 ; SESR
-WM32 0xFF001070 0x00000000 ; SEAR
-WM32 0xFF001100 0x000000E0 ; PGCHP (PReP|ARTRY|750|SYS_TEA)
-WM32 0xFF001130 0x40000000 ; GPDIR
-WM32 0xFF001150 0x40000000 ; GPOUT
-WM32 0xFF001160 0x709C2508 ; ATAS
-WM32 0xFF001170 0x00000000 ; AVDG
-WM32 0xFF001220 0x00000000 ; MESR
-WM32 0xFF001230 0x00000000 ; MEAR
-WM32 0xFF001210 0x00000000 ; MWPR
-WM32 0xFF001120 0x00000000 ; RGBAN1
-;
-; init memory - this assumes 2 x 512MB DIMMs
-;
-WM32 0xFF001300 0x80000080 ; MCER0
-WM32 0xFF001310 0x82000080 ; MCER1
-WM32 0xFF001320 0x00000000 ; MCER2
-WM32 0xFF001330 0x00000000 ; MCER3
-WM32 0xFF001340 0x00000000 ; MCER4
-WM32 0xFF001350 0x00000000 ; MCER5
-WM32 0xFF001200 0xD2B06000 ; MCCR
-DELAY 1000
-;
-; enable pci
-;
-WM32 0xFF00000C 0x80000002 ; CNFR
-WM32 0xFF200018 0xFF500000 ; PCIBAR
-WM32 0xFF201000 0x80000000 ; PCIENB
-WM32 0xFF00000C 0x00000000 ; CNFR
-;
-; config pci
-;
-WM32 0xFF5F8000 0x06000080
-WM16 0xFF5F8010 0xFFFF
-WM32 0xFF5F8000 0x40000080
-WM16 0xFF5F8010 0x0000
-WM32 0xFF5F6120 0x40000000 ; PCIDG
-WM32 0xFF5F7800 0x00000000 ; PIBAR
-WM32 0xFF5F7810 0x00000000 ; PMBAR
-WM32 0xFF5F7F20 0xA000C000 ; PR
-WM32 0xFF5F7F30 0xFC000000 ; ACR
-WM32 0xFF5F7F40 0xF8000000 ; MSIZE
-WM32 0xFF5F7F60 0xF8000000 ; IOSIZE
-WM32 0xFF5F7F80 0xC0000000 ; SMBAR
-WM32 0xFF5F7FC0 0x80000000 ; SIBAR
-WM32 0xFF5F8100 0x00000080 ; PSSIZE
-WM32 0xFF5F8120 0x00000000 ; BARPS
-WM32 0xFF5F8140 0x00000080 ; PSBAR
-WM32 0xFF5F8200 0x00000000 ; BPMDLK
-WM32 0xFF5F8210 0x00000000 ; TPMDLK
-WM32 0xFF5F8220 0x00000000 ; BIODLK
-WM32 0xFF5F8230 0x00000000 ; TIODLK
-WM32 0xFF5F8000 0x04000080
-WM16 0xFF5F8010 0xA7FD
-WM32 0xFF5F7EF0 0xFC000000 ; CRR
-;
-; VFD - output the sequence '01234' to show
-; something is happening
-;
-;WM8 0x80000390 0x38
-;WM8 0x80000390 0x01
-;WM8 0x80000390 0x0C
-;WM8 0x80000390 0x06
-;WM8 0x80000390 0x02
-;DELAY 100
-;WM8 0x80000391 0x30
-;DELAY 100
-;WM8 0x80000391 0x31
-;DELAY 100
-;WM8 0x80000391 0x32
-;DELAY 100
-;WM8 0x80000391 0x33
-;DELAY 100
-;WM8 0x80000391 0x34
-;
-; UART - output the sequence '01234' to show
-; something is happening
-;
-WM8 0x800003F9 0
-WM8 0x800003FA 1
-WM8 0x800003FB 0x83
-WM8 0x800003F8 4 ; 115200
-WM8 0x800003F9 0
-WM8 0x800003FB 0x3
-DELAY 100
-WM8 0x800003F8 0x30
-DELAY 100
-WM8 0x800003F8 0x31
-DELAY 100
-WM8 0x800003F8 0x32
-DELAY 100
-WM8 0x800003F8 0x33
-DELAY 100
-WM8 0x800003F8 0x34
-;
-; define maximal transfer size
-;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM)
-TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash)
-
-
-[TARGET]
-CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400)
-JTAGCLOCK 0 ;use 16 MHz JTAG clock
-WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush
-BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY)
-BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
-STEPMODE TRACE ;TRACE or HWBP, HWPB uses a hardware breakpoint
-;VECTOR CATCH ;catch unhandled exceptions
-DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH)
-;PARITY ON ;enable data parity generation
-;MEMDELAY 4000 ;additional memory access delay
-;REGLIST STD ;select register to transfer to GDB
-;L2PM 0x00100000 0x80000 ;L2 privat memory
-BOOTADDR 0xfff00100
-STARTUP RESET
-
-[HOST]
-FORMAT ELF
-LOAD MANUAL ;load code MANUAL or AUTO after reset
-DEBUGPORT 2001
-
-[FLASH]
-; Am29LV800BB on local processor bus (RCS0)
-; set PPMC7410 switch SW2-1 OFF => ROM on Local bus
-; enable flash write in PICR1 (see INIT part)
-; set maximal transfer size to 4 bytes (see INIT part)
-CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
-CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
-BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
-;WORKSPACE 0x00000000 ;workspace in SDRAM
-FILE coreboot.rom
-FORMAT ELF
-ERASE 0xFFF00000 ;erase sector 0 of flash
-ERASE 0xFFF10000 ;erase sector 1 of flash
-ERASE 0xFFF20000 ;erase sector 2 of flash
-ERASE 0xFFF30000 ;erase sector 3 of flash
-ERASE 0xFFF40000 ;erase sector 4 of flash
-ERASE 0xFFF50000 ;erase sector 5 of flash
-ERASE 0xFFF60000 ;erase sector 6 of flash
-ERASE 0xFFF70000 ;erase sector 7 of flash
-;ERASE 0xFFF80000 ;erase sector 8 of flash
-;ERASE 0xFFF90000 ;erase sector 9 of flash
-;ERASE 0xFFFA0000 ;erase sector 10 of flash
-;ERASE 0xFFFB0000 ;erase sector 11 of flash
-;ERASE 0xFFFC0000 ;erase sector 12 of flash
-;ERASE 0xFFFD0000 ;erase sector 13 of flash
-;ERASE 0xFFFE0000 ;erase sector 14 of flash
-;ERASE 0xFFFF0000 ;erase sector 15 of flash
-
-[REGS]
-;DMM1 0xFC000000 ;Embedded utility memory base address
-;IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0
-;IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1
-;IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2
-;IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3
-FILE cpc700.def
-
-
+++ /dev/null
-#include <stdint.h>
-#include "../../../northbridge/ibm/cpc710/cpc710.h"
-
-/*
- * Bus clock jumper settings on SIOR0 27:28
- */
-static uint32_t BusClockSpeed[] = {
- 66000000, /* 00 */
- 83000000, /* 01 */
- 100000000, /* 10 */
- 133000000 /* 11 */
-};
-
-/*
- * Timer frequency is 1/4 of the bus clock frequency.
- *
- * For the briQ, bits 27:28 of SIOR0 encode bus clock frequency.
- */
-unsigned long
-get_timer_freq(void)
-{
- uint32_t sior0 = getCPC710(CPC710_SDRAM0_SIOR0);
-
- return BusClockSpeed[(sior0 >> 3) & 0x2] / 4;
-}
-
-/*
- * Frequency of PCI bus.
- *
- * For the briQ, bit 29 of SIOR0 is 66MHz enable (active low).
- */
-unsigned long
-get_pci_bus_freq(void)
-{
- uint32_t sior0 = getCPC710(CPC710_SDRAM0_SIOR0);
-
- if (sior0 & 0x4 == 0x4)
- return 33000000;
-
- return 66000000;
-}
-
+++ /dev/null
-chip northbridge/ibm/cpc710
- device pci_domain 0 on # 32bit pci bridge
- device pci 0.0 on
- chip southbridge/winbond/w83c553
- # FIXME The function numbers are ok but the device id is wrong here!
- device pci 0.0 on end # pci to isa bridge
- device pci 0.1 on end # pci ide controller
- end
- end
- end
- device cpu_bus 0 on
- # chip cpu/ppc/ppc7xx
- # device cpu 0 on end
- # end
- end
-end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
+++ /dev/null
-/*
- * Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Do very early board initialization:
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <uart8250.h>
-
-void
-board_init(void)
-{
-}
-
-void
-board_init2(void)
-{
- /*
- * Enable UART
- */
- uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, CONFIG_TTYS0_LCS);
- printk_info("briQ initialized...\n");
-
-}
projects / coreboot.git / commitdiff