3 #include <cpu/x86/cache.h>
4 #include <cpu/x86/mtrr.h>
5 #include <cpu/amd/mtrr.h>
6 #include <cpu/x86/msr.h>
8 static void set_var_mtrr(
9 unsigned reg, unsigned base, unsigned size, unsigned type)
12 /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
13 /* FIXME: It only support 4G less range */
15 basem.lo = base | type;
17 wrmsr(MTRRphysBase_MSR(reg), basem);
18 maskm.lo = ~(size - 1) | MTRRphysMaskValid;
19 maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
20 wrmsr(MTRRphysMask_MSR(reg), maskm);
23 #if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
24 static void cache_lbmem(int type)
26 /* Enable caching for 0 - 1MB using variable mtrr */
28 set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type);
32 /* the fixed and variable MTTRs are power-up with random values,
33 * clear them to MTRR_TYPE_UNCACHEABLE for safty.
35 static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
38 * The cache is not enabled in cr0 nor in MTRRdefType_MSR
39 * entry32.inc ensures the cache is not enabled in cr0
42 const unsigned long *msr_addr;
44 /* Inialize all of the relevant msrs to 0 */
48 for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
52 #if defined(CONFIG_XIP_ROM_SIZE)
53 /* enable write through caching so we can do execute in place
56 set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
59 /* Set the default memory type and enable fixed and variable MTRRs
61 /* Enable Variable MTRRs */
64 wrmsr(MTRRdefType_MSR, msr);
68 static inline void early_mtrr_init(void)
70 static const unsigned long mtrr_msrs[] = {
77 0x200, 0x201, 0x202, 0x203,
78 0x204, 0x205, 0x206, 0x207,
79 0x208, 0x209, 0x20A, 0x20B,
80 0x20C, 0x20D, 0x20E, 0x20F,
81 /* NULL end of table */
85 do_early_mtrr_init(mtrr_msrs);
89 static inline int early_mtrr_init_detected(void)
92 /* See if MTRR's are enabled.
93 * a #RESET disables them while an #INIT
94 * preserves their state. This works
95 * on both Intel and AMD cpus, at least
96 * according to the documentation.
98 msr = rdmsr(MTRRdefType_MSR);
99 return msr.lo & MTRRdefTypeEn;
103 #endif /* EARLYMTRR_C */