Use symbolic names for some MTRR bits instead of numbers in CAR code

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 26cdec3fbe69c1f1951e549aa3dd0c39bff04fc7..424bd93e7c7c79f65427333d092a63cb65ac1498 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -77,7 +77,7 @@ cache_as_ram_setup:
        /* Check if cpu_init_detected. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(1 << 11), %eax
+       andl    $MTRRdefTypeEn, %eax
        movl    %eax, %ebx      /* We store the status. */
 
        jmp_if_k8(CAR_FAM10_out_post_errata)
@@ -306,7 +306,7 @@ clear_fixed_var_mtrr_out:
        jmp_if_k8(wbcache_post_fam10_setup)
        movl    $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
 wbcache_post_fam10_setup:
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 3949a567c8c0a65e8b8dae52092e5372249a79a5..fc4eb8ae7401ff1d74b6a043218be20497fbf68c 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -254,7 +254,7 @@ clear_fixed_var_mtrr_out:
 
        movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0x0000000f, %edx
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
@@ -354,7 +354,7 @@ lout:
         */
        movl    $MTRRdefType_MSR, %ecx
        xorl    %edx, %edx
-       movl    $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
+       movl    $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */
        wrmsr
 
        /* Enable cache. */

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index fc4947600f740b1063438f0c436f7892c30eea1f..0ee26fcdd2b897e10caae0f9466cbb7d887f6028 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -63,14 +63,14 @@ clear_mtrrs:
 
        /* Set Cache-as-RAM mask. */
        movl    $(MTRRphysMask_MSR(0)), %ecx
-       movl    $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+       movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx
        wrmsr
 
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        /* Enable L2 cache. */
@@ -118,7 +118,7 @@ clear_mtrrs:
 
        movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0x0000000f, %edx
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
@@ -160,7 +160,7 @@ clear_mtrrs:
        /* Disable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(~(1 << 11)), %eax
+       andl    $(~MTRRdefTypeEn), %eax
        wrmsr
 
        post_code(0x31)
@@ -201,7 +201,7 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+       movl    $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx       // 36bit address space
        wrmsr
 
@@ -217,7 +217,7 @@ clear_mtrrs:
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        post_code(0x3b)

diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index a1b82675fba1d874514d77f6f2f08d305fb6c54f..a7605cc6899e1afd4ea5fd581139a542697d38bb 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -70,14 +70,14 @@ clear_mtrrs:
 
        /* Set Cache-as-RAM mask. */
        movl    $(MTRRphysMask_MSR(0)), %ecx
-       movl    $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+       movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx
        wrmsr
 
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        /* Enable L2 cache. */
@@ -125,7 +125,7 @@ clear_mtrrs:
 
        movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0x0000000f, %edx
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
@@ -167,7 +167,7 @@ clear_mtrrs:
        /* Disable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(~(1 << 11)), %eax
+       andl    $(~MTRRdefTypeEn), %eax
        wrmsr
 
        post_code(0x31)
@@ -208,7 +208,7 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+       movl    $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx       // 36bit address space
        wrmsr
 
@@ -224,7 +224,7 @@ clear_mtrrs:
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        post_code(0x3b)