Intel cpus: improve CPU compatibility of new CAR

Most or many Xeons have no MSR 0x11e.

I have previously tested that a HT-enabled P4 (model f25) can
execute this but will not have cache-as-ram enabled. Should work
for non-HT P4.

Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/644
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index a6cbd6bac5bb0e33efe41d970f3f65d7a950745e..641a2f3304350707a6686b96c475df2f2b41f694 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -83,11 +83,40 @@ clear_mtrrs:
        orl     $MTRRdefTypeEn, %eax
        wrmsr
 
-       /* Enable L2 cache. */
+       /* Enable L2 cache Write-Back (WBINVD and FLUSH#).
+        *
+        * MSR is set when DisplayFamily_DisplayModel is one of:
+        * 06_0x, 06_17, 06_1C
+        *
+        * Description says this bit enables use of WBINVD and FLUSH#.
+        * Should this be set only after the system bus and/or memory
+        * controller can successfully handle write cycles?
+        */
+
+#define EAX_FAMILY(a)  (a << 8)        /* for family <= 0fH */
+#define EAX_MODEL(a)   (((a & 0xf0) << 12) | ((a & 0xf) << 4))
+
+       movl    $1, %eax
+       cpuid
+       movl    %eax, %ebx
+       andl    $EAX_FAMILY(0x0f), %eax
+       cmpl    $EAX_FAMILY(0x06), %eax
+       jne     no_msr_11e
+       movl    %ebx, %eax
+       andl    $EAX_MODEL(0xff), %eax
+       cmpl    $EAX_MODEL(0x17), %eax
+       je      has_msr_11e
+       cmpl    $EAX_MODEL(0x1c), %eax
+       je      has_msr_11e
+       andl    $EAX_MODEL(0xf0), %eax
+       cmpl    $EAX_MODEL(0x00), %eax
+       jne     no_msr_11e
+has_msr_11e:
        movl    $0x11e, %ecx
        rdmsr
        orl     $(1 << 8), %eax
        wrmsr
+no_msr_11e:
 
        /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
        movl    %cr0, %eax