2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/stack.h>
22 #include <cpu/x86/mtrr.h>
23 #include <cpu/x86/post_code.h>
24 #include <cpu/x86/lapic_def.h>
26 /* Macro to access Local APIC registers at default base. */
27 #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
29 #define CPU_MAXPHYADDR 36
30 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
32 /* Base address to cache all of Flash ROM, just below 4GB. */
33 #define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
35 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
36 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
38 /* Save the BIST result. */
44 /* Send INIT IPI to all excluding ourself. */
46 movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
49 /* Zero out all fixed range and variable range MTRRs. */
50 movl $mtrr_table, %esi
51 movl $((mtrr_table_end - mtrr_table) / 2), %edi
62 /* Configure the default memory type to uncacheable. */
63 movl $MTRRdefType_MSR, %ecx
65 andl $(~0x00000cff), %eax
68 /* Set Cache-as-RAM base address. */
69 movl $(MTRRphysBase_MSR(0)), %ecx
70 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
74 /* Set Cache-as-RAM mask. */
75 movl $(MTRRphysMask_MSR(0)), %ecx
76 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
77 movl $CPU_PHYSMASK_HI, %edx
81 movl $MTRRdefType_MSR, %ecx
83 orl $MTRRdefTypeEn, %eax
86 /* Enable L2 cache Write-Back (WBINVD and FLUSH#).
88 * MSR is set when DisplayFamily_DisplayModel is one of:
91 * Description says this bit enables use of WBINVD and FLUSH#.
92 * Should this be set only after the system bus and/or memory
93 * controller can successfully handle write cycles?
96 #define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */
97 #define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4))
102 andl $EAX_FAMILY(0x0f), %eax
103 cmpl $EAX_FAMILY(0x06), %eax
106 andl $EAX_MODEL(0xff), %eax
107 cmpl $EAX_MODEL(0x17), %eax
109 cmpl $EAX_MODEL(0x1c), %eax
111 andl $EAX_MODEL(0xf0), %eax
112 cmpl $EAX_MODEL(0x00), %eax
121 /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
123 andl $(~((1 << 30) | (1 << 29))), %eax
127 /* Clear the cache memory reagion. */
130 movl $CACHE_AS_RAM_BASE, %edi
131 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
134 /* Enable Cache-as-RAM mode by disabling cache. */
139 #if CONFIG_XIP_ROM_SIZE
140 /* Enable cache for our code in Flash because we do XIP here */
141 movl $MTRRphysBase_MSR(1), %ecx
144 * IMPORTANT: The following calculation _must_ be done at runtime. See
145 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
147 movl $copy_and_run, %eax
148 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
149 orl $MTRR_TYPE_WRBACK, %eax
152 movl $MTRRphysMask_MSR(1), %ecx
153 movl $CPU_PHYSMASK_HI, %edx
154 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
156 #endif /* CONFIG_XIP_ROM_SIZE */
160 andl $(~((1 << 30) | (1 << 29))), %eax
163 /* Set up the stack pointer. */
165 /* Leave some space for the struct ehci_debug_info. */
166 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp
168 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp
171 /* Restore the BIST result. */
178 /* Call romstage.c main function. */
194 movl $MTRRdefType_MSR, %ecx
196 andl $(~MTRRdefTypeEn), %eax
207 andl $~((1 << 30) | (1 << 29)), %eax
219 /* Enable Write Back and Speculative Reads for low RAM. */
220 movl $MTRRphysBase_MSR(0), %ecx
221 movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
224 movl $MTRRphysMask_MSR(0), %ecx
225 movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
226 movl $CPU_PHYSMASK_HI, %edx
229 /* Enable caching and Speculative Reads for Flash ROM device. */
230 movl $MTRRphysBase_MSR(1), %ecx
231 movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
234 movl $MTRRphysMask_MSR(1), %ecx
235 movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
236 movl $CPU_PHYSMASK_HI, %edx
241 /* And enable cache again after setting MTRRs. */
243 andl $~((1 << 30) | (1 << 29)), %eax
249 movl $MTRRdefType_MSR, %ecx
251 orl $MTRRdefTypeEn, %eax
256 /* Invalidate the cache again. */
261 /* Clear boot_complete flag. */
264 post_code(POST_PREPARE_RAMSTAGE)
265 cld /* Clear direction flag. */
269 movl $ROMSTAGE_STACK, %esp
275 post_code(POST_DEAD_CODE)
281 .word 0x250, 0x258, 0x259
282 .word 0x268, 0x269, 0x26A
283 .word 0x26B, 0x26C, 0x26D
286 .word 0x200, 0x201, 0x202, 0x203
287 .word 0x204, 0x205, 0x206, 0x207
288 .word 0x208, 0x209, 0x20A, 0x20B
289 .word 0x20C, 0x20D, 0x20E, 0x20F