Add an option to keep the ROM cached after romstage

Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d5ab20591b51d5ad02d26d5b52b344ad7b..504d71b4f587e08565ba35b0d39d3865aa23ab3e 100644 (file)
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void);
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);

-
+#else
+#define acpi_slp_type 0

 #endif
 
 /* northbridge/amd/amdfam10/amdfam10_acpi.c */
 #endif
 
 /* northbridge/amd/amdfam10/amdfam10_acpi.c */


@@ -434,6 +435,7 @@ void generate_cpu_entries(void);
 #else // CONFIG_GENERATE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
 #else // CONFIG_GENERATE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)

+#define acpi_slp_type 0

 
 #endif
 
 
 #endif
 

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index d2809f8fe812c559ecd0a9a47802009aeaf26d8e..68946227b96a30967a5ca935ab460b371feb2683 100644 (file)
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -40,4 +40,6 @@ config LOGICAL_CPUS
        bool
        default y
 
        bool
        default y
 

-
+config CACHE_ROM
+       bool
+       default n

diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956a9a9f50846fa79ce5ef168e1356dd3e64..f3fcadc0a7a6845c0e6711d33734b28f4d7c9cc2 100644 (file)
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c

+ramstage-y += boot_cpu.c

diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0883ac076f064679e4436bd1bc8354bb29..0fb9d5d35c587cc28a02b9c0a58b48347dfd1dd6 100644 (file)
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>

 #include <cpu/x86/msr.h>
 
 #if CONFIG_SMP
 #include <cpu/x86/msr.h>
 
 #if CONFIG_SMP

-static int boot_cpu(void)
+int boot_cpu(void)

 {
        int bsp;
        msr_t msr;
 {
        int bsp;
        msr_t msr;

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 46d8e2d4c7a50cdadb5b5fe42ff358752d053ac8..9015ad4d97c9dd96a99333b784e6bbea71a58593 100644 (file)
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,9 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>

+#include <cpu/x86/lapic.h>

 #include <arch/cpu.h>
 #include <arch/cpu.h>

+#include <arch/acpi.h>

 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;


@@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = {
        MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 
        MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 

-

 void enable_fixed_mtrr(void)
 {
        msr_t msr;
 void enable_fixed_mtrr(void)
 {
        msr_t msr;


@@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
        while(var_state.reg < MTRRS) {
                set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
        }
        while(var_state.reg < MTRRS) {
                set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
        }

+
+#if CONFIG_CACHE_ROM
+       /* Enable Caching and speculative Reads for the
+        * complete ROM now that we actually have RAM.
+        */
+       if (boot_cpu() && (acpi_slp_type != 3)) {
+               set_var_mtrr(7, (4096-4)*1024, 4*1024,
+                       MTRR_TYPE_WRPROT, address_bits);
+       }
+#endif
+

        printk(BIOS_SPEW, "call enable_var_mtrr()\n");
        enable_var_mtrr();
        printk(BIOS_SPEW, "Leave %s\n", __func__);
        printk(BIOS_SPEW, "call enable_var_mtrr()\n");
        enable_var_mtrr();
        printk(BIOS_SPEW, "Leave %s\n", __func__);

diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 68608edab1374e94d34a633bb274f94e1a4daf77..2215ec7ee5e28b4d31f67d33b6bcbb82893669f1 100644 (file)
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -27,8 +27,6 @@ static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
        do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
 }
 
        do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
 }
 

-
-

 static inline void enable_lapic(void)
 {
 
 static inline void enable_lapic(void)
 {
 


@@ -53,7 +51,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
        return lapic_read(LAPIC_ID) >> 24;
 }
 
        return lapic_read(LAPIC_ID) >> 24;
 }
 

-
+#ifndef __ROMCC__

 #if CONFIG_AP_IN_SIPI_WAIT != 1
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c
 #if CONFIG_AP_IN_SIPI_WAIT != 1
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c


@@ -156,4 +154,7 @@ int start_cpu(struct device *cpu);
 
 #endif /* !__PRE_RAM__ */
 
 
 #endif /* !__PRE_RAM__ */
 

+int boot_cpu(void);
+#endif
+

 #endif /* CPU_X86_LAPIC_H */
 #endif /* CPU_X86_LAPIC_H */