2 * mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
27 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed
28 2005.6 Eric add address bit in x86_setup_mtrrs
29 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs,
30 for AMD, it will not use x86_setup_fixed_mtrrs
34 #include <console/console.h>
35 #include <device/device.h>
36 #include <cpu/x86/msr.h>
37 #include <cpu/x86/mtrr.h>
38 #include <cpu/x86/cache.h>
42 extern uint64_t uma_memory_base, uma_memory_size;
45 static unsigned int mtrr_msr[] = {
46 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
47 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
48 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
52 void enable_fixed_mtrr(void)
56 msr = rdmsr(MTRRdefType_MSR);
58 wrmsr(MTRRdefType_MSR, msr);
61 static void enable_var_mtrr(void)
65 msr = rdmsr(MTRRdefType_MSR);
66 msr.lo |= MTRRdefTypeEn;
67 wrmsr(MTRRdefType_MSR, msr);
70 /* setting variable mtrr, comes from linux kernel source */
71 static void set_var_mtrr(
72 unsigned int reg, unsigned long basek, unsigned long sizek,
73 unsigned char type, unsigned address_bits)
76 unsigned address_mask_high;
81 // it is recommended that we disable and enable cache when we
87 zero.lo = zero.hi = 0;
88 /* The invalid bit is kept in the mask, so we simply clear the
89 relevant mask register to disable a range. */
90 wrmsr (MTRRphysMask_MSR(reg), zero);
97 address_mask_high = ((1u << (address_bits - 32u)) - 1u);
99 base.hi = basek >> 22;
100 base.lo = basek << 10;
102 printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
104 if (sizek < 4*1024*1024) {
105 mask.hi = address_mask_high;
106 mask.lo = ~((sizek << 10) -1);
109 mask.hi = address_mask_high & (~((sizek >> 22) -1));
113 // it is recommended that we disable and enable cache when we
117 /* Bit 32-35 of MTRRphysMask should be set to 1 */
119 mask.lo |= MTRRphysMaskValid;
120 wrmsr (MTRRphysBase_MSR(reg), base);
121 wrmsr (MTRRphysMask_MSR(reg), mask);
126 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
127 static inline unsigned int fms(unsigned int x)
131 __asm__("bsrl %1,%0\n\t"
134 "1:" : "=r" (r) : "g" (x));
138 /* fls: find least sigificant bit set */
139 static inline unsigned int fls(unsigned int x)
143 __asm__("bsfl %1,%0\n\t"
146 "1:" : "=r" (r) : "g" (x));
150 /* setting up variable and fixed mtrr
152 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
153 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
154 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
155 * requirement. So a 8K range must be 8K aligned not 4K aligned.
157 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
158 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
159 * A 124MB (128MB - 4MB SMA) example:
160 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
161 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
163 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
164 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
165 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
166 * The same 124MB example:
167 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
168 * or a 156MB (128MB + 32MB - 4MB SMA) example:
169 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
171 /* 2 MTRRS are reserved for the operating system */
179 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
182 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
185 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
187 msr.lo = msr.hi = 0; /* Shut up gcc */
188 for(i = first; i < last; i++) {
189 /* When I switch to a new msr read it in */
190 if (fixed_msr != i >> 3) {
191 /* But first write out the old msr */
192 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
194 wrmsr(mtrr_msr[fixed_msr], msr);
198 msr = rdmsr(mtrr_msr[fixed_msr]);
201 msr.lo &= ~(0xff << ((i&3)*8));
202 msr.lo |= type << ((i&3)*8);
204 msr.hi &= ~(0xff << ((i&3)*8));
205 msr.hi |= type << ((i&3)*8);
208 /* Write out the final msr */
209 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
211 wrmsr(mtrr_msr[fixed_msr], msr);
216 static unsigned fixed_mtrr_index(unsigned long addrk)
219 index = (addrk - 0) >> 6;
221 index = ((addrk - 8*64) >> 4) + 8;
224 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
226 if (index > NUM_FIXED_RANGES) {
227 index = NUM_FIXED_RANGES;
232 static unsigned int range_to_mtrr(unsigned int reg,
233 unsigned long range_startk, unsigned long range_sizek,
234 unsigned long next_range_startk, unsigned char type,
235 unsigned int address_bits, unsigned int above4gb)
238 /* If there's no MTRR hole, this function will bail out
239 * here when called for the hole.
241 printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk);
245 if (reg >= BIOS_MTRRS) {
246 printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
247 range_startk >>10, range_sizek >> 10,
248 (type==MTRR_TYPE_UNCACHEABLE)?"UC":
249 ((type==MTRR_TYPE_WRBACK)?"WB":"Other") );
254 unsigned long max_align, align;
256 /* Compute the maximum size I can make a range */
257 max_align = fls(range_startk);
258 align = fms(range_sizek);
259 if (align > max_align) {
263 printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
264 reg, range_startk >>10, sizek >> 10,
265 (type==MTRR_TYPE_UNCACHEABLE)?"UC":
266 ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
269 /* if range is above 4GB, MTRR is needed
270 * only if above4gb flag is set
272 if (range_startk < 0x100000000ull / 1024 || above4gb)
273 set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
274 range_startk += sizek;
275 range_sizek -= sizek;
276 if (reg >= BIOS_MTRRS) {
277 printk(BIOS_ERR, "Running out of variable MTRRs!\n");
284 static unsigned long resk(uint64_t value)
286 unsigned long resultk;
287 if (value < (1ULL << 42)) {
288 resultk = value >> 10;
291 resultk = 0xffffffff;
296 static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
298 unsigned int start_mtrr;
299 unsigned int last_mtrr;
300 start_mtrr = fixed_mtrr_index(resk(res->base));
301 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
302 if (start_mtrr >= NUM_FIXED_RANGES) {
305 printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n",
306 start_mtrr, last_mtrr);
307 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
311 #ifndef CONFIG_VAR_MTRR_HOLE
312 #define CONFIG_VAR_MTRR_HOLE 1
315 struct var_mtrr_state {
316 unsigned long range_startk, range_sizek;
318 unsigned long hole_startk, hole_sizek;
319 unsigned int address_bits;
320 unsigned int above4gb; /* Set if MTRRs are needed for DRAM above 4GB */
323 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
325 struct var_mtrr_state *state = gp;
326 unsigned long basek, sizek;
327 if (state->reg >= BIOS_MTRRS)
329 basek = resk(res->base);
330 sizek = resk(res->size);
331 /* See if I can merge with the last range
332 * Either I am below 1M and the fixed mtrrs handle it, or
335 if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) {
336 unsigned long endk = basek + sizek;
337 state->range_sizek = endk - state->range_startk;
340 /* Write the range mtrrs */
341 if (state->range_sizek != 0) {
342 #if CONFIG_VAR_MTRR_HOLE
343 if (state->hole_sizek == 0) {
344 /* We need to put that on to hole */
345 unsigned long endk = basek + sizek;
346 state->hole_startk = state->range_startk + state->range_sizek;
347 state->hole_sizek = basek - state->hole_startk;
348 state->range_sizek = endk - state->range_startk;
352 state->reg = range_to_mtrr(state->reg, state->range_startk,
353 state->range_sizek, basek, MTRR_TYPE_WRBACK,
354 state->address_bits, state->above4gb);
355 #if CONFIG_VAR_MTRR_HOLE
356 state->reg = range_to_mtrr(state->reg, state->hole_startk,
357 state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE,
358 state->address_bits, state->above4gb);
360 state->range_startk = 0;
361 state->range_sizek = 0;
362 state->hole_startk = 0;
363 state->hole_sizek = 0;
365 /* Allocate an msr */
366 printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
367 state->range_startk = basek;
368 state->range_sizek = sizek;
371 void x86_setup_fixed_mtrrs(void)
373 /* Try this the simple way of incrementally adding together
374 * mtrrs. If this doesn't work out we can get smart again
375 * and clear out the mtrrs.
378 printk(BIOS_DEBUG, "\n");
379 /* Initialized the fixed_mtrrs to uncached */
380 printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n",
381 0, NUM_FIXED_RANGES);
382 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
384 /* Now see which of the fixed mtrrs cover ram.
386 search_global_resources(
387 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
388 set_fixed_mtrr_resource, NULL);
389 printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
391 /* enable fixed MTRR */
392 printk(BIOS_SPEW, "call enable_fixed_mtrr()\n");
397 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
398 /* this routine needs to know how many address bits a given processor
399 * supports. CPUs get grumpy when you set too many bits in
400 * their mtrr registers :( I would generically call cpuid here
401 * and find out how many physically supported but some cpus are
402 * buggy, and report more bits then they actually support.
403 * If above4gb flag is set, variable MTRR ranges must be used to
404 * set cacheability of DRAM above 4GB. If above4gb flag is clear,
405 * some other mechanism is controlling cacheability of DRAM above 4GB.
408 /* Try this the simple way of incrementally adding together
409 * mtrrs. If this doesn't work out we can get smart again
410 * and clear out the mtrrs.
412 struct var_mtrr_state var_state;
414 /* Cache as many memory areas as possible */
415 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
416 * In some cases it is definitely possible to do better.
418 var_state.range_startk = 0;
419 var_state.range_sizek = 0;
420 var_state.hole_startk = 0;
421 var_state.hole_sizek = 0;
423 var_state.address_bits = address_bits;
424 var_state.above4gb = above4gb;
426 search_global_resources(
427 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
428 set_var_mtrr_resource, &var_state);
430 #if (CONFIG_GFXUMA == 1) /* UMA or SP. */
431 /* For now we assume the UMA space is at the end of memory below 4GB */
432 if (var_state.hole_startk || var_state.hole_sizek) {
433 printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
435 #if CONFIG_VAR_MTRR_HOLE
436 // Increase the base range and set up UMA as an UC hole instead
437 var_state.range_sizek += (uma_memory_size >> 10);
439 var_state.hole_startk = (uma_memory_base >> 10);
440 var_state.hole_sizek = (uma_memory_size >> 10);
444 /* Write the last range */
445 var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
446 var_state.range_sizek, 0, MTRR_TYPE_WRBACK,
447 var_state.address_bits, var_state.above4gb);
448 #if CONFIG_VAR_MTRR_HOLE
449 var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
450 var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE,
451 var_state.address_bits, var_state.above4gb);
453 printk(BIOS_DEBUG, "DONE variable MTRRs\n");
454 printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
455 /* Clear out the extra MTRR's */
456 while(var_state.reg < MTRRS) {
457 set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
459 printk(BIOS_SPEW, "call enable_var_mtrr()\n");
461 printk(BIOS_SPEW, "Leave %s\n", __func__);
466 void x86_setup_mtrrs(void)
469 x86_setup_fixed_mtrrs();
470 address_size = cpu_phys_address_size();
471 printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size);
472 x86_setup_var_mtrrs(address_size, 1);
476 int x86_mtrr_check(void)
478 /* Only Pentium Pro and later have MTRR */
480 printk(BIOS_DEBUG, "\nMTRR check\n");
485 printk(BIOS_DEBUG, "Fixed MTRRs : ");
487 printk(BIOS_DEBUG, "Enabled\n");
489 printk(BIOS_DEBUG, "Disabled\n");
491 printk(BIOS_DEBUG, "Variable MTRRs: ");
493 printk(BIOS_DEBUG, "Enabled\n");
495 printk(BIOS_DEBUG, "Disabled\n");
497 printk(BIOS_DEBUG, "\n");
500 return ((int) msr.lo);