src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
  21                                 u32 *AddrTmgCTL, u32 *ODC_CTL,
  22                                 u8 *CMDmode);
  23
  24 void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
  25                          struct DCTStatStruc *pDCTstat, u32 dct)
  26 {
  27         Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
  28                                 pDCTstat->MAload[dct],
  29                                 &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
  30                                 &pDCTstat->_2Tmode);
  31
  32         pDCTstat->CH_EccDQSLike[0]  = 0x0403;
  33         pDCTstat->CH_EccDQSScale[0] = 0x70;
  34         pDCTstat->CH_EccDQSLike[1]  = 0x0403;
  35         pDCTstat->CH_EccDQSScale[1] = 0x70;
  36
  37         pDCTstat->CH_ODC_CTL[dct] |= 0x20000000;        /* 60ohms */
  38 }
  39
  40 /*
  41  *  In: MAAdimms   - number of DIMMs on the channel
  42  *    : Speed      - Speed (see DCTStatstruc.Speed for definition)
  43  *    : MAAload    - number of address bus loads on the channel
  44  * Out: AddrTmgCTL - Address Timing Control Register Value
  45  *    : ODC_CTL    - Output Driver Compensation Control Register Value
  46  *    : CMDmode    - CMD mode
  47  */
  48 static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
  49                                 u32 *AddrTmgCTL, u32 *ODC_CTL,
  50                                 u8 *CMDmode)
  51 {
  52         *AddrTmgCTL = 0;
  53         *ODC_CTL = 0;
  54         *CMDmode = 1;
  55
  56         if(MAAdimms == 1) {
  57                 if(MAAload >= 16) {
  58                         if(Speed == 4)
  59                                 *AddrTmgCTL = 0x003B0000;
  60                         else if (Speed == 5)
  61                                 *AddrTmgCTL = 0x00380000;
  62                         else if (Speed == 6)
  63                                 *AddrTmgCTL = 0x00360000;
  64                         else
  65                                 *AddrTmgCTL = 0x00340000;
  66                 } else {
  67                         *AddrTmgCTL = 0x00000000;
  68                 }
  69                 *ODC_CTL = 0x00113222;
  70                 *CMDmode = 1;
  71         } else /* if(MAAdimms == 0) */ {
  72                 if(Speed == 4) {
  73                         *CMDmode = 1;
  74                         *AddrTmgCTL = 0x00390039;
  75                 } else if(Speed == 5) {
  76                         *CMDmode = 1;
  77                         *AddrTmgCTL = 0x00350037;
  78                 } else if(Speed == 6) {
  79                         *CMDmode = 2;
  80                         *AddrTmgCTL = 0x00000035;
  81                 } else {
  82                         *CMDmode = 2;
  83                         *AddrTmgCTL = 0x00000033;
  84                 }
  85                 *ODC_CTL = 0x00223323;
  86         }
  87 }