2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * Description: Include file for all generic DDR 3 MCT files.
26 /*===========================================================================
28 ===========================================================================*/
29 #define PT_L1 0 /* CPU Package Type */
36 #define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
37 #define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/
38 #define K_MIN 1 /* k loop constraint. 1=200 Mhz*/
39 #define K_MAX 5 /* k loop constraint. 5=533 Mhz*/
40 #define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/
41 #define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/
43 #define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/
44 /* memory initialization (ecc and check-bits).*/
45 /* 1=40 ns/64 bytes.*/
46 #define FirstPass 1 /* First pass through RcvEn training*/
47 #define SecondPass 2 /* Second pass through Rcven training*/
49 #define RCVREN_MARGIN 6 /* number of DLL taps to delay beyond first passing position*/
50 #define MAXASYNCLATCTL_2 2 /* Max Async Latency Control value*/
51 #define MAXASYNCLATCTL_3 3 /* Max Async Latency Control value*/
55 #define DQS_WRITEDIR 1
57 #define MIN_DQS_WNDW 3
58 #define secPassOffset 6
59 #define Pass1MemClkDly 0x20 /* Add 1/2 Memlock delay */
60 #define MAX_RD_LAT 0x3FF
63 #define MIN_DQS_WR_FENCE 14
64 #define MAX_DQS_WR_FENCE 20
65 #define FenceTrnFinDlySeed 19
68 #define PA_HOST(Node) ((((0x18+Node) << 3)+0) << 12) /* Node 0 Host Bus function PCI Address bits [15:0]*/
69 #define PA_MAP(Node) ((((0x18+Node) << 3)+1) << 12) /* Node 0 MAP function PCI Address bits [15:0]*/
70 #define PA_DCT(Node) ((((0x18+Node) << 3)+2) << 12) /* Node 0 DCT function PCI Address bits [15:0]*/
71 /* #define PA_EXT_DCT (((00 << 3)+4) << 8) */ /*Node 0 DCT extended configuration registers*/
72 /* #define PA_DCTADDL (((00 << 3)+2) << 8) */ /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/
73 /* #define PA_EXT_DCTADDL (((00 << 3)+5) << 8) */ /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/
75 #define PA_NBMISC(Node) ((((0x18+Node) << 3)+3) << 12) /*Node 0 Misc PCI Address bits [15:0]*/
76 /* #define PA_NBDEVOP (((00 << 3)+3) << 8) */ /*Node 0 Misc PCI Address bits [15:0]*/
78 #define DCC_EN 1 /* X:2:0x94[19]*/
79 #define ILD_Lmt 3 /* X:2:0x94[18:16]*/
81 #define EncodedTSPD 0x00191709 /* encodes which SPD byte to get T from*/
82 /* versus CL X, CL X-.5, and CL X-1*/
84 #define Bias_TrpT 5 /* bias to convert bus clocks to bit field value*/
94 #define Min_TrpT 5 /* min programmable value in busclocks */
95 #define Max_TrpT 12 /* max programmable value in busclocks */
113 /*common register bit names*/
114 #define DramHoleValid 0 /* func 1, offset F0h, bit 0*/
115 #define DramMemHoistValid 1 /* func 1, offset F0h, bit 1*/
116 #define CSEnable 0 /* func 2, offset 40h-5C, bit 0*/
117 #define Spare 1 /* func 2, offset 40h-5C, bit 1*/
118 #define TestFail 2 /* func 2, offset 40h-5C, bit 2*/
119 #define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/
120 #define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/
121 #define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/
122 #define InitDram 0 /* func 2, offset 90h, bit 0*/
123 #define BurstLength32 10 /* func 2, offset 90h, bit 10*/
124 #define Width128 11 /* func 2, offset 90h, bit 11*/
125 #define X4Dimm 12 /* func 2, offset 90h, bit 12*/
126 #define UnBuffDimm 16 /* func 2, offset 90h, bit 16*/
127 #define DimmEcEn 19 /* func 2, offset 90h, bit 19*/
128 #define MemClkFreqVal 3 /* func 2, offset 94h, bit 3*/
129 #define RDqsEn 12 /* func 2, offset 94h, bit 12*/
130 #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/
131 #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/
132 #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/
133 #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/
134 #define PwrSavingsEn 10 /* func 2, offset A0h, bit 10*/
135 #define Mod64BitMux 4 /* func 2, offset A0h, bit 4*/
136 #define DisableJitter 1 /* func 2, offset A0h, bit 1*/
137 #define MemClrDis 1 /* func 3, offset F8h, FNC 4, bit 1*/
138 #define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2*/
139 #define Dr_MemClrStatus 10 /* func 3, offset 110h, bit 10*/
140 #define MemClrBusy 9 /* func 3, offset 110h, bit 9*/
141 #define DctGangEn 4 /* func 3, offset 110h, bit 4*/
142 #define MemClrInit 3 /* func 3, offset 110h, bit 3*/
143 #define SendZQCmd 29 /* func 2, offset 7Ch, bit 29 */
144 #define AssertCke 28 /* func 2, offset 7Ch, bit 28*/
145 #define DeassertMemRstX 27 /* func 2, offset 7Ch, bit 27*/
146 #define SendMrsCmd 26 /* func 2, offset 7Ch, bit 26*/
147 #define SendAutoRefresh 25 /* func 2, offset 7Ch, bit 25*/
148 #define SendPchgAll 24 /* func 2, offset 7Ch, bit 24*/
149 #define DisDqsBar 6 /* func 2, offset 90h, bit 6*/
150 #define DramEnabled 8 /* func 2, offset 110h, bit 8*/
151 #define LegacyBiosMode 9 /* func 2, offset 94h, bit 9*/
152 #define PrefDramTrainMode 28 /* func 2, offset 11Ch, bit 28*/
153 #define FlushWr 30 /* func 2, offset 11Ch, bit 30*/
154 #define DisAutoComp 30 /* func 2, offset 9Ch, Index 8, bit 30*/
155 #define DqsRcvTrEn 13 /* func 2, offset 9Ch, Index 8, bit 13*/
156 #define ForceAutoPchg 23 /* func 2, offset 90h, bit 23*/
157 #define ClLinesToNbDis 15 /* Bu_CFG2, bit 15*/
158 #define WbEnhWsbDis_D (48-32)
159 #define PhyFenceTrEn 3 /* func 2, offset 9Ch, Index 8, bit 3 */
160 #define ParEn 8 /* func 2, offset 90h, bit 8 */
161 #define DcqArbBypassEn 19 /* func 2, offset 94h, bit 19 */
162 #define ActiveCmdAtRst 1 /* func 2, offset A8H, bit 1 */
163 #define FlushWrOnStpGnt 29 /* func 2, offset 11Ch, bit 29 */
164 #define BankSwizzleMode 22 /* func 2, offset 94h, bit 22 */
165 #define ChSetupSync 15 /* func 2, offset 78h, bit 15 */
167 #define Ddr3Mode 8 /* func 2, offset 94h, bit 8 */
168 #define EnterSelfRef 17 /* func 2, offset 90h, bit 17 */
169 #define onDimmMirror 3 /* func 2, offset 5C:40h, bit 3 */
170 #define OdtSwizzle 6 /* func 2, offset A8h, bit 6 */
171 #define FreqChgInProg 21 /* func 2, offset 94h, bit 21 */
172 #define ExitSelfRef 1 /* func 2, offset 90h, bit 1 */
174 #define SubMemclkRegDly 5 /* func 2, offset A8h, bit 5 */
175 #define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */
176 #define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */
178 /*=============================================================================
180 ============================================================================*/
182 #define OCD_Default 2
185 /*=============================================================================
187 =============================================================================*/
188 #define SPD_ByteUse 0
189 #define SPD_TYPE 2 /*SPD byte read location*/
190 #define JED_DDRSDRAM 0x07 /*Jedec defined bit field*/
191 #define JED_DDR2SDRAM 0x08 /*Jedec defined bit field*/
192 #define JED_DDR3SDRAM 0x0B /* Jedec defined bit field*/
194 #define SPD_DIMMTYPE 3
195 #define SPD_ATTRIB 21
196 #define JED_DIFCKMSK 0x20 /*Differential Clock Input*/
197 #define JED_REGADCMSK 0x11 /*Registered Address/Control*/
198 #define JED_PROBEMSK 0x40 /*Analysis Probe installed*/
199 #define JED_RDIMM 0x1 /* RDIMM */
200 #define JED_MiniRDIMM 0x5 /* Mini-RDIMM */
201 #define SPD_Density 4 /* Bank address bits,SDRAM capacity */
202 #define SPD_Addressing 5 /* Row/Column address bits */
203 #define SPD_Organization 7 /* rank#,Device width */
204 #define SPD_BusWidth 8 /* ECC, Bus width */
205 #define JED_ECC 8 /* ECC capability */
207 #define SPD_MTBDividend 10
208 #define SPD_MTBDivisor 11
209 #define SPD_tCKmin 12
210 #define SPD_CASLow 14
211 #define SPD_CASHigh 15
212 #define SPD_tAAmin 16
214 #define SPD_DEVATTRIB 22
215 #define SPD_EDCTYPE 11
216 #define JED_ADRCPAR 0x04
218 #define SPD_tWRmin 17
219 #define SPD_tRCDmin 18
220 #define SPD_tRRDmin 19
221 #define SPD_tRPmin 20
222 #define SPD_Upper_tRAS_tRC 21
223 #define SPD_tRASmin 22
224 #define SPD_tRCmin 23
225 #define SPD_tWTRmin 26
226 #define SPD_tRTPmin 27
227 #define SPD_Upper_tFAW 28
228 #define SPD_tFAWmin 29
230 #define SPD_RefRawCard 62
231 #define SPD_AddressMirror 63
232 #define SPD_RegManufactureID_L 65 /* not used */
233 #define SPD_RegManufactureID_H 66 /* not used */
234 #define SPD_RegManRevID 67 /* not used */
236 #define SPD_byte_126 126
237 #define SPD_byte_127 127
241 #define SPD_LBANKS 17 /*number of [logical] banks on each device*/
242 #define SPD_DMBANKS 5 /*number of physical banks on dimm*/
243 #define SPDPLBit 4 /* Dram package bit*/
244 #define SPD_BANKSZ 31 /*capacity of physical bank*/
245 #define SPD_DEVWIDTH 13
246 #define SPD_CASLAT 18
254 #define SPD_TRCRFC 40
258 #define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/
260 #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/
262 /*-----------------------------
263 Jdec DDR II related equates
264 -----------------------------*/
265 #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/
266 #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/
268 /*=============================================================================
270 =============================================================================*/
272 #define _2GB_RJ8 (2<<(30-8))
273 #define _4GB_RJ8 (4<<(30-8))
274 #define _4GB_RJ4 (4<<(30-4))
276 #define BigPagex8_RJ8 (1<<(17+3-8)) /*128KB * 8 >> 8 */
278 /*=============================================================================
279 Global MCT Status Structure
280 =============================================================================*/
281 struct MCTStatStruc {
282 u32 GStatus; /* Global Status bitfield*/
283 u32 HoleBase; /* If not zero, BASE[39:8] (system address)
284 of sub 4GB dram hole for HW remapping.*/
285 u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
286 u32 SysLimit; /* LIMIT[39:8] (system address)*/
289 /*=============================================================================
290 Global MCT Configuration Status Word (GStatus)
291 =============================================================================*/
292 /*These should begin at bit 0 of GStatus[31:0]*/
293 #define GSB_MTRRshort 0 /* Ran out of MTRRs while mapping memory*/
294 #define GSB_ECCDIMMs 1 /* All banks of all Nodes are ECC capable*/
295 #define GSB_DramECCDis 2 /* Dram ECC requested but not enabled.*/
296 #define GSB_SoftHole 3 /* A Node Base gap was created*/
297 #define GSB_HWHole 4 /* A HW dram remap was created*/
298 #define GSB_NodeIntlv 5 /* Node Memory interleaving was enabled*/
299 #define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/
300 #define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */
301 /* NOTE: This is a local bit used by memory code */
303 /*===============================================================================
304 Local DCT Status structure (a structure for each DCT)
305 ===============================================================================*/
306 #include "mwlc_d.h" /* I have to */
308 struct DCTStatStruc { /* A per Node structure*/
309 /* DCTStatStruct_F - start */
310 u8 Node_ID; /* Node ID of current controller*/
311 u8 ErrCode; /* Current error condition of Node
313 1= Variance Error, DCT is running but not in an optimal configuration.
314 2= Stop Error, DCT is NOT running
315 3= Fatal Error, DCT/MCT initialization has been halted.*/
316 u32 ErrStatus; /* Error Status bit Field */
317 u32 Status; /* Status bit Field*/
318 u8 DIMMAddr[8]; /* SPD address of DIMM controlled by MA0_CS_L[0,1]*/
319 /* SPD address of..MB0_CS_L[0,1]*/
320 /* SPD address of..MA1_CS_L[0,1]*/
321 /* SPD address of..MB1_CS_L[0,1]*/
322 /* SPD address of..MA2_CS_L[0,1]*/
323 /* SPD address of..MB2_CS_L[0,1]*/
324 /* SPD address of..MA3_CS_L[0,1]*/
325 /* SPD address of..MB3_CS_L[0,1]*/
326 u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present.
336 u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/
337 u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */
338 u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/
339 u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/
340 u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/
341 u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/
342 u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/
343 u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/
344 u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/
345 u8 MAload[2]; /* Number of devices loading MAA bus*/
346 /* Number of devices loading MAB bus*/
347 u8 MAdimms[2]; /*Number of DIMMs loading CH A*/
348 /* Number of DIMMs loading CH B*/
349 u8 DATAload[2]; /*Number of ranks loading CH A DATA*/
350 /* Number of ranks loading CH B DATA*/
351 u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs
357 u8 DIMMCASL; /* Min valid Mfg. CL bitfield
363 u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/
364 u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/
365 u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/
366 u16 DIMMTras; /* Minimax Tras*40 (ns) of DIMMs*/
367 u16 DIMMTrc; /* Minimax Trc*40 (ns) of DIMMs*/
368 u16 DIMMTwr; /* Minimax Twr*40 (ns) of DIMMs*/
369 u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/
370 u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/
371 u8 Speed; /* Bus Speed (to set Controller)
376 u8 CASL; /* CAS latency DCT setting
382 u8 Trcd; /* DCT Trcd (busclocks) */
383 u8 Trp; /* DCT Trp (busclocks) */
384 u8 Trtp; /* DCT Trtp (busclocks) */
385 u8 Tras; /* DCT Tras (busclocks) */
386 u8 Trc; /* DCT Trc (busclocks) */
387 u8 Twr; /* DCT Twr (busclocks) */
388 u8 Trrd; /* DCT Trrd (busclocks) */
389 u8 Twtr; /* DCT Twtr (busclocks) */
390 u8 Trfc[4]; /* DCT Logical DIMM0 Trfc
391 0=75ns (for 256Mb devs)
392 1=105ns (for 512Mb devs)
393 2=127.5ns (for 1Gb devs)
394 3=195ns (for 2Gb devs)
395 4=327.5ns (for 4Gb devs) */
396 /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */
397 /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */
398 /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */
399 u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */
400 u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */
401 u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */
402 u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */
403 u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */
404 u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency
408 400=400Mhz (DDR800) */
409 u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode)
412 u8 TrwtTO; /* DCT TrwtTO (busclocks)*/
413 u8 Twrrd; /* DCT Twrrd (busclocks)*/
414 u8 Twrwr; /* DCT Twrwr (busclocks)*/
415 u8 Trdrd; /* DCT Trdrd (busclocks)*/
416 u32 CH_ODC_CTL[2]; /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h*/
417 u32 CH_ADDR_TMG[2]; /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h*/
418 /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 20h*/
419 /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 24h*/
420 u16 CH_EccDQSLike[2]; /* CHA DQS ECC byte like...*/
421 u8 CH_EccDQSScale[2]; /* CHA DQS ECC byte scale*/
422 /* CHA DQS ECC byte like...*/
423 /* CHA DQS ECC byte scale*/
424 u8 MaxAsyncLat; /* Max Asynchronous Latency (ns)*/
425 /* NOTE: Not used in Barcelona - u8 CH_D_RCVRDLY[2][4]; */
426 /* CHA DIMM 0 - 4 Receiver Enable Delay*/
427 /* CHB DIMM 0 - 4 Receiver Enable Delay */
428 /* NOTE: Not used in Barcelona - u8 CH_D_B_DQS[2][2][8]; */
429 /* CHA Byte 0-7 Write DQS Delay */
430 /* CHA Byte 0-7 Read DQS Delay */
431 /* CHB Byte 0-7 Write DQS Delay */
432 /* CHB Byte 0-7 Read DQS Delay */
433 u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/
434 u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/
435 u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/
436 u8 ByteLane; /* Current Byte Lane (0..7)*/
437 u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/
438 u8 Pattern; /* Current pattern*/
439 u8 DQSDelay; /* Current DQS delay value*/
440 u32 TrainErrors; /* Current Training Errors*/
442 u32 AMC_TSC_DeltaLo; /* Time Stamp Counter measurement of AMC, Low dword*/
443 u32 AMC_TSC_DeltaHi; /* Time Stamp Counter measurement of AMC, High dword*/
444 /* NOTE: Not used in Barcelona - */
445 u8 CH_D_DIR_MaxMin_B_Dly[2][2][2][8];
446 /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
447 /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
448 /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
449 /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
450 /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
451 /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
452 /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
453 /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
454 u32 LogicalCPUID; /* The logical CPUID of the node*/
455 u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/
456 u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/
457 u16 DimmQRPresent; /* QuadRank DIMM present?*/
458 u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/
459 u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/
460 u16 DimmYr06; /* Bitmap indicating which Dimms have a manufactur's year code <= 2006*/
461 u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/
462 u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/
463 u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/
464 u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects
465 0 in any bit field indicates Channel 0
466 1 in any bit field indicates Channel 1 */
467 u16 DIMMTfaw; /* Minimax Tfaw*16 (ns) of DIMMs */
468 u8 Tfaw; /* DCT Tfaw (busclocks) */
469 u16 CSUsrTestFail; /* Chip selects excluded by user */
470 /* DCTStatStruct_F - end */
472 u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/
473 /* Max Read Latency (ns) for DCT 1*/
474 u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */
475 /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/
476 /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/
477 /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/
478 /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/
479 /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/
480 /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/
481 /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/
482 /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/
483 u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */
484 /* CHA DIMM0 Byte 0 - 7 TxDqs */
485 /* CHA DIMM0 Byte 0 - 7 TxDqs */
486 /* CHA DIMM1 Byte 0 - 7 TxDqs */
487 /* CHA DIMM1 Byte 0 - 7 TxDqs */
488 /* CHB DIMM0 Byte 0 - 7 TxDqs */
489 /* CHB DIMM0 Byte 0 - 7 TxDqs */
490 /* CHB DIMM1 Byte 0 - 7 TxDqs */
491 /* CHB DIMM1 Byte 0 - 7 TxDqs */
492 u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */
493 /* CHA DIMM 0 Receiver Enable Delay*/
494 /* CHA DIMM 1 Receiver Enable Delay*/
495 /* CHA DIMM 2 Receiver Enable Delay*/
496 /* CHA DIMM 3 Receiver Enable Delay*/
498 /* CHB DIMM 0 Receiver Enable Delay*/
499 /* CHB DIMM 1 Receiver Enable Delay*/
500 /* CHB DIMM 2 Receiver Enable Delay*/
501 /* CHB DIMM 3 Receiver Enable Delay*/
502 u8 CH_D_BC_RCVRDLY[2][4];
503 /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/
504 /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/
505 u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/
507 u16 CSPresent_DCT[2]; /* DCT# CS mapping */
508 u16 MirrPresU_NumRegR; /* Address mapping from edge connect to DIMM present for unbuffered dimm
509 Number of registers on the dimm for registered dimm */
510 u8 MaxDCTs; /* Max number of DCTs in system*/
511 /* NOTE: removed u8 DCT. Use ->dev_ for pci R/W; */ /*DCT pointer*/
512 u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/
513 u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/
514 u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/
517 /* NOTE: Not used - u8 NodeSpeed */ /* Bus Speed (to set Controller) */
521 /* NOTE: Not used - u8 NodeCASL */ /* CAS latency DCT setting */
528 u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/
529 u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/
530 u8 DqsRcvEn_Pass; /* for TrainRcvrEn byte lane pass flag*/
531 u8 DqsRcvEn_Saved; /* for TrainRcvrEn byte lane saved flag*/
532 u8 SeedPass1Remainder; /* for Phy assisted DQS receiver enable training*/
534 /* for second pass - Second pass should never run for Fam10*/
535 /* NOTE: Not used for Barcelona - u8 CH_D_B_RCVRDLY_1[2][4][8]; */ /* CHA DIMM 0 Receiver Enable Delay */
536 /* CHA DIMM 1 Receiver Enable Delay*/
537 /* CHA DIMM 2 Receiver Enable Delay*/
538 /* CHA DIMM 3 Receiver Enable Delay*/
540 /* CHB DIMM 0 Receiver Enable Delay*/
541 /* CHB DIMM 1 Receiver Enable Delay*/
542 /* CHB DIMM 2 Receiver Enable Delay*/
543 /* CHB DIMM 3 Receiver Enable Delay*/
545 u8 ClToNB_flag; /* is used to restore ClLinesToNbDis bit after memory */
546 u32 NodeSysBase; /* for channel interleave usage */
548 /* New for LB Support */
565 u16 RegMan1Present; /* DIMM present bitmap of Register manufacture 1 */
566 u16 RegMan2Present; /* DIMM present bitmap of Register manufacture 2 */
568 struct _sMCTStruct *C_MCTPtr;
569 struct _sDCTStruct *C_DCTPtr[2];
570 /* struct _sDCTStruct *C_DCT1Ptr; */
572 struct _sMCTStruct s_C_MCTPtr;
573 struct _sDCTStruct s_C_DCTPtr[2];
574 /* struct _sDCTStruct s_C_DCT1Ptr[8]; */
577 /*===============================================================================
578 Local Error Status Codes (DCTStatStruc.ErrCode)
579 ===============================================================================*/
580 #define SC_RunningOK 0
581 #define SC_VarianceErr 1 /* Running non-optimally*/
582 #define SC_StopError 2 /* Not Running*/
583 #define SC_FatalErr 3 /* Fatal Error, MCTB has exited immediately*/
585 /*===============================================================================
586 Local Error Status (DCTStatStruc.ErrStatus[31:0])
587 ===============================================================================*/
589 #define SB_DIMMChkSum 1
590 #define SB_DimmMismatchM 2 /* dimm module type(buffer) mismatch*/
591 #define SB_DimmMismatchT 3 /* dimm CL/T mismatch*/
592 #define SB_DimmMismatchO 4 /* dimm organization mismatch (128-bit)*/
593 #define SB_NoTrcTrfc 5 /* SPD missing Trc or Trfc info*/
594 #define SB_NoCycTime 6 /* SPD missing byte 23 or 25*/
595 #define SB_BkIntDis 7 /* Bank interleave requested but not enabled*/
596 #define SB_DramECCDis 8 /* Dram ECC requested but not enabled*/
597 #define SB_SpareDis 9 /* Online spare requested but not enabled*/
598 #define SB_MinimumMode 10 /* Running in Minimum Mode*/
599 #define SB_NORCVREN 11 /* No DQS Receiver Enable pass window found*/
600 #define SB_CHA2BRCVREN 12 /* DQS Rcvr En pass window CHA to CH B too large*/
601 #define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/
602 #define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/
603 #define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/
604 #define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */
606 /*===============================================================================
607 Local Configuration Status (DCTStatStruc.Status[31:0])
608 ===============================================================================*/
609 #define SB_Registered 0 /* All DIMMs are Registered*/
610 #define SB_ECCDIMMs 1 /* All banks ECC capable*/
611 #define SB_PARDIMMs 2 /* All banks Addr/CMD Parity capable*/
612 #define SB_DiagClks 3 /* Jedec ALL slots clock enable diag mode*/
613 #define SB_128bitmode 4 /* DCT in 128-bit mode operation*/
614 #define SB_64MuxedMode 5 /* DCT in 64-bit mux'ed mode.*/
615 #define SB_2TMode 6 /* 2T CMD timing mode is enabled.*/
616 #define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/
617 #define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/
618 #define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/
619 #define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/
620 #define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/
621 #define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/
624 /*===============================================================================
625 NVRAM/run-time-configurable Items
626 ===============================================================================*/
627 /*Platform Configuration*/
628 #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits)
632 #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/
633 #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/
634 #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits)
638 400=400Mhz (DDR800)*/
639 #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits)
640 0=Platform not capable
641 1=Platform is capable*/
642 #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits)
644 1=R4 (4-Rank Registered DIMMs in AMD server configuration)
645 2=S4 (Unbuffered SO-DIMMs)*/
646 #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition).
647 4=4 times bypass (normal for non-UMA systems)
648 7=7 times bypass (normal for UMA systems)*/
649 #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition).
650 2=8 times (normal for non-UMA systems)
651 3=16 times (normal for UMA systems)*/
655 #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits)
656 0=Auto, no user limit
657 1=Auto, user limit provided in NV_MemCkVal
658 2=Manual, user value provided in NV_MemCkVal*/
659 #define NV_MemCkVal 11 /* Memory Clock Value (2-bits)
665 /*Dram Configuration*/
666 #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits)
669 #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits)
671 1=enable all memclocks*/
672 #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits)
673 0=Exit current node init if any DIMM has SPD checksum error
674 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
675 #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control
677 1=perform DQS training*/
678 #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits)
681 #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits)
683 1=enable (4 beat burst when width is 64-bits)*/
686 #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits)
689 #define NV_CKE_CTL 31 /* CKE based power down control (1-bits)
690 0=per Channel control
691 1=per Chip select control*/
692 #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits)
697 #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits)
698 NV_BottomIO[7:0]=Addr[31:24]*/
699 #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits)
700 NV_BottomUMA[7:0]=Addr[31:24]*/
701 #define NV_MemHole 42 /* Memory Hole Remapping (1-bits)
706 #define NV_ECC 50 /* Dram ECC enable*/
707 #define NV_NBECC 52 /* ECC MCE enable*/
708 #define NV_ChipKill 53 /* Chip-Kill ECC Mode enable*/
709 #define NV_ECCRedir 54 /* Dram ECC Redirection enable*/
710 #define NV_DramBKScrub 55 /* Dram ECC Background Scrubber CTL*/
711 #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/
712 #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/
713 #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0:
716 /* Chip Select Spare Control bit 1-4:
717 Reserved, must be zero*/
718 #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control
721 #define NV_Unganged 62
723 #define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits)
725 yy1b = enable with DctSelIntLvAddr set to yyb */
728 #ifndef MAX_NODES_SUPPORTED
729 #define MAX_NODES_SUPPORTED 8
732 #ifndef MAX_DIMMS_SUPPORTED
733 #define MAX_DIMMS_SUPPORTED 8
736 #ifndef MAX_CS_SUPPORTED
737 #define MAX_CS_SUPPORTED 8
740 #ifndef MCT_DIMM_SPARE_NO_WARM
741 #define MCT_DIMM_SPARE_NO_WARM 0
744 u32 Get_NB32(u32 dev, u32 reg);
745 void Set_NB32(u32 dev, u32 reg, u32 val);
746 u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);
747 void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data);
748 u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index);
749 void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data);
750 u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val);
751 void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct);
752 u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value);
753 u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass);
754 u32 SetupDqsPattern_1PassA(u8 Pass);
755 u32 SetupDqsPattern_1PassB(u8 Pass);
756 u8 mct_Get_Start_RcvrEnDly_1Pass(u8 Pass);
757 u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass);
758 void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
759 void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
760 u32 mctGetLogicalCPUID(u32 Node);
761 u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
762 void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass);
763 void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
764 void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
765 void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
766 void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,struct DCTStatStruc *pDCTstatA);
767 void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass);
768 void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel);
769 void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct);
770 void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct);
771 void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, u32 DramConfigHi);
772 void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct);
773 void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
774 void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
775 void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass);
776 void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC);
777 u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val);
778 void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct);
779 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
780 void mctSMBhub_Init(u32 node);
781 int mctRead_SPD(u32 smaddr, u32 reg);
782 void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
783 void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
784 void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
786 void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
787 u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass);
788 u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct);
789 void mct_Wait(u32 cycles);
790 u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel);
791 u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid);
792 void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr);