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(parent: 4dd3853) | patch
Add support for Intel Sandybridge CPU (northbridge part)
authorStefan Reinauer <stefan.reinauer@coreboot.org>
Tue, 3 Apr 2012 22:08:51 +0000 (00:08 +0200)
committerStefan Reinauer <stefan.reinauer@coreboot.org>
Thu, 5 Apr 2012 18:59:31 +0000 (20:59 +0200)
commit00636b0daefc3c499990744226a0e1a316d71731
tree4360fe7a5817a4d6c2164daf547b7d9ba5bd46a8tree | snapshot
parent4dd3853437a3506880e2879e6640d455778f6413commit | diff
Add support for Intel Sandybridge CPU (northbridge part)

Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/854
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
19 files changed:
src/northbridge/intel/Kconfig diff | blob | history
src/northbridge/intel/Makefile.inc diff | blob | history
src/northbridge/intel/sandybridge/Kconfig [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/Makefile.inc [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/acpi.c [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/acpi/hostbridge.asl [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/acpi/igd.asl [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/acpi/sandybridge.asl [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/chip.h [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/early_init.c [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/finalize.c [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/gma.c [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/northbridge.c [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/pcie_config.c [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/pei_data.h [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/raminit.c [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/raminit.h [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/sandybridge.h [new file with mode: 0644] blob
src/northbridge/intel/sandybridge/udelay.c [new file with mode: 0644] blob
my coreboot WIP stuff (asus m5a99x-evo board)