src/northbridge/intel/sandybridge/gma.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Chromium OS Authors
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <arch/io.h>
  21 #include <console/console.h>
  22 #include <delay.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26
  27 #include "chip.h"
  28 #include "sandybridge.h"
  29
  30 /* some vga option roms are used for several chipsets but they only have one
  31  * PCI ID in their header. If we encounter such an option rom, we need to do
  32  * the mapping ourselfes
  33  */
  34
  35 u32 map_oprom_vendev(u32 vendev)
  36 {
  37         u32 new_vendev=vendev;
  38
  39         switch (vendev) {
  40         case 0x01028086:                /* GT1 Desktop */
  41         case 0x010a8086:                /* GT1 Server */
  42         case 0x01128086:                /* GT2 Desktop */
  43         case 0x01168086:                /* GT2 Mobile */
  44         case 0x01228086:                /* GT2 Desktop >=1.3GHz */
  45         case 0x01268086:                /* GT2 Mobile >=1.3GHz */
  46         case 0x01668086:                /* IVB */
  47                 new_vendev=0x01068086;  /* GT1 Mobile */
  48                 break;
  49         }
  50
  51         return new_vendev;
  52 }
  53
  54 static struct resource *gtt_res = NULL;
  55
  56 static inline u32 gtt_read(u32 reg)
  57 {
  58         return read32(gtt_res->base + reg);
  59 }
  60
  61 static inline void gtt_write(u32 reg, u32 data)
  62 {
  63         write32(gtt_res->base + reg, data);
  64 }
  65
  66 #define GTT_RETRY 1000
  67 static int gtt_poll(u32 reg, u32 mask, u32 value)
  68 {
  69         unsigned try = GTT_RETRY;
  70         u32 data;
  71
  72         while (try--) {
  73                 data = gtt_read(reg);
  74                 if ((data & mask) == value)
  75                         return 1;
  76                 udelay(10);
  77         }
  78
  79         printk(BIOS_ERR, "GT init timeout\n");
  80         return 0;
  81 }
  82
  83 static void gma_pm_init_pre_vbios(struct device *dev)
  84 {
  85         u32 reg32;
  86
  87         printk(BIOS_DEBUG, "GT Power Management Init\n");
  88
  89         gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
  90         if (!gtt_res || !gtt_res->base)
  91                 return;
  92
  93         if (bridge_silicon_revision() < IVB_STEP_C0) {
  94                 /* 1: Enable force wake */
  95                 gtt_write(0xa18c, 0x00000001);
  96                 if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
  97                         return;
  98         } else {
  99                 gtt_write(0xa180, 1 << 5);
 100                 gtt_write(0xa188, 0xffff0001);
 101                 if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
 102                         return;
 103         }
 104
 105         if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
 106                 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
 107                 reg32 = gtt_read(0x42004);
 108                 reg32 |= (1 << 14) | (1 << 15);
 109                 gtt_write(0x42004, reg32);
 110         }
 111
 112         if (bridge_silicon_revision() >= IVB_STEP_A0) {
 113                 /* Display Reset Acknowledge Settings */
 114                 gtt_write(0xa18c, 0x00000001);
 115                 reg32 = gtt_read(0x45010);
 116                 reg32 |= (1 << 1) | (1 << 0);
 117                 gtt_write(0x45010, reg32);
 118         }
 119
 120         /* 2: Get GT SKU from GTT+0x911c[13] */
 121         if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
 122                 reg32 = gtt_read(0x911c);
 123                 if (reg32 & (1 << 13)) {
 124                         printk(BIOS_DEBUG, "GT1 Power Meter Weights\n");
 125                         gtt_write(0xa200, 0xcc000000);
 126                         gtt_write(0xa204, 0x07000040);
 127                         gtt_write(0xa208, 0x0000fe00);
 128                         gtt_write(0xa20c, 0x00000000);
 129                         gtt_write(0xa210, 0x17000000);
 130                         gtt_write(0xa214, 0x00000021);
 131                         gtt_write(0xa218, 0x0817fe19);
 132                         gtt_write(0xa21c, 0x00000000);
 133                         gtt_write(0xa220, 0x00000000);
 134                         gtt_write(0xa224, 0xcc000000);
 135                         gtt_write(0xa228, 0x07000040);
 136                         gtt_write(0xa22c, 0x0000fe00);
 137                         gtt_write(0xa230, 0x00000000);
 138                         gtt_write(0xa234, 0x17000000);
 139                         gtt_write(0xa238, 0x00000021);
 140                         gtt_write(0xa23c, 0x0817fe19);
 141                         gtt_write(0xa240, 0x00000000);
 142                         gtt_write(0xa244, 0x00000000);
 143                         gtt_write(0xa248, 0x8000421e);
 144                 } else {
 145                         printk(BIOS_DEBUG, "GT2 Power Meter Weights\n");
 146                         gtt_write(0xa200, 0x330000a6);
 147                         gtt_write(0xa204, 0x402d0031);
 148                         gtt_write(0xa208, 0x00165f83);
 149                         gtt_write(0xa20c, 0xf1000000);
 150                         gtt_write(0xa210, 0x00000000);
 151                         gtt_write(0xa214, 0x00160016);
 152                         gtt_write(0xa218, 0x002a002b);
 153                         gtt_write(0xa21c, 0x00000000);
 154                         gtt_write(0xa220, 0x00000000);
 155                         gtt_write(0xa224, 0x330000a6);
 156                         gtt_write(0xa228, 0x402d0031);
 157                         gtt_write(0xa22c, 0x00165f83);
 158                         gtt_write(0xa230, 0xf1000000);
 159                         gtt_write(0xa234, 0x00000000);
 160                         gtt_write(0xa238, 0x00160016);
 161                         gtt_write(0xa23c, 0x002a002b);
 162                         gtt_write(0xa240, 0x00000000);
 163                         gtt_write(0xa244, 0x00000000);
 164                         gtt_write(0xa248, 0x8000421e);
 165                 }
 166         } else {
 167                 printk(BIOS_DEBUG, "IVB GT Power Meter Weights\n");
 168                 gtt_write(0xa800, 0x00000000);
 169                 gtt_write(0xa804, 0x00023800);
 170                 gtt_write(0xa808, 0x00000902);
 171                 gtt_write(0xa80c, 0x0c002f00);
 172                 gtt_write(0xa810, 0x12000500);
 173                 gtt_write(0xa814, 0x00000000);
 174                 gtt_write(0xa818, 0x00b20000);
 175                 gtt_write(0xa81c, 0x00000002);
 176                 gtt_write(0xa820, 0x03004b02);
 177                 gtt_write(0xa824, 0x00000600);
 178                 gtt_write(0xa828, 0x07000773);
 179                 gtt_write(0xa82c, 0x00000000);
 180                 gtt_write(0xa830, 0x00010000);
 181                 gtt_write(0xa834, 0x0510020d);
 182                 gtt_write(0xa838, 0x00020100);
 183                 gtt_write(0xa83c, 0x00103700);
 184                 gtt_write(0xa840, 0x0000001d);
 185                 gtt_write(0xa844, 0x00000000);
 186                 gtt_write(0xa848, 0x20001b00);
 187                 gtt_write(0xa84c, 0x0a000010);
 188                 gtt_write(0xa850, 0x00000000);
 189                 gtt_write(0xa854, 0x00000008);
 190                 gtt_write(0xa858, 0x00000000);
 191                 gtt_write(0xa85c, 0x00000000);
 192                 gtt_write(0xa860, 0x00040000);
 193                 gtt_write(0xa248, 0x0000221e);
 194                 gtt_write(0xa900, 0x00000000);
 195                 gtt_write(0xa904, 0x00003500);
 196                 gtt_write(0xa908, 0x00000000);
 197                 gtt_write(0xa90c, 0x0c000000);
 198                 gtt_write(0xa910, 0x12000500);
 199                 gtt_write(0xa914, 0x00000000);
 200                 gtt_write(0xa918, 0x00b20000);
 201                 gtt_write(0xa91c, 0x00000000);
 202                 gtt_write(0xa920, 0x08004b02);
 203                 gtt_write(0xa924, 0x00000400);
 204                 gtt_write(0xa928, 0x07000820);
 205                 gtt_write(0xa92c, 0x00000000);
 206                 gtt_write(0xa930, 0x00030000);
 207                 gtt_write(0xa934, 0x050f020d);
 208                 gtt_write(0xa938, 0x00020300);
 209                 gtt_write(0xa93c, 0x00903900);
 210                 gtt_write(0xa940, 0x00000000);
 211                 gtt_write(0xa944, 0x00000000);
 212                 gtt_write(0xa948, 0x20001b00);
 213                 gtt_write(0xa94c, 0x0a000010);
 214                 gtt_write(0xa950, 0x00000000);
 215                 gtt_write(0xa954, 0x00000008);
 216                 gtt_write(0xa960, 0x00110000);
 217                 gtt_write(0xaa3c, 0x00003900);
 218                 gtt_write(0xaa54, 0x00000008);
 219                 gtt_write(0xaa60, 0x00110000);
 220         }
 221
 222         /* 3: Gear ratio map */
 223         gtt_write(0xa004, 0x00000010);
 224
 225         /* 4: GFXPAUSE */
 226         gtt_write(0xa000, 0x00070020);
 227
 228         /* 5: Dynamic EU trip control */
 229         gtt_write(0xa080, 0x00000004);
 230
 231         /* 6: ECO bits */
 232         reg32 = gtt_read(0xa180);
 233         reg32 |= (1 << 26) | (1 << 31);
 234         /* (bit 20=1 for SNB step D1+ / IVB A0+) */
 235         if (bridge_silicon_revision() >= SNB_STEP_D1)
 236                 reg32 |= (1 << 20);
 237         gtt_write(0xa180, reg32);
 238
 239         /* 6a: for SnB step D2+ only */
 240         if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
 241                 (bridge_silicon_revision() >= SNB_STEP_D2)) {
 242                 reg32 = gtt_read(0x9400);
 243                 reg32 |= (1 << 7);
 244                 gtt_write(0x9400, reg32);
 245
 246                 reg32 = gtt_read(0x941c);
 247                 reg32 &= 0xf;
 248                 reg32 |= (1 << 1);
 249                 gtt_write(0x941c, reg32);
 250                 if (!gtt_poll(0x941c, (1 << 1), (0 << 1)))
 251                         return;
 252         }
 253
 254         if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
 255                 reg32 = gtt_read(0x907c);
 256                 reg32 |= (1 << 16);
 257                 gtt_write(0x907c, reg32);
 258
 259                 /* 6b: Clocking reset controls */
 260                 gtt_write(0x9424, 0x00000001);
 261         } else {
 262                 /* 6b: Clocking reset controls */
 263                 gtt_write(0x9424, 0x00000000);
 264         }
 265
 266         /* 7 */
 267         if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
 268                 return;
 269         gtt_write(0x138128, 0x00000029); /* Mailbox Data */
 270         gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
 271         if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
 272                 return;
 273         gtt_write(0x138124, 0x8000000a); /* Mailbox Cmd to clear RC6 count */
 274         if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
 275                 return;
 276
 277         /* 8 */
 278         gtt_write(0xa090, 0x00000000); /* RC Control */
 279         gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
 280         gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
 281         gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
 282         gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */
 283         gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */
 284
 285         /* 9 */
 286         gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */
 287         gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */
 288         gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */
 289
 290         /* 10 */
 291         gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */
 292         gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */
 293         gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */
 294         gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */
 295         gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */
 296
 297         /* 11 */
 298         gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */
 299         gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */
 300         gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */
 301         gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */
 302         gtt_write(0xa068, 0x000186a0); /* RP Up EI */
 303         gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
 304         gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
 305
 306         /* 11a: Enable Render Standby (RC6) */
 307         if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
 308                 /* on IVB: also enable DeepRenderStandby */
 309                 gtt_write(0xa090, 0x88060000); /* HW RC Control */
 310         } else {
 311                 gtt_write(0xa090, 0x88040000); /* HW RC Control */
 312         }
 313
 314         /* 12: Normal Frequency Request */
 315         /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
 316         reg32 = MCHBAR32(0x5998);
 317         reg32 >>= 16;
 318         reg32 &= 0xef;
 319         reg32 <<= 25;
 320         gtt_write(0xa008, reg32);
 321
 322         /* 13: RP Control */
 323         gtt_write(0xa024, 0x00000592);
 324
 325         /* 14: Enable PM Interrupts */
 326         gtt_write(0x4402c, 0x03000076);
 327
 328         /* Clear 0x6c024 [8:6] */
 329         reg32 = gtt_read(0x6c024);
 330         reg32 &= ~0x000001c0;
 331         gtt_write(0x6c024, reg32);
 332 }
 333
 334 static void gma_pm_init_post_vbios(struct device *dev)
 335 {
 336         struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
 337         u32 reg32;
 338
 339         printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
 340
 341         /* 15: Deassert Force Wake */
 342         gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
 343         if (!gtt_poll(0x130090, (1 << 0), (0 << 0)))
 344                 return;
 345
 346         /* 16: SW RC Control */
 347         gtt_write(0xa094, 0x00060000);
 348
 349         /* Setup Digital Port Hotplug */
 350         reg32 = gtt_read(0xc4030);
 351         if (!reg32) {
 352                 reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
 353                 reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
 354                 reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
 355                 gtt_write(0xc4030, reg32);
 356         }
 357
 358         /* Setup Panel Power On Delays */
 359         reg32 = gtt_read(0xc7208);
 360         if (!reg32) {
 361                 reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
 362                 reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
 363                 reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
 364                 gtt_write(0xc7208, reg32);
 365         }
 366
 367         /* Setup Panel Power Off Delays */
 368         reg32 = gtt_read(0xc720c);
 369         if (!reg32) {
 370                 reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
 371                 reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
 372                 gtt_write(0xc720c, reg32);
 373         }
 374
 375         /* Setup Panel Power Cycle Delay */
 376         if (conf->gpu_panel_power_cycle_delay) {
 377                 reg32 = gtt_read(0xc7210);
 378                 reg32 &= ~0xff;
 379                 reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
 380                 gtt_write(0xc7210, reg32);
 381         }
 382 }
 383
 384 static void gma_func0_init(struct device *dev)
 385 {
 386         u32 reg32;
 387
 388         /* IGD needs to be Bus Master */
 389         reg32 = pci_read_config32(dev, PCI_COMMAND);
 390         reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
 391         pci_write_config32(dev, PCI_COMMAND, reg32);
 392
 393         /* Init graphics power management */
 394         gma_pm_init_pre_vbios(dev);
 395
 396         /* PCI Init, will run VBIOS */
 397         pci_dev_init(dev);
 398
 399         /* Post VBIOS init */
 400         gma_pm_init_post_vbios(dev);
 401 }
 402
 403 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 404 {
 405         if (!vendor || !device) {
 406                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 407                                 pci_read_config32(dev, PCI_VENDOR_ID));
 408         } else {
 409                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 410                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 411         }
 412 }
 413
 414 static struct pci_operations gma_pci_ops = {
 415         .set_subsystem    = gma_set_subsystem,
 416 };
 417
 418 static struct device_operations gma_func0_ops = {
 419         .read_resources         = pci_dev_read_resources,
 420         .set_resources          = pci_dev_set_resources,
 421         .enable_resources       = pci_dev_enable_resources,
 422         .init                   = gma_func0_init,
 423         .scan_bus               = 0,
 424         .enable                 = 0,
 425         .ops_pci                = &gma_pci_ops,
 426 };
 427
 428 static const struct pci_driver gma_gt1_desktop __pci_driver = {
 429         .ops    = &gma_func0_ops,
 430         .vendor = PCI_VENDOR_ID_INTEL,
 431         .device = 0x0102,
 432 };
 433
 434 static const struct pci_driver gma_gt1_mobile __pci_driver = {
 435         .ops    = &gma_func0_ops,
 436         .vendor = PCI_VENDOR_ID_INTEL,
 437         .device = 0x0106,
 438 };
 439
 440 static const struct pci_driver gma_gt1_server __pci_driver = {
 441         .ops    = &gma_func0_ops,
 442         .vendor = PCI_VENDOR_ID_INTEL,
 443         .device = 0x010a,
 444 };
 445
 446 static const struct pci_driver gma_gt2_desktop __pci_driver = {
 447         .ops    = &gma_func0_ops,
 448         .vendor = PCI_VENDOR_ID_INTEL,
 449         .device = 0x0112,
 450 };
 451
 452 static const struct pci_driver gma_gt2_mobile __pci_driver = {
 453         .ops    = &gma_func0_ops,
 454         .vendor = PCI_VENDOR_ID_INTEL,
 455         .device = 0x0116,
 456 };
 457
 458 static const struct pci_driver gma_gt2_desktop_fast __pci_driver = {
 459         .ops    = &gma_func0_ops,
 460         .vendor = PCI_VENDOR_ID_INTEL,
 461         .device = 0x0122,
 462 };
 463
 464 static const struct pci_driver gma_gt2_mobile_fast __pci_driver = {
 465         .ops    = &gma_func0_ops,
 466         .vendor = PCI_VENDOR_ID_INTEL,
 467         .device = 0x0126,
 468 };
 469
 470 static const struct pci_driver gma_func0_driver_3 __pci_driver = {
 471         .ops    = &gma_func0_ops,
 472         .vendor = PCI_VENDOR_ID_INTEL,
 473         .device = 0x0166,
 474 };