src/northbridge/intel/sandybridge/acpi/hostbridge.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22
  23 Name(_HID,EISAID("PNP0A08"))    // PCIe
  24 Name(_CID,EISAID("PNP0A03"))    // PCI
  25
  26 Name(_ADR, 0)
  27 Name(_BBN, 0)
  28
  29 Device (MCHC)
  30 {
  31         Name(_ADR, 0x00000000)  // 0:0.0
  32
  33         OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
  34         Field (MCHP, DWordAcc, NoLock, Preserve)
  35         {
  36                 Offset (0x40),  // EPBAR
  37                 EPEN,    1,     // Enable
  38                 ,       11,     //
  39                 EPBR,   24,     // EPBAR
  40
  41                 Offset (0x48),  // MCHBAR
  42                 MHEN,    1,     // Enable
  43                 ,       13,     //
  44                 MHBR,   22,     // MCHBAR
  45
  46                 Offset (0x60),  // PCIe BAR
  47                 PXEN,    1,     // Enable
  48                 PXSZ,    2,     // BAR size
  49                 ,       23,     //
  50                 PXBR,   10,     // PCIe BAR
  51
  52                 Offset (0x68),  // DMIBAR
  53                 DMEN,    1,     // Enable
  54                 ,       11,     //
  55                 DMBR,   24,     // DMIBAR
  56
  57                 Offset (0x70),  // ME Base Address
  58                 MEBA,    64,
  59
  60                 // ...
  61
  62                 Offset (0x80),  // PAM0
  63                 ,        4,
  64                 PM0H,    2,
  65                 ,        2,
  66                 Offset (0x81),  // PAM1
  67                 PM1L,    2,
  68                 ,        2,
  69                 PM1H,    2,
  70                 ,        2,
  71                 Offset (0x82),  // PAM2
  72                 PM2L,    2,
  73                 ,        2,
  74                 PM2H,    2,
  75                 ,        2,
  76                 Offset (0x83),  // PAM3
  77                 PM3L,    2,
  78                 ,        2,
  79                 PM3H,    2,
  80                 ,        2,
  81                 Offset (0x84),  // PAM4
  82                 PM4L,    2,
  83                 ,        2,
  84                 PM4H,    2,
  85                 ,        2,
  86                 Offset (0x85),  // PAM5
  87                 PM5L,    2,
  88                 ,        2,
  89                 PM5H,    2,
  90                 ,        2,
  91                 Offset (0x86),  // PAM6
  92                 PM6L,    2,
  93                 ,        2,
  94                 PM6H,    2,
  95                 ,        2,
  96
  97                 Offset (0xa0),  // Top of Used Memory
  98                 TOM,     64,
  99
 100                 Offset (0xbc),  // Top of Low Used Memory
 101                 TLUD,    32,
 102         }
 103
 104 }
 105
 106
 107 // Current Resource Settings
 108
 109 Method (_CRS, 0, Serialized)
 110 {
 111         Name (MCRS, ResourceTemplate()
 112         {
 113                 // Bus Numbers
 114                 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 115                                 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 116
 117                 // IO Region 0
 118                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 119                                 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 120
 121                 // PCI Config Space
 122                 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 123
 124                 // IO Region 1
 125                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 126                                 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 127
 128                 // VGA memory (0xa0000-0xbffff)
 129                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 130                                 Cacheable, ReadWrite,
 131                                 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
 132                                 0x00020000,,, ASEG)
 133
 134                 // OPROM reserved (0xc0000-0xc3fff)
 135                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 136                                 Cacheable, ReadWrite,
 137                                 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
 138                                 0x00004000,,, OPR0)
 139
 140                 // OPROM reserved (0xc4000-0xc7fff)
 141                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 142                                 Cacheable, ReadWrite,
 143                                 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
 144                                 0x00004000,,, OPR1)
 145
 146                 // OPROM reserved (0xc8000-0xcbfff)
 147                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 148                                 Cacheable, ReadWrite,
 149                                 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
 150                                 0x00004000,,, OPR2)
 151
 152                 // OPROM reserved (0xcc000-0xcffff)
 153                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 154                                 Cacheable, ReadWrite,
 155                                 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
 156                                 0x00004000,,, OPR3)
 157
 158                 // OPROM reserved (0xd0000-0xd3fff)
 159                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 160                                 Cacheable, ReadWrite,
 161                                 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
 162                                 0x00004000,,, OPR4)
 163
 164                 // OPROM reserved (0xd4000-0xd7fff)
 165                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 166                                 Cacheable, ReadWrite,
 167                                 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
 168                                 0x00004000,,, OPR5)
 169
 170                 // OPROM reserved (0xd8000-0xdbfff)
 171                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 172                                 Cacheable, ReadWrite,
 173                                 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
 174                                 0x00004000,,, OPR6)
 175
 176                 // OPROM reserved (0xdc000-0xdffff)
 177                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 178                                 Cacheable, ReadWrite,
 179                                 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 180                                 0x00004000,,, OPR7)
 181
 182                 // BIOS Extension (0xe0000-0xe3fff)
 183                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 184                                 Cacheable, ReadWrite,
 185                                 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
 186                                 0x00004000,,, ESG0)
 187
 188                 // BIOS Extension (0xe4000-0xe7fff)
 189                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 190                                 Cacheable, ReadWrite,
 191                                 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
 192                                 0x00004000,,, ESG1)
 193
 194                 // BIOS Extension (0xe8000-0xebfff)
 195                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 196                                 Cacheable, ReadWrite,
 197                                 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
 198                                 0x00004000,,, ESG2)
 199
 200                 // BIOS Extension (0xec000-0xeffff)
 201                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 202                                 Cacheable, ReadWrite,
 203                                 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
 204                                 0x00004000,,, ESG3)
 205
 206                 // System BIOS (0xf0000-0xfffff)
 207                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 208                                 Cacheable, ReadWrite,
 209                                 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 210                                 0x00010000,,, FSEG)
 211
 212                 // PCI Memory Region (Top of memory-0xfebfffff)
 213                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 214                                 Cacheable, ReadWrite,
 215                                 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
 216                                 0xfec00000,,, PM01)
 217
 218                 // TPM Area (0xfed40000-0xfed44fff)
 219                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 220                                 Cacheable, ReadWrite,
 221                                 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
 222                                 0x00005000,,, TPMR)
 223         })
 224
 225         // Find PCI resource area in MCRS
 226         CreateDwordField(MCRS, PM01._MIN, PMIN)
 227         CreateDwordField(MCRS, PM01._MAX, PMAX)
 228         CreateDwordField(MCRS, PM01._LEN, PLEN)
 229
 230         // Fix up PCI memory region
 231         // Start with Top of Lower Usable DRAM
 232         Store (^MCHC.TLUD, Local0)
 233         Store (^MCHC.MEBA, Local1)
 234
 235         // Check if ME base is equal
 236         If (LEqual (Local0, Local1)) {
 237                 // Use Top Of Memory instead
 238                 Store (^MCHC.TOM, Local0)
 239         }
 240
 241         Store (Local0, PMIN)
 242         Add(Subtract(PMAX, PMIN), 1, PLEN)
 243
 244         Return (MCRS)
 245 }
 246
 247 /* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
 248 #include "acpi/sandybridge_pci_irqs.asl"
 249
 250