2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82945GM:
37 case PCI_DEVICE_ID_INTEL_82945P:
38 case PCI_DEVICE_ID_INTEL_82975X:
39 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
41 case PCI_DEVICE_ID_INTEL_PM965:
42 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
43 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
45 case PCI_DEVICE_ID_INTEL_82810:
46 case PCI_DEVICE_ID_INTEL_82810DC:
47 printf("This northbrigde does not have EPBAR.\n");
50 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
54 epbar = map_physical(epbar_phys, size);
57 perror("Error mapping EPBAR");
61 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
62 for (i = 0; i < size; i += 4) {
63 if (*(uint32_t *)(epbar + i))
64 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
67 unmap_physical((void *)epbar, size);
72 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
74 int print_dmibar(struct pci_dev *nb)
76 int i, size = (4 * 1024);
77 volatile uint8_t *dmibar;
80 printf("\n============= DMIBAR ============\n\n");
82 switch (nb->device_id) {
83 case PCI_DEVICE_ID_INTEL_82945GM:
84 case PCI_DEVICE_ID_INTEL_82945P:
85 case PCI_DEVICE_ID_INTEL_82975X:
86 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
88 case PCI_DEVICE_ID_INTEL_PM965:
89 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
90 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
92 case PCI_DEVICE_ID_INTEL_82810:
93 case PCI_DEVICE_ID_INTEL_82810DC:
94 printf("This northbrigde does not have DMIBAR.\n");
97 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
101 dmibar = map_physical(dmibar_phys, size);
103 if (dmibar == NULL) {
104 perror("Error mapping DMIBAR");
108 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
109 for (i = 0; i < size; i += 4) {
110 if (*(uint32_t *)(dmibar + i))
111 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
114 unmap_physical((void *)dmibar, size);
119 * PCIe MMIO configuration space
121 int print_pciexbar(struct pci_dev *nb)
123 uint64_t pciexbar_reg;
124 uint64_t pciexbar_phys;
125 volatile uint8_t *pciexbar;
126 int max_busses, devbase, i;
129 printf("========= PCIEXBAR ========\n\n");
131 switch (nb->device_id) {
132 case PCI_DEVICE_ID_INTEL_82945GM:
133 case PCI_DEVICE_ID_INTEL_82945P:
134 case PCI_DEVICE_ID_INTEL_82975X:
135 pciexbar_reg = pci_read_long(nb, 0x48);
137 case PCI_DEVICE_ID_INTEL_PM965:
138 pciexbar_reg = pci_read_long(nb, 0x60);
139 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
141 case PCI_DEVICE_ID_INTEL_82810:
142 case PCI_DEVICE_ID_INTEL_82810DC:
143 printf("Error: This northbrigde does not have PCIEXBAR.\n");
146 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
150 if (!(pciexbar_reg & (1 << 0))) {
151 printf("PCIEXBAR register is disabled.\n");
155 switch ((pciexbar_reg >> 1) & 3) {
157 pciexbar_phys = pciexbar_reg & (0xff << 28);
161 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
165 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
169 printf("Undefined address base. Bailing out.\n");
173 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
175 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
177 if (pciexbar == NULL) {
178 perror("Error mapping PCIEXBAR");
182 for (bus = 0; bus < max_busses; bus++) {
183 for (dev = 0; dev < 32; dev++) {
184 for (fn = 0; fn < 8; fn++) {
185 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
187 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
190 /* This is a heuristics. Anyone got a better check? */
191 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
192 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
194 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
199 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
200 for (i = 0; i < 4096; i++) {
202 printf("\n%04x:", i);
203 printf(" %02x", *(pciexbar+devbase+i));
210 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));