add i810 and ich0
authorStefan Reinauer <stepan@coresystems.de>
Sat, 29 Aug 2009 15:45:43 +0000 (15:45 +0000)
committerStefan Reinauer <stepan@openbios.org>
Sat, 29 Aug 2009 15:45:43 +0000 (15:45 +0000)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

util/inteltool/inteltool.c
util/inteltool/inteltool.h
util/inteltool/memory.c
util/inteltool/pcie.c
util/inteltool/powermgt.c

index b1f7f05bffd690a22fb1f5e5d2026429cffe0c86..04b0a9d87f0a9601dac4545f06fda501ec7c19ff 100644 (file)
@@ -29,6 +29,8 @@ static const struct {
        uint16_t vendor_id, device_id;
        char *name;
 } supported_chips_list[] = {
+       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
+       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
index b3b10430c94a4080693dca68ba0648da86975714..391cd55d1d1179c4a7d0ae164be6170946896600 100644 (file)
@@ -44,6 +44,8 @@
 #define PCI_DEVICE_ID_INTEL_ICH8M      0x2815
 #define PCI_DEVICE_ID_INTEL_ICH10R     0x3a16
 
+#define PCI_DEVICE_ID_INTEL_82810      0x7120
+#define PCI_DEVICE_ID_INTEL_82810DC    0x7122
 #define PCI_DEVICE_ID_INTEL_82845      0x1a30
 #define PCI_DEVICE_ID_INTEL_82945P     0x2770
 #define PCI_DEVICE_ID_INTEL_82945GM    0x27a0
index 049ce828b7dea4bed51e8e1dcd4e5ae9cf2989b9..a2060cbed07c747a354e840eddf243f57c3576cf 100644 (file)
@@ -43,7 +43,8 @@ int print_mchbar(struct pci_dev *nb)
                mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
                mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
                break;
-       case 0x1234: // Dummy for non-existent functionality
+       case PCI_DEVICE_ID_INTEL_82810:
+       case PCI_DEVICE_ID_INTEL_82810DC:
                printf("This northbrigde does not have MCHBAR.\n");
                return 1;
        default:
index 86ccf69119f75147a5b81b6c5df64b2fa16a8c13..3a31ae47176a5a1cc6e42167d3e64a763f9375a4 100644 (file)
@@ -42,7 +42,8 @@ int print_epbar(struct pci_dev *nb)
                epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
                epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
                break;
-       case 0x1234: // Dummy for non-existent functionality
+       case PCI_DEVICE_ID_INTEL_82810:
+       case PCI_DEVICE_ID_INTEL_82810DC:
                printf("This northbrigde does not have EPBAR.\n");
                return 1;
        default:
@@ -88,7 +89,8 @@ int print_dmibar(struct pci_dev *nb)
                dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
                dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
                break;
-       case 0x1234: // Dummy for non-existent functionality
+       case PCI_DEVICE_ID_INTEL_82810:
+       case PCI_DEVICE_ID_INTEL_82810DC:
                printf("This northbrigde does not have DMIBAR.\n");
                return 1;
        default:
@@ -136,7 +138,8 @@ int print_pciexbar(struct pci_dev *nb)
                pciexbar_reg = pci_read_long(nb, 0x60);
                pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
                break;
-       case 0x1234: // Dummy for non-existent functionality
+       case PCI_DEVICE_ID_INTEL_82810:
+       case PCI_DEVICE_ID_INTEL_82810DC:
                printf("Error: This northbrigde does not have PCIEXBAR.\n");
                return 1;
        default:
index e985d6b3eb5b19e87c827df9a882b36fb5e61a89..5dd651ba12be4c509875fb96d612cdc3fdf8bbb7 100644 (file)
@@ -145,6 +145,64 @@ static const io_register_t ich8_pm_registers[] = {
        { 0x7c, 4, "RESERVED" },
 };
 
+static const io_register_t ich0_pm_registers[] = {
+       { 0x00, 2, "PM1_STS" },
+       { 0x02, 2, "PM1_EN" },
+       { 0x04, 4, "PM1_CNT" },
+       { 0x08, 4, "PM1_TMR" },
+       { 0x0c, 4, "RESERVED" },
+       { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+       /* This register returns 0 on read, but reading it may cause
+        * the system to enter C2 state, which might hang the system.
+        */
+       { 0x14, 1, "LV2" },
+       { 0x15, 1, "RESERVED" },
+       { 0x16, 2, "RESERVED" },
+#endif
+       { 0x18, 4, "RESERVED" },
+       { 0x1c, 4, "RESERVED" },
+       { 0x20, 4, "RESERVED" },
+       { 0x24, 4, "RESERVED" },
+       { 0x28, 4, "GPE0_STS" },
+       { 0x2C, 4, "GPE0_EN" },
+       { 0x30, 2, "SMI_EN" },
+       { 0x32, 2, "RESERVED" },
+       { 0x34, 2, "SMI_STS" },
+       { 0x36, 2, "RESERVED" },
+       { 0x38, 4, "RESERVED" },
+       { 0x3c, 4, "RESERVED" },
+       { 0x40, 2, "IOMON_STS_EN" },
+       { 0x42, 2, "RESERVED" },
+       { 0x44, 2, "DEVACT_STS" },
+       { 0x46, 2, "RESERVED" },
+       { 0x48, 4, "RESERVED" },
+       { 0x4c, 2, "BUS_ADDR_TRACK" },
+       { 0x4e, 1, "BUS_CYC_TRACK" },
+       { 0x4f, 1, "RESERVED" },
+       { 0x50, 4, "RESERVED" },
+       { 0x54, 4, "RESERVED" },
+       { 0x58, 4, "RESERVED" },
+       { 0x5c, 4, "RESERVED" },
+       /* Here start the TCO registers */
+       { 0x60, 1, "TCO_RLD" },
+       { 0x61, 1, "TCO_TMR" },
+       { 0x62, 1, "TCO_DAT_IN" },
+       { 0x63, 1, "TCO_DAT_OUT" },
+       { 0x64, 2, "TCO1_STS" },
+       { 0x66, 2, "TCO2_STS" },
+       { 0x68, 2, "TCO1_CNT" },
+       { 0x6a, 2, "TCO2_CNT" },
+       { 0x6c, 1, "TCO_MESSAGE1" },
+       { 0x6d, 1, "TCO_MESSAGE2" },
+       { 0x6e, 1, "TCO_WDSTATUS" },
+       { 0x6f, 1, "RESERVED" },
+       { 0x70, 4, "RESERVED" },
+       { 0x74, 4, "RESERVED" },
+       { 0x78, 4, "RESERVED" },
+       { 0x7c, 4, "RESERVED" },
+};
+
 int print_pmbase(struct pci_dev *sb)
 {
        int i, size;
@@ -167,6 +225,11 @@ int print_pmbase(struct pci_dev *sb)
                pm_registers = ich8_pm_registers;
                size = ARRAY_SIZE(ich8_pm_registers);
                break;
+       case PCI_DEVICE_ID_INTEL_ICH0:
+               pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+               pm_registers = ich0_pm_registers;
+               size = ARRAY_SIZE(ich0_pm_registers);
+               break;
        case 0x1234: // Dummy for non-existent functionality
                printf("This southbridge does not have PMBASE.\n");
                return 1;