2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82945GM:
37 case PCI_DEVICE_ID_INTEL_82945P:
38 case PCI_DEVICE_ID_INTEL_82975X:
39 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
41 case PCI_DEVICE_ID_INTEL_PM965:
42 case PCI_DEVICE_ID_INTEL_82Q35:
43 case PCI_DEVICE_ID_INTEL_82G33:
44 case PCI_DEVICE_ID_INTEL_82Q33:
45 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
46 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
48 case PCI_DEVICE_ID_INTEL_82810:
49 case PCI_DEVICE_ID_INTEL_82810DC:
50 printf("This northbrigde does not have EPBAR.\n");
53 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
57 epbar = map_physical(epbar_phys, size);
60 perror("Error mapping EPBAR");
64 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
65 for (i = 0; i < size; i += 4) {
66 if (*(uint32_t *)(epbar + i))
67 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
70 unmap_physical((void *)epbar, size);
75 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
77 int print_dmibar(struct pci_dev *nb)
79 int i, size = (4 * 1024);
80 volatile uint8_t *dmibar;
83 printf("\n============= DMIBAR ============\n\n");
85 switch (nb->device_id) {
86 case PCI_DEVICE_ID_INTEL_82945GM:
87 case PCI_DEVICE_ID_INTEL_82945P:
88 case PCI_DEVICE_ID_INTEL_82975X:
89 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
91 case PCI_DEVICE_ID_INTEL_PM965:
92 case PCI_DEVICE_ID_INTEL_82Q35:
93 case PCI_DEVICE_ID_INTEL_82G33:
94 case PCI_DEVICE_ID_INTEL_82Q33:
95 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
96 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
98 case PCI_DEVICE_ID_INTEL_82810:
99 case PCI_DEVICE_ID_INTEL_82810DC:
100 printf("This northbrigde does not have DMIBAR.\n");
103 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
107 dmibar = map_physical(dmibar_phys, size);
109 if (dmibar == NULL) {
110 perror("Error mapping DMIBAR");
114 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
115 for (i = 0; i < size; i += 4) {
116 if (*(uint32_t *)(dmibar + i))
117 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
120 unmap_physical((void *)dmibar, size);
125 * PCIe MMIO configuration space
127 int print_pciexbar(struct pci_dev *nb)
129 uint64_t pciexbar_reg;
130 uint64_t pciexbar_phys;
131 volatile uint8_t *pciexbar;
132 int max_busses, devbase, i;
135 printf("========= PCIEXBAR ========\n\n");
137 switch (nb->device_id) {
138 case PCI_DEVICE_ID_INTEL_82945GM:
139 case PCI_DEVICE_ID_INTEL_82945P:
140 case PCI_DEVICE_ID_INTEL_82975X:
141 pciexbar_reg = pci_read_long(nb, 0x48);
143 case PCI_DEVICE_ID_INTEL_PM965:
144 case PCI_DEVICE_ID_INTEL_82Q35:
145 case PCI_DEVICE_ID_INTEL_82G33:
146 case PCI_DEVICE_ID_INTEL_82Q33:
147 pciexbar_reg = pci_read_long(nb, 0x60);
148 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
150 case PCI_DEVICE_ID_INTEL_82810:
151 case PCI_DEVICE_ID_INTEL_82810DC:
152 printf("Error: This northbrigde does not have PCIEXBAR.\n");
155 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
159 if (!(pciexbar_reg & (1 << 0))) {
160 printf("PCIEXBAR register is disabled.\n");
164 switch ((pciexbar_reg >> 1) & 3) {
166 pciexbar_phys = pciexbar_reg & (0xff << 28);
170 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
174 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
178 printf("Undefined address base. Bailing out.\n");
182 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
184 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
186 if (pciexbar == NULL) {
187 perror("Error mapping PCIEXBAR");
191 for (bus = 0; bus < max_busses; bus++) {
192 for (dev = 0; dev < 32; dev++) {
193 for (fn = 0; fn < 8; fn++) {
194 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
196 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
199 /* This is a heuristics. Anyone got a better check? */
200 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
201 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
203 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
208 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
209 for (i = 0; i < 4096; i++) {
211 printf("\n%04x:", i);
212 printf(" %02x", *(pciexbar+devbase+i));
219 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));