Add 82Q35/P35/Q33/G33/G31/P31 support to inteltool.
authorLoïc Grenié <loic.grenie@gmail.com>
Mon, 2 Nov 2009 15:01:49 +0000 (15:01 +0000)
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Mon, 2 Nov 2009 15:01:49 +0000 (15:01 +0000)
The registers are (as far as I can tell) unchanged with respect to those
of the PM965.

Signed-off-by: Loïc Grenié <loic.grenie@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

util/inteltool/inteltool.c
util/inteltool/inteltool.h
util/inteltool/memory.c
util/inteltool/pcie.c

index 6ae32ccf1ae93e419bbffb3caadcf60149752eaa..64f55e87bfa32da08b84d8e63a1a4f6fa9d051e6 100644 (file)
@@ -39,6 +39,9 @@ static const struct {
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
+       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
+       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
+       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
index b4757e53e849560a97f0d93f84130dae233ff216..8a5994dfabac3ec9ebd6963684b4367ca71a3686 100644 (file)
@@ -52,6 +52,9 @@
 #define PCI_DEVICE_ID_INTEL_82945GM            0x27a0
 #define PCI_DEVICE_ID_INTEL_PM965              0x2a00
 #define PCI_DEVICE_ID_INTEL_82975X             0x277c
+#define PCI_DEVICE_ID_INTEL_82Q35              0x29b0
+#define PCI_DEVICE_ID_INTEL_82G33              0x29c0
+#define PCI_DEVICE_ID_INTEL_82Q33              0x29d0
 #define PCI_DEVICE_ID_INTEL_X58                        0x3405
 
 #define PCI_DEVICE_ID_INTEL_82443LX            0x7180
index 6792ec4eb8fb3ab242ba64ce3d52ae8f058847fc..aad16fcb3c200231bce302c87333e5c2ba16421c 100644 (file)
@@ -40,6 +40,9 @@ int print_mchbar(struct pci_dev *nb)
                mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
                break;
        case PCI_DEVICE_ID_INTEL_PM965:
+       case PCI_DEVICE_ID_INTEL_82Q35:
+       case PCI_DEVICE_ID_INTEL_82G33:
+       case PCI_DEVICE_ID_INTEL_82Q33:
                mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
                mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
                break;
index 3a31ae47176a5a1cc6e42167d3e64a763f9375a4..bcb7f96b34a1d8406af01843ac091e00d5e15a51 100644 (file)
@@ -39,6 +39,9 @@ int print_epbar(struct pci_dev *nb)
                epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
                break;
        case PCI_DEVICE_ID_INTEL_PM965:
+       case PCI_DEVICE_ID_INTEL_82Q35:
+       case PCI_DEVICE_ID_INTEL_82G33:
+       case PCI_DEVICE_ID_INTEL_82Q33:
                epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
                epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
                break;
@@ -86,6 +89,9 @@ int print_dmibar(struct pci_dev *nb)
                dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
                break;
        case PCI_DEVICE_ID_INTEL_PM965:
+       case PCI_DEVICE_ID_INTEL_82Q35:
+       case PCI_DEVICE_ID_INTEL_82G33:
+       case PCI_DEVICE_ID_INTEL_82Q33:
                dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
                dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
                break;
@@ -135,6 +141,9 @@ int print_pciexbar(struct pci_dev *nb)
                pciexbar_reg = pci_read_long(nb, 0x48);
                break;
        case PCI_DEVICE_ID_INTEL_PM965:
+       case PCI_DEVICE_ID_INTEL_82Q35:
+       case PCI_DEVICE_ID_INTEL_82G33:
+       case PCI_DEVICE_ID_INTEL_82Q33:
                pciexbar_reg = pci_read_long(nb, 0x60);
                pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
                break;