2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include "inteltool.h"
23 static const io_register_t ich0_gpio_registers[] = {
24 { 0x00, 4, "GPIO_USE_SEL" },
25 { 0x04, 4, "GP_IO_SEL" },
26 { 0x08, 4, "RESERVED" },
27 { 0x0c, 4, "GP_LVL" },
28 { 0x10, 4, "RESERVED" },
29 { 0x14, 4, "GPO_TTL" },
30 { 0x18, 4, "GPO_BLINK" },
31 { 0x1c, 4, "RESERVED" },
32 { 0x20, 4, "RESERVED" },
33 { 0x24, 4, "RESERVED" },
34 { 0x28, 4, "RESERVED" },
35 { 0x2c, 4, "GPI_INV" },
36 { 0x30, 4, "RESERVED" },
37 { 0x34, 4, "RESERVED" },
38 { 0x38, 4, "RESERVED" },
39 { 0x3C, 4, "RESERVED" }
42 static const io_register_t ich2_gpio_registers[] = {
43 { 0x00, 4, "GPIO_USE_SEL" },
44 { 0x04, 4, "GP_IO_SEL" },
45 { 0x08, 4, "RESERVED" },
46 { 0x0c, 4, "GP_LVL" },
47 { 0x10, 4, "RESERVED" },
48 { 0x14, 4, "GPO_TTL" },
49 { 0x18, 4, "GPO_BLINK" },
50 { 0x1c, 4, "RESERVED" },
51 { 0x20, 4, "RESERVED" },
52 { 0x24, 4, "RESERVED" },
53 { 0x28, 4, "RESERVED" },
54 { 0x2c, 4, "GPI_INV" },
55 { 0x30, 4, "RESERVED" },
56 { 0x34, 4, "RESERVED" },
57 { 0x38, 4, "RESERVED" },
58 { 0x3C, 4, "RESERVED" }
61 static const io_register_t ich4_gpio_registers[] = {
62 { 0x00, 4, "GPIO_USE_SEL" },
63 { 0x04, 4, "GP_IO_SEL" },
64 { 0x08, 4, "RESERVED" },
65 { 0x0c, 4, "GP_LVL" },
66 { 0x10, 4, "RESERVED" },
67 { 0x14, 4, "GPO_TTL" },
68 { 0x18, 4, "GPO_BLINK" },
69 { 0x1c, 4, "RESERVED" },
70 { 0x20, 4, "RESERVED" },
71 { 0x24, 4, "RESERVED" },
72 { 0x28, 4, "RESERVED" },
73 { 0x2c, 4, "GPI_INV" },
74 { 0x30, 4, "GPIO_USE_SEL2" },
75 { 0x34, 4, "GP_IO_SEL2" },
76 { 0x38, 4, "GP_LVL2" },
77 { 0x3C, 4, "RESERVED" }
80 static const io_register_t ich6_gpio_registers[] = {
81 { 0x00, 4, "GPIO_USE_SEL" },
82 { 0x08, 4, "RESERVED" },
83 { 0x0c, 4, "GP_LVL" },
84 { 0x10, 4, "RESERVED" },
85 { 0x14, 4, "RESERVED" },
86 { 0x18, 4, "GPO_BLINK" },
87 { 0x1c, 4, "RESERVED" },
88 { 0x20, 4, "RESERVED" },
89 { 0x24, 4, "RESERVED" },
90 { 0x28, 4, "RESERVED" },
91 { 0x2c, 4, "GPI_INV" },
92 { 0x30, 4, "GPIO_USE_SEL2" },
93 { 0x34, 4, "GP_IO_SEL2" },
94 { 0x38, 4, "GP_LVL2" },
95 { 0x04, 4, "GP_IO_SEL" },
98 static const io_register_t ich7_gpio_registers[] = {
99 { 0x00, 4, "GPIO_USE_SEL" },
100 { 0x04, 4, "GP_IO_SEL" },
101 { 0x08, 4, "RESERVED" },
102 { 0x0c, 4, "GP_LVL" },
103 { 0x10, 4, "RESERVED" },
104 { 0x14, 4, "RESERVED" },
105 { 0x18, 4, "GPO_BLINK" },
106 { 0x1c, 4, "RESERVED" },
107 { 0x20, 4, "RESERVED" },
108 { 0x24, 4, "RESERVED" },
109 { 0x28, 4, "RESERVED" },
110 { 0x2c, 4, "GPI_INV" },
111 { 0x30, 4, "GPIO_USE_SEL2" },
112 { 0x34, 4, "GP_IO_SEL2" },
113 { 0x38, 4, "GP_LVL2" },
114 { 0x3C, 4, "RESERVED" }
117 static const io_register_t ich8_gpio_registers[] = {
118 { 0x00, 4, "GPIO_USE_SEL" },
119 { 0x04, 4, "GP_IO_SEL" },
120 { 0x08, 4, "RESERVED" },
121 { 0x0c, 4, "GP_LVL" },
122 { 0x10, 4, "GPIO_USE_SEL Override (LOW)" },
123 { 0x14, 4, "RESERVED" },
124 { 0x18, 4, "GPO_BLINK" },
125 { 0x1c, 4, "GP_SER_BLINK" },
126 { 0x20, 4, "GP_SB_CMDSTS" },
127 { 0x24, 4, "GP_SB_DATA" },
128 { 0x28, 4, "RESERVED" },
129 { 0x2c, 4, "GPI_INV" },
130 { 0x30, 4, "GPIO_USE_SEL2" },
131 { 0x34, 4, "GP_IO_SEL2" },
132 { 0x38, 4, "GP_LVL2" },
133 { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
136 static const io_register_t ich9_gpio_registers[] = {
137 { 0x00, 4, "GPIO_USE_SEL" },
138 { 0x04, 4, "GP_IO_SEL" },
139 { 0x08, 4, "RESERVED" },
140 { 0x0c, 4, "GP_LVL" },
141 { 0x10, 4, "RESERVED" },
142 { 0x14, 4, "RESERVED" },
143 { 0x18, 4, "GPO_BLINK" },
144 { 0x1c, 4, "GP_SER_BLINK" },
145 { 0x20, 4, "GP_SB_CMDSTS" },
146 { 0x24, 4, "GP_SB_DATA" },
147 { 0x28, 4, "RESERVED" },
148 { 0x2c, 4, "GPI_INV" },
149 { 0x30, 4, "GPIO_USE_SEL2" },
150 { 0x34, 4, "GP_IO_SEL2" },
151 { 0x38, 4, "GP_LVL2" },
152 { 0x3C, 4, "RESERVED" }
155 int print_gpios(struct pci_dev *sb)
159 const io_register_t *gpio_registers;
161 printf("\n============= GPIOS =============\n\n");
163 switch (sb->device_id) {
164 case PCI_DEVICE_ID_INTEL_ICH9DH:
165 case PCI_DEVICE_ID_INTEL_ICH9DO:
166 case PCI_DEVICE_ID_INTEL_ICH9R:
167 case PCI_DEVICE_ID_INTEL_ICH9:
168 case PCI_DEVICE_ID_INTEL_ICH9M:
169 case PCI_DEVICE_ID_INTEL_ICH9ME:
170 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
171 gpio_registers = ich9_gpio_registers;
172 size = ARRAY_SIZE(ich9_gpio_registers);
174 case PCI_DEVICE_ID_INTEL_ICH8M:
175 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
176 gpio_registers = ich8_gpio_registers;
177 size = ARRAY_SIZE(ich8_gpio_registers);
179 case PCI_DEVICE_ID_INTEL_ICH7:
180 case PCI_DEVICE_ID_INTEL_ICH7M:
181 case PCI_DEVICE_ID_INTEL_ICH7DH:
182 case PCI_DEVICE_ID_INTEL_ICH7MDH:
183 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
184 gpio_registers = ich7_gpio_registers;
185 size = ARRAY_SIZE(ich7_gpio_registers);
187 case PCI_DEVICE_ID_INTEL_ICH6:
188 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
189 gpio_registers = ich6_gpio_registers;
190 size = ARRAY_SIZE(ich6_gpio_registers);
192 case PCI_DEVICE_ID_INTEL_ICH4:
193 case PCI_DEVICE_ID_INTEL_ICH4M:
194 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
195 gpio_registers = ich4_gpio_registers;
196 size = ARRAY_SIZE(ich4_gpio_registers);
198 case PCI_DEVICE_ID_INTEL_ICH2:
199 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
200 gpio_registers = ich2_gpio_registers;
201 size = ARRAY_SIZE(ich2_gpio_registers);
203 case PCI_DEVICE_ID_INTEL_ICH:
204 case PCI_DEVICE_ID_INTEL_ICH0:
205 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
206 gpio_registers = ich0_gpio_registers;
207 size = ARRAY_SIZE(ich0_gpio_registers);
209 case PCI_DEVICE_ID_INTEL_82371XX:
210 printf("This southbridge has GPIOs in the PM unit.\n");
212 case 0x1234: // Dummy for non-existent functionality
213 printf("This southbridge does not have GPIOBASE.\n");
216 printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
220 printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
222 for (i = 0; i < size; i++) {
223 switch (gpio_registers[i].size) {
225 printf("gpiobase+0x%04x: 0x%08x (%s)\n",
226 gpio_registers[i].addr,
227 inl(gpiobase+gpio_registers[i].addr),
228 gpio_registers[i].name);
231 printf("gpiobase+0x%04x: 0x%04x (%s)\n",
232 gpio_registers[i].addr,
233 inw(gpiobase+gpio_registers[i].addr),
234 gpio_registers[i].name);
237 printf("gpiobase+0x%04x: 0x%02x (%s)\n",
238 gpio_registers[i].addr,
239 inb(gpiobase+gpio_registers[i].addr),
240 gpio_registers[i].name);