This patch adds inteltool support for i810E and ICH2.
authorJoseph Smith <joe@settoplinux.org>
Wed, 16 Jun 2010 22:21:19 +0000 (22:21 +0000)
committerJoseph Smith <joe@smittys.pointclark.net>
Wed, 16 Jun 2010 22:21:19 +0000 (22:21 +0000)
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

util/inteltool/gpio.c
util/inteltool/inteltool.c
util/inteltool/inteltool.h
util/inteltool/memory.c
util/inteltool/pcie.c
util/inteltool/powermgt.c
util/inteltool/rootcmplx.c

index 4d0ced81bae3b1f8e905bcf73e107e4f46874372..a3b6e3d4a0f2d704b88c13d4f2e208625664bd73 100644 (file)
@@ -39,6 +39,25 @@ static const io_register_t ich0_gpio_registers[] = {
        { 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich2_gpio_registers[] = {
+       { 0x00, 4, "GPIO_USE_SEL" },
+       { 0x04, 4, "GP_IO_SEL" },
+       { 0x08, 4, "RESERVED" },
+       { 0x0c, 4, "GP_LVL" },
+       { 0x10, 4, "RESERVED" },
+       { 0x14, 4, "GPO_TTL" },
+       { 0x18, 4, "GPO_BLINK" },
+       { 0x1c, 4, "RESERVED" },
+       { 0x20, 4, "RESERVED" },
+       { 0x24, 4, "RESERVED" },
+       { 0x28, 4, "RESERVED" },
+       { 0x2c, 4, "GPI_INV" },
+       { 0x30, 4, "RESERVED" },
+       { 0x34, 4, "RESERVED" },
+       { 0x38, 4, "RESERVED" },
+       { 0x3C, 4, "RESERVED" }
+};
+
 static const io_register_t ich4_gpio_registers[] = {
        { 0x00, 4, "GPIO_USE_SEL" },
        { 0x04, 4, "GP_IO_SEL" },
@@ -176,6 +195,11 @@ int print_gpios(struct pci_dev *sb)
                gpio_registers = ich4_gpio_registers;
                size = ARRAY_SIZE(ich4_gpio_registers);
                break;
+       case PCI_DEVICE_ID_INTEL_ICH2:
+               gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
+               gpio_registers = ich2_gpio_registers;
+               size = ARRAY_SIZE(ich2_gpio_registers);
+               break;
        case PCI_DEVICE_ID_INTEL_ICH:
        case PCI_DEVICE_ID_INTEL_ICH0:
                gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
index 615234edaa6e856ac6e9e2dc0f502cd244edf372..236f8c80e59adc2d1f9198753ec7c48bedb41131 100644 (file)
@@ -34,6 +34,7 @@ static const struct {
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
+       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
index 613469ca45bc50c84dab17a6c14d41f869b38f49..e9a9beba84fa33dde3b84750d1523fd9a74ce5aa 100644 (file)
@@ -55,6 +55,7 @@
 
 #define PCI_DEVICE_ID_INTEL_82810              0x7120
 #define PCI_DEVICE_ID_INTEL_82810DC            0x7122
+#define PCI_DEVICE_ID_INTEL_82810E_MC          0x7124
 #define PCI_DEVICE_ID_INTEL_82830M             0x3575
 #define PCI_DEVICE_ID_INTEL_82845              0x1a30
 #define PCI_DEVICE_ID_INTEL_82915              0x2580
index 0dae58998de60c85f01f5eede11788fe5b713dd5..5c25dd0623320516fb64e7f2ff39524617797efd 100644 (file)
@@ -50,6 +50,7 @@ int print_mchbar(struct pci_dev *nb)
        case PCI_DEVICE_ID_INTEL_82443LX:
        case PCI_DEVICE_ID_INTEL_82443BX:
        case PCI_DEVICE_ID_INTEL_82810:
+       case PCI_DEVICE_ID_INTEL_82810E_MC:
        case PCI_DEVICE_ID_INTEL_82810DC:
        case PCI_DEVICE_ID_INTEL_82830M:
                printf("This northbrigde does not have MCHBAR.\n");
index cf8814299dc4b1058fd01da9f20acac0481f6f4e..771a28f2201c97b2499bcf0bf77e2164e4c44343 100644 (file)
@@ -49,6 +49,7 @@ int print_epbar(struct pci_dev *nb)
                break;
        case PCI_DEVICE_ID_INTEL_82810:
        case PCI_DEVICE_ID_INTEL_82810DC:
+       case PCI_DEVICE_ID_INTEL_82810E_MC:
        case PCI_DEVICE_ID_INTEL_82830M:
                printf("This northbrigde does not have EPBAR.\n");
                return 1;
@@ -102,6 +103,7 @@ int print_dmibar(struct pci_dev *nb)
                break;
        case PCI_DEVICE_ID_INTEL_82810:
        case PCI_DEVICE_ID_INTEL_82810DC:
+       case PCI_DEVICE_ID_INTEL_82810E_MC:
                printf("This northbrigde does not have DMIBAR.\n");
                return 1;
        default:
@@ -156,6 +158,7 @@ int print_pciexbar(struct pci_dev *nb)
                break;
        case PCI_DEVICE_ID_INTEL_82810:
        case PCI_DEVICE_ID_INTEL_82810DC:
+       case PCI_DEVICE_ID_INTEL_82810E_MC:
                printf("Error: This northbrigde does not have PCIEXBAR.\n");
                return 1;
        default:
index de28d6a6d36088fb89dafa0b61f5d23e7eecbe22..f7275843f1484b0c0fb9b1094f5ce54480726dc8 100644 (file)
@@ -299,6 +299,69 @@ static const io_register_t ich4_pm_registers[] = {
        { 0x7c, 4, "RESERVED" },
 };
 
+static const io_register_t ich2_pm_registers[] = {
+       { 0x00, 2, "PM1_STS" },
+       { 0x02, 2, "PM1_EN" },
+       { 0x04, 4, "PM1_CNT" },
+       { 0x08, 4, "PM1_TMR" },
+       { 0x0c, 4, "RESERVED" },
+       { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+       /* This register returns 0 on read, but reading it may cause
+        * the system to enter C2 state, which might hang the system.
+        */
+       { 0x14, 1, "LV2" },
+       { 0x15, 1, "RESERVED" },
+       { 0x16, 2, "RESERVED" },
+#endif
+       { 0x18, 4, "RESERVED" },
+       { 0x1c, 4, "RESERVED" },
+       { 0x20, 4, "RESERVED" },
+       { 0x24, 4, "RESERVED" },
+       { 0x28, 2, "GPE0_STS" },
+       { 0x2a, 2, "GPE0_EN" },
+       { 0x2c, 2, "GPE1_STS" },
+       { 0x2e, 2, "GPE1_EN" },
+       { 0x30, 2, "SMI_EN" },
+       { 0x32, 2, "RESERVED" },
+       { 0x34, 2, "SMI_STS" },
+       { 0x36, 2, "RESERVED" },
+       { 0x38, 4, "RESERVED" },
+       { 0x3c, 4, "RESERVED" },
+       { 0x40, 2, "MON_SMI_STS" },
+       { 0x42, 2, "RESERVED" },
+       { 0x44, 2, "DEV_TRP_STS" },
+       { 0x46, 2, "RESERVED" },
+       { 0x48, 2, "TRP_EN" },
+       { 0x4A, 2, "RESERVED" },
+       { 0x4c, 2, "BUS_ADDR_TRACK" },
+       { 0x4e, 1, "BUS_CYC_TRACK" },
+       { 0x4f, 1, "RESERVED" },
+       { 0x50, 4, "RESERVED" },
+       { 0x54, 4, "RESERVED" },
+       { 0x58, 4, "RESERVED" },
+       { 0x5c, 4, "RESERVED" },
+       /* Here start the TCO registers */
+       { 0x60, 1, "TCO_RLD" },
+       { 0x61, 1, "TCO_TMR" },
+       { 0x62, 1, "TCO_DAT_IN" },
+       { 0x63, 1, "TCO_DAT_OUT" },
+       { 0x64, 2, "TCO1_STS" },
+       { 0x66, 2, "TCO2_STS" },
+       { 0x68, 2, "TCO1_CNT" },
+       { 0x6a, 2, "TCO2_CNT" },
+       { 0x6c, 1, "TCO_MESSAGE1" },
+       { 0x6d, 1, "TCO_MESSAGE2" },
+       { 0x6e, 1, "TCO_WDSTATUS" },
+       { 0x6f, 1, "RESERVED" },
+       { 0x70, 1, "SW_IRQ_GEN" },
+       { 0x71, 1, "RESERVED" },
+       { 0x72, 2, "RESERVED" },
+       { 0x74, 4, "RESERVED" },
+       { 0x78, 4, "RESERVED" },
+       { 0x7c, 4, "RESERVED" },
+};
+
 static const io_register_t ich0_pm_registers[] = {
        { 0x00, 2, "PM1_STS" },
        { 0x02, 2, "PM1_EN" },
@@ -443,6 +506,11 @@ int print_pmbase(struct pci_dev *sb)
                pm_registers = ich4_pm_registers;
                size = ARRAY_SIZE(ich4_pm_registers);
                break;
+       case PCI_DEVICE_ID_INTEL_ICH2:
+               pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+               pm_registers = ich2_pm_registers;
+               size = ARRAY_SIZE(ich2_pm_registers);
+               break;
        case PCI_DEVICE_ID_INTEL_ICH0:
                pmbase = pci_read_word(sb, 0x40) & 0xfffc;
                pm_registers = ich0_pm_registers;
index 266ad4f0498c1104c69ab7239214cb9d8f4f7dbd..b89e6a1b6bbdd35924b79e5aaf90e9e37c1e0e39 100644 (file)
@@ -47,6 +47,7 @@ int print_rcba(struct pci_dev *sb)
                break;
        case PCI_DEVICE_ID_INTEL_ICH:
        case PCI_DEVICE_ID_INTEL_ICH0:
+       case PCI_DEVICE_ID_INTEL_ICH2:
        case PCI_DEVICE_ID_INTEL_ICH4:
        case PCI_DEVICE_ID_INTEL_ICH4M:
                printf("This southbridge does not have RCBA.\n");