src/southbridge/via/k8t890/ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ops.h>
  23 #include <device/pci_ids.h>
  24 #include <console/console.h>
  25
  26 /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  27  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  28  */
  29
  30 static void vt8237r_cfg(struct device *dev, struct device *devsb)
  31 {
  32         u8 regm, regm3;
  33
  34         device_t devfun3;
  35
  36         devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  37                                            PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
  38
  39         if (!devfun3)
  40                 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  41                                            PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
  42
  43         if (!devfun3)
  44                 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  45                                            PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
  46
  47         pci_write_config8(dev, 0x70, 0xc2);
  48
  49         /* PCI Control */
  50         pci_write_config8(dev, 0x72, 0xee);
  51         pci_write_config8(dev, 0x73, 0x01);
  52         pci_write_config8(dev, 0x74, 0x24);
  53         pci_write_config8(dev, 0x75, 0x0f);
  54         pci_write_config8(dev, 0x76, 0x50);
  55         pci_write_config8(dev, 0x77, 0x08);
  56         pci_write_config8(dev, 0x78, 0x01);
  57         /* APIC on HT */
  58         pci_write_config8(dev, 0x7c, 0x7f);
  59         pci_write_config8(dev, 0x7f, 0x02);
  60
  61         /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
  62
  63         regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */
  64         pci_write_config8(dev, 0x57, regm);
  65
  66         regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */
  67         pci_write_config8(dev, 0x61, regm);
  68
  69         regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */
  70         pci_write_config8(dev, 0x62, regm);
  71
  72         regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */
  73         pci_write_config8(dev, 0xe6, regm);
  74
  75         regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
  76
  77         /*
  78          * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
  79          * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
  80          * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
  81          */
  82         if (regm3 == 0xff)
  83                 regm3 = 0xc0;
  84         else
  85                 regm3 = 0x0;
  86
  87         /* Shadow page F + memhole copy */
  88         regm = pci_read_config8(devfun3, 0x83);
  89         pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
  90 }
  91
  92
  93
  94 /**
  95  * Setup the V-Link for VT8237R, 8X mode.
  96  *
  97  * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
  98  *
  99  *                                               REG   DEF   AW  VIA-8X VIA-4X
 100  *                                               -----------------------------
 101  * NB V-Link Manual Driving Control strobe       0xb5  0x46  0x46  0x88  0x88
 102  * NB V-Link Manual Driving Control - Data       0xb6  0x46  0x46  0x88  0x88
 103  * NB V-Link Receiving Strobe Delay              0xb7  0x02  0x02  0x61  0x01
 104  * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4  0x10  0x10  0x11  0x11
 105  * SB V-Link Strobe Drive Control                0xb9  0x00  0xa5  0x98  0x98
 106  * SB V-Link Data drive Control????              0xba  0x00  0xbb  0x77  0x77
 107  * SB V-Link Receive Strobe Delay????            0xbb  0x04  0x11  0x11  0x11
 108  * SB V-Link Compensation Control bit0 (use b9)  0xb8  0x00  0x01  0x01  0x01
 109  * V-Link CKG Control                            0xb0  0x05  0x05  0x06  0x03
 110  * V-Link CKG Control                            0xb1  0x05  0x05  0x01  0x03
 111  */
 112
 113 static void vt8237r_vlink_init(struct device *dev)
 114 {
 115         u8 reg;
 116
 117         /*
 118          * This init code is valid only for the VT8237R! For different
 119          * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
 120          * and VT8251) a different init code is required.
 121          */
 122
 123         pci_write_config8(dev, 0xb5, 0x88);
 124         pci_write_config8(dev, 0xb6, 0x88);
 125         pci_write_config8(dev, 0xb7, 0x61);
 126
 127         reg = pci_read_config8(dev, 0xb4);
 128         reg |= 0x11;
 129         pci_write_config8(dev, 0xb4, reg);
 130
 131         pci_write_config8(dev, 0xb9, 0x98);
 132         pci_write_config8(dev, 0xba, 0x77);
 133         pci_write_config8(dev, 0xbb, 0x11);
 134
 135         reg = pci_read_config8(dev, 0xb8);
 136         reg |= 0x1;
 137         pci_write_config8(dev, 0xb8, reg);
 138
 139         pci_write_config8(dev, 0xb0, 0x06);
 140         pci_write_config8(dev, 0xb1, 0x01);
 141
 142         /* Program V-link 8X 16bit full duplex, parity enabled. */
 143         pci_write_config8(dev, 0x48, 0xa3);
 144 }
 145
 146 static void ctrl_init(struct device *dev) {
 147
 148         /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
 149            should to 1 */
 150
 151         /* C2P Read ACK Return Priority */
 152         /* PCI CFG Address bits[27:24] are used as extended register address
 153            bit[11:8] */
 154
 155         pci_write_config8(dev, 0x47, 0x30);
 156
 157         /* VT8237R specific configuration  other SB are done in their own directories */
 158
 159         device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
 160                                          PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
 161         if (devsb) {
 162                 vt8237r_vlink_init(dev);
 163                 vt8237r_cfg(dev, devsb);
 164         }
 165
 166 }
 167
 168 static const struct device_operations ctrl_ops = {
 169         .read_resources         = pci_dev_read_resources,
 170         .set_resources          = pci_dev_set_resources,
 171         .enable_resources       = pci_dev_enable_resources,
 172         .init                   = ctrl_init,
 173         .ops_pci                = 0,
 174 };
 175
 176 static const struct pci_driver northbridge_driver_t __pci_driver = {
 177         .ops    = &ctrl_ops,
 178         .vendor = PCI_VENDOR_ID_VIA,
 179         .device = PCI_DEVICE_ID_VIA_K8T890CE_7,
 180 };
 181
 182 static const struct pci_driver northbridge_driver_tcf __pci_driver = {
 183         .ops    = &ctrl_ops,
 184         .vendor = PCI_VENDOR_ID_VIA,
 185         .device = PCI_DEVICE_ID_VIA_K8T890CF_7,
 186 };
 187
 188 static const struct pci_driver northbridge_driver_m __pci_driver = {
 189         .ops    = &ctrl_ops,
 190         .vendor = PCI_VENDOR_ID_VIA,
 191         .device = PCI_DEVICE_ID_VIA_K8M890CE_7,
 192 };