src/southbridge/via/k8t890/ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ops.h>
  24 #include <device/pci_ids.h>
  25 #include <console/console.h>
  26 #include "k8x8xx.h"
  27
  28 void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs)
  29 {
  30         msr_t msr;
  31
  32         regs->rom_shadow_ctrl_pg_c = 0xff;
  33         regs->rom_shadow_ctrl_pg_d = 0xff;
  34         regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff;
  35         regs->rom_shadow_ctrl_pg_f_memhole = 0x30;
  36         regs->smm_apic_decoding = 0x19;
  37         msr = rdmsr(TOP_MEM);
  38         regs->shadow_mem_ctrl = msr.lo >> 24;
  39         regs->low_top_address = msr.lo >> 16;
  40 }
  41
  42 /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  43  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  44  */
  45
  46 void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb)
  47 {
  48         u8 regm3;
  49         struct k8x8xx_vt8237_mirrored_regs mregs;
  50
  51         pci_write_config8(dev, 0x70, 0xc2);
  52
  53         /* PCI Control */
  54 #if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
  55         pci_write_config8(dev, 0x72, 0xee);
  56 #endif
  57         pci_write_config8(dev, 0x73, 0x01);
  58 #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
  59         pci_write_config8(dev, 0x74, 0x64);
  60         pci_write_config8(dev, 0x75, 0x3f);
  61 #else
  62         pci_write_config8(dev, 0x74, 0x24);
  63         pci_write_config8(dev, 0x75, 0x0f);
  64 #endif
  65         pci_write_config8(dev, 0x76, 0x50);
  66 #if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
  67         pci_write_config8(dev, 0x77, 0x08);
  68 #endif
  69         pci_write_config8(dev, 0x78, 0x01);
  70         /* APIC on HT */
  71         pci_write_config8(dev, 0x7c, 0x7f);
  72         pci_write_config8(dev, 0x7f, 0x02);
  73
  74         k8x8xx_vt8237_mirrored_regs_fill(&mregs);
  75
  76         pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl);            /* Shadow mem CTRL */
  77         pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c);       /* Shadow page C */
  78         pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d);       /* Shadow page D */
  79         pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding);          /* SMM and APIC decoding */
  80
  81         regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding;        /* Shadow page E */
  82
  83         /*
  84          * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
  85          * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
  86          * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
  87          */
  88         if (regm3 == 0xff)
  89                 regm3 = 0xc0;
  90         else
  91                 regm3 = 0x0;
  92
  93         /* Shadow page F + memhole copy */
  94         pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F));
  95
  96 }
  97
  98
  99
 100 /**
 101  * Setup the V-Link for VT8237R, 8X mode.
 102  *
 103  * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
 104  *
 105  *                                               REG   DEF   AW  VIA-8X VIA-4X
 106  *                                               -----------------------------
 107  * NB V-Link Manual Driving Control strobe       0xb5  0x46  0x46  0x88  0x88
 108  * NB V-Link Manual Driving Control - Data       0xb6  0x46  0x46  0x88  0x88
 109  * NB V-Link Receiving Strobe Delay              0xb7  0x02  0x02  0x61  0x01
 110  * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4  0x10  0x10  0x11  0x11
 111  * SB V-Link Strobe Drive Control                0xb9  0x00  0xa5  0x98  0x98
 112  * SB V-Link Data drive Control????              0xba  0x00  0xbb  0x77  0x77
 113  * SB V-Link Receive Strobe Delay????            0xbb  0x04  0x11  0x11  0x11
 114  * SB V-Link Compensation Control bit0 (use b9)  0xb8  0x00  0x01  0x01  0x01
 115  * V-Link CKG Control                            0xb0  0x05  0x05  0x06  0x03
 116  * V-Link CKG Control                            0xb1  0x05  0x05  0x01  0x03
 117  */
 118
 119 static void vt8237r_vlink_init(struct device *dev)
 120 {
 121         u8 reg;
 122
 123         /*
 124          * This init code is valid only for the VT8237R! For different
 125          * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
 126          * and VT8251) a different init code is required.
 127          */
 128
 129         pci_write_config8(dev, 0xb5, 0x88);
 130         pci_write_config8(dev, 0xb6, 0x88);
 131         pci_write_config8(dev, 0xb7, 0x61);
 132
 133         reg = pci_read_config8(dev, 0xb4);
 134         reg |= 0x11;
 135         pci_write_config8(dev, 0xb4, reg);
 136
 137         pci_write_config8(dev, 0xb9, 0x98);
 138         pci_write_config8(dev, 0xba, 0x77);
 139         pci_write_config8(dev, 0xbb, 0x11);
 140
 141         reg = pci_read_config8(dev, 0xb8);
 142         reg |= 0x1;
 143         pci_write_config8(dev, 0xb8, reg);
 144
 145         pci_write_config8(dev, 0xb0, 0x06);
 146         pci_write_config8(dev, 0xb1, 0x01);
 147
 148         /* Program V-link 8X 16bit full duplex, parity enabled. */
 149         pci_write_config8(dev, 0x48, 0xa3);
 150 }
 151
 152 static void ctrl_init(struct device *dev)
 153 {
 154
 155         print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
 156         /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
 157            should to 1 */
 158
 159         /* C2P Read ACK Return Priority */
 160         /* PCI CFG Address bits[27:24] are used as extended register address
 161            bit[11:8] */
 162
 163 #if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
 164         pci_write_config8(dev, 0x47, 0x30);
 165 #endif
 166
 167         /* VT8237R specific configuration  other SB are done in their own directories */
 168
 169         device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
 170                                          PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
 171         if (devsb) {
 172                 vt8237r_vlink_init(dev);
 173                 k8x8xx_vt8237r_cfg(dev, devsb);
 174         } else {
 175                 print_debug("VT8237R LPC not found !\n");
 176                 return;
 177         }
 178         print_debug(" Done\n");
 179         print_debug(" VIA_X_7 device dump:\n");
 180         dump_south(dev);
 181
 182 }
 183
 184 static struct pci_operations lops_pci = {
 185         .set_subsystem = pci_dev_set_subsystem,
 186 };
 187
 188 static const struct device_operations ctrl_ops = {
 189         .read_resources         = pci_dev_read_resources,
 190         .set_resources          = pci_dev_set_resources,
 191         .enable_resources       = pci_dev_enable_resources,
 192         .init                   = ctrl_init,
 193         .ops_pci                = &lops_pci,
 194 };
 195
 196 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
 197         .ops    = &ctrl_ops,
 198         .vendor = PCI_VENDOR_ID_VIA,
 199         .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR,
 200 };
 201
 202 static const struct pci_driver northbridge_driver_m800 __pci_driver = {
 203         .ops    = &ctrl_ops,
 204         .vendor = PCI_VENDOR_ID_VIA,
 205         .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR,
 206 };
 207
 208 static const struct pci_driver northbridge_driver_t890 __pci_driver = {
 209         .ops    = &ctrl_ops,
 210         .vendor = PCI_VENDOR_ID_VIA,
 211         .device = PCI_DEVICE_ID_VIA_K8T890CE_7,
 212 };
 213
 214 static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
 215         .ops    = &ctrl_ops,
 216         .vendor = PCI_VENDOR_ID_VIA,
 217         .device = PCI_DEVICE_ID_VIA_K8T890CF_7,
 218 };
 219
 220 static const struct pci_driver northbridge_driver_m890 __pci_driver = {
 221         .ops    = &ctrl_ops,
 222         .vendor = PCI_VENDOR_ID_VIA,
 223         .device = PCI_DEVICE_ID_VIA_K8M890CE_7,
 224 };