2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <arch/romcc_io.h>
23 #include <console/console.h>
25 #include <device/pci_def.h>
27 /* Required for successful build, but currently empty. */
28 void set_debug_port(unsigned int port)
30 /* Not needed, the southbridges hardcode physical USB port 1. */
33 void sch_enable_usbdebug(unsigned int port)
36 device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
38 /* Set the EHCI BAR address. */
39 pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
41 /* Enable access to the EHCI memory space registers. */
42 pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
44 /* Force ownership of the Debug Port to the EHCI controller. */
45 printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
46 dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
48 write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);