2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <pc80/mc146818rtc.h>
26 #include <pc80/isa-dma.h>
27 #include <pc80/i8259.h>
29 #include <arch/ioapic.h>
32 #include <cpu/x86/smm.h>
36 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
37 #define TEST_SMM_FLASH_LOCKDOWN 0
39 typedef struct southbridge_intel_i82801gx_config config_t;
41 static void i82801gx_enable_apic(struct device *dev)
45 volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
46 volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
48 /* Enable ACPI I/O and power management.
51 pci_write_config8(dev, ACPI_CNTL, 0x80);
54 *ioapic_data = (1 << 25);
58 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
59 if (reg32 != (1 << 25))
62 printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
65 printk(BIOS_SPEW, " reg 0x%04x:", i);
67 printk(BIOS_SPEW, " 0x%08x\n", reg32);
70 *ioapic_index = 3; /* Select Boot Configuration register. */
71 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
74 static void i82801gx_enable_serial_irqs(struct device *dev)
76 /* Set packet length and toggle silent mode bit for one frame. */
77 pci_write_config8(dev, SERIRQ_CNTL,
78 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
81 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
82 * 0x00 - 0000 = Reserved
83 * 0x01 - 0001 = Reserved
84 * 0x02 - 0010 = Reserved
90 * 0x08 - 1000 = Reserved
95 * 0x0D - 1101 = Reserved
98 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
99 * 0x80 - The PIRQ is not routed.
102 static void i82801gx_pirq_init(device_t dev)
105 /* Get the chip configuration */
106 config_t *config = dev->chip_info;
108 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
109 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
110 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
111 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
113 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
114 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
115 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
116 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
118 /* Eric Biederman once said we should let the OS do this.
119 * I am not so sure anymore he was right.
122 for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
123 u8 int_pin=0, int_line=0;
125 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
128 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
131 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
132 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
133 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
134 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
140 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
144 static void i82801gx_gpi_routing(device_t dev)
146 /* Get the chip configuration */
147 config_t *config = dev->chip_info;
150 /* An array would be much nicer here, or some
151 * other method of doing this.
153 reg32 |= (config->gpi0_routing & 0x03) << 0;
154 reg32 |= (config->gpi1_routing & 0x03) << 2;
155 reg32 |= (config->gpi2_routing & 0x03) << 4;
156 reg32 |= (config->gpi3_routing & 0x03) << 6;
157 reg32 |= (config->gpi4_routing & 0x03) << 8;
158 reg32 |= (config->gpi5_routing & 0x03) << 10;
159 reg32 |= (config->gpi6_routing & 0x03) << 12;
160 reg32 |= (config->gpi7_routing & 0x03) << 14;
161 reg32 |= (config->gpi8_routing & 0x03) << 16;
162 reg32 |= (config->gpi9_routing & 0x03) << 18;
163 reg32 |= (config->gpi10_routing & 0x03) << 20;
164 reg32 |= (config->gpi11_routing & 0x03) << 22;
165 reg32 |= (config->gpi12_routing & 0x03) << 24;
166 reg32 |= (config->gpi13_routing & 0x03) << 26;
167 reg32 |= (config->gpi14_routing & 0x03) << 28;
168 reg32 |= (config->gpi15_routing & 0x03) << 30;
170 pci_write_config32(dev, 0xb8, reg32);
173 extern u8 acpi_slp_type;
175 static void i82801gx_power_options(device_t dev)
181 /* Get the chip configuration */
182 config_t *config = dev->chip_info;
184 int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
187 /* Which state do we want to goto after g3 (power restored)?
191 * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
193 if (get_option(&pwr_on, "power_on_after_fail") < 0)
194 pwr_on = MAINBOARD_POWER_ON;
196 reg8 = pci_read_config8(dev, GEN_PMCON_3);
199 case MAINBOARD_POWER_OFF:
203 case MAINBOARD_POWER_ON:
207 case MAINBOARD_POWER_KEEP:
209 state = "state keep";
215 reg8 |= (3 << 4); /* avoid #S4 assertions */
216 reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
218 pci_write_config8(dev, GEN_PMCON_3, reg8);
219 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
221 /* Set up NMI on errors. */
223 reg8 &= 0x0f; /* Higher Nibble must be 0 */
224 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
225 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
226 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
230 nmi_option = NMI_OFF;
231 get_option(&nmi_option, "nmi");
233 printk(BIOS_INFO, "NMI sources enabled.\n");
234 reg8 &= ~(1 << 7); /* Set NMI. */
236 printk(BIOS_INFO, "NMI sources disabled.\n");
237 reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
241 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
242 reg16 = pci_read_config16(dev, GEN_PMCON_1);
243 reg16 &= ~(3 << 0); // SMI# rate 1 minute
244 reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
245 reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
246 reg16 |= (1 << 5); // CPUSLP_EN Desktop only
247 // another laptop wants this?
248 // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
249 reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
250 #if DEBUG_PERIODIC_SMIS
251 /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
254 reg16 |= (3 << 0); // Periodic SMI every 8s
256 pci_write_config16(dev, GEN_PMCON_1, reg16);
258 // Set the board's GPI routing.
259 i82801gx_gpi_routing(dev);
261 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
263 outl(config->gpe0_en, pmbase + GPE0_EN);
264 outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
266 /* Set up power management block and determine sleep mode */
267 reg32 = inl(pmbase + 0x04); // PM1_CNT
269 reg32 &= ~(7 << 10); // SLP_TYP
270 reg32 |= (1 << 1); // enable C3->C0 transition on bus master
271 reg32 |= (1 << 0); // SCI_EN
272 outl(reg32, pmbase + 0x04);
275 static void i82801gx_configure_cstates(device_t dev)
279 reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
280 reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
281 pci_write_config8(dev, 0xa9, reg8);
283 // Set Deeper Sleep configuration to recommended values
284 reg8 = pci_read_config8(dev, 0xaa);
286 reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us
287 reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us
288 pci_write_config8(dev, 0xaa, reg8);
291 static void i82801gx_rtc_init(struct device *dev)
296 reg8 = pci_read_config8(dev, GEN_PMCON_3);
297 rtc_failed = reg8 & RTC_BATTERY_DEAD;
299 reg8 &= ~RTC_BATTERY_DEAD;
300 pci_write_config8(dev, GEN_PMCON_3, reg8);
302 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
304 rtc_init(rtc_failed);
307 static void enable_hpet(void)
311 /* Move HPET to default address 0xfed00000 and enable it */
312 reg32 = RCBA32(HPTC);
313 reg32 |= (1 << 7); // HPET Address Enable
315 RCBA32(HPTC) = reg32;
318 static void enable_clock_gating(void)
322 /* Enable Clock Gating for most devices */
324 reg32 |= (1 << 31); // LPC clock gating
325 reg32 |= (1 << 30); // PATA clock gating
327 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
328 reg32 |= (1 << 23); // AC97 clock gating
329 reg32 |= (1 << 19); // USB EHCI clock gating
330 reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
331 reg32 |= (1 << 2); // PCIe clock gating;
332 reg32 &= ~(1 << 20); // No static clock gating for USB
333 reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
337 #if CONFIG_HAVE_SMI_HANDLER
338 static void i82801gx_lock_smm(struct device *dev)
340 #if TEST_SMM_FLASH_LOCKDOWN
344 #if ENABLE_ACPI_MODE_IN_COREBOOT
345 printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
346 outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
347 printk(BIOS_DEBUG, "done.\n");
349 printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
350 outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
351 printk(BIOS_DEBUG, "done.\n");
353 /* Don't allow evil boot loaders, kernels, or
354 * userspace applications to deceive us:
358 #if TEST_SMM_FLASH_LOCKDOWN
360 printk(BIOS_DEBUG, "Locking BIOS to RO... ");
361 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
362 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
364 reg8 &= ~(1 << 0); /* clear BIOSWE */
365 pci_write_config8(dev, 0xdc, reg8);
366 reg8 |= (1 << 1); /* set BLE */
367 pci_write_config8(dev, 0xdc, reg8);
368 printk(BIOS_DEBUG, "ok.\n");
369 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
370 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
373 printk(BIOS_DEBUG, "Writing:\n");
374 *(volatile u8 *)0xfff00000 = 0x00;
375 printk(BIOS_DEBUG, "Testing:\n");
376 reg8 |= (1 << 0); /* set BIOSWE */
377 pci_write_config8(dev, 0xdc, reg8);
379 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
380 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
382 printk(BIOS_DEBUG, "Done.\n");
387 #define SPIBASE 0x3020
388 static void i82801gx_spi_init(void)
392 spicontrol = RCBA16(SPIBASE + 2);
393 spicontrol &= ~(1 << 0); // SPI Access Request
394 RCBA16(SPIBASE + 2) = spicontrol;
397 static void i82801gx_fixups(struct device *dev)
399 /* This needs to happen after PCI enumeration */
402 /* USB Transient Disconnect Detect:
403 * Prevent a SE0 condition on the USB ports from being
404 * interpreted by the UHCI controller as a disconnect
406 pci_write_config8(dev, 0xad, 0x3);
409 static void lpc_init(struct device *dev)
411 printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
413 /* Set the value for PCI command register. */
414 pci_write_config16(dev, PCI_COMMAND, 0x000f);
416 /* IO APIC initialization. */
417 i82801gx_enable_apic(dev);
419 i82801gx_enable_serial_irqs(dev);
421 /* Setup the PIRQ. */
422 i82801gx_pirq_init(dev);
424 /* Setup power options. */
425 i82801gx_power_options(dev);
427 /* Configure Cx state registers */
428 i82801gx_configure_cstates(dev);
430 /* Set the state of the GPIO lines. */
433 /* Initialize the real time clock. */
434 i82801gx_rtc_init(dev);
436 /* Initialize ISA DMA. */
439 /* Initialize the High Precision Event Timers, if present. */
442 /* Initialize Clock Gating */
443 enable_clock_gating();
447 /* The OS should do this? */
448 /* Interrupt 9 should be level triggered (SCI) */
449 i8259_configure_irq_trigger(9, 1);
451 #if CONFIG_HAVE_SMI_HANDLER
452 i82801gx_lock_smm(dev);
457 i82801gx_fixups(dev);
460 static void i82801gx_lpc_read_resources(device_t dev)
462 struct resource *res;
464 /* Get the normal PCI resources of this device. */
465 pci_dev_read_resources(dev);
467 /* Add an extra subtractive resource for both memory and I/O. */
468 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
471 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
472 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
474 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
475 res->base = 0xff800000;
476 res->size = 0x00800000; /* 8 MB for flash */
477 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
478 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
480 res = new_resource(dev, 3); /* IOAPIC */
481 res->base = IO_APIC_ADDR;
482 res->size = 0x00001000;
483 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
486 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
488 if (!vendor || !device) {
489 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
490 pci_read_config32(dev, PCI_VENDOR_ID));
492 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
493 ((device & 0xffff) << 16) | (vendor & 0xffff));
497 static struct pci_operations pci_ops = {
498 .set_subsystem = set_subsystem,
501 static struct device_operations device_ops = {
502 .read_resources = i82801gx_lpc_read_resources,
503 .set_resources = pci_dev_set_resources,
504 .enable_resources = pci_dev_enable_resources,
506 .scan_bus = scan_static_bus,
507 .enable = i82801gx_enable,
511 /* 82801GH (ICH7 DH) */
512 static const struct pci_driver ich7_dh_lpc __pci_driver = {
514 .vendor = PCI_VENDOR_ID_INTEL,
518 /* 82801GB/GR (ICH7/ICH7R) */
519 static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
521 .vendor = PCI_VENDOR_ID_INTEL,
525 /* 82801GBM/GU (ICH7-M/ICH7-U) */
526 static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
528 .vendor = PCI_VENDOR_ID_INTEL,
532 /* 82801GHM (ICH7-M DH) */
533 static const struct pci_driver ich7m_dh_lpc __pci_driver = {
535 .vendor = PCI_VENDOR_ID_INTEL,