2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
21 #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
23 * It does not matter where we put the SMBus I/O base, as long as we
24 * keep it consistent and don't interfere with other devices. Stage2
25 * will relocate this anyways.
26 * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
27 * again. But handling static BARs is a generic problem that should be
28 * solved in the device allocator.
30 #define SMBUS_IO_BASE 0x0400
31 /* TODO Make sure these don't get changed by stage2 */
32 #define DEFAULT_GPIOBASE 0x0480
33 #define DEFAULT_PMBASE 0x0500
35 #define IO_APIC_ADDR 0xfec00000
36 #define HPET_ADDR 0xfed00000
37 #define DEFAULT_RCBA 0xfed1c000
40 #define DEBUG_PERIODIC_SMIS 0
42 #if !defined(ASSEMBLY)
43 #if !defined(__PRE_RAM__)
45 extern void i82801gx_enable(device_t dev);
47 void i82801gx_enable_usbdebug(unsigned int port);
50 #define MAINBOARD_POWER_OFF 0
51 #define MAINBOARD_POWER_ON 1
52 #define MAINBOARD_POWER_KEEP 2
54 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
55 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
58 /* PCI Configuration Space (D30:F0): PCI2PCI */
68 /* PCI Configuration Space (D31:F0): LPC */
70 #define SERIRQ_CNTL 0x64
72 #define GEN_PMCON_1 0xa0
73 #define GEN_PMCON_2 0xa2
74 #define GEN_PMCON_3 0xa4
76 /* GEN_PMCON_3 bits */
77 #define RTC_BATTERY_DEAD (1 << 2)
78 #define RTC_POWER_FAILED (1 << 1)
79 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
82 #define ACPI_CNTL 0x44
83 #define BIOS_CNTL 0xDC
84 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
85 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
87 #define PIRQA_ROUT 0x60
88 #define PIRQB_ROUT 0x61
89 #define PIRQC_ROUT 0x62
90 #define PIRQD_ROUT 0x63
91 #define PIRQE_ROUT 0x68
92 #define PIRQF_ROUT 0x69
93 #define PIRQG_ROUT 0x6A
94 #define PIRQH_ROUT 0x6B
96 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
97 #define LPC_EN 0x82 /* LPC IF Enables Register */
99 /* PCI Configuration Space (D31:F1): IDE */
101 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
102 #define IDE_DECODE_ENABLE (1 << 15)
103 #define IDE_SITRE (1 << 14)
104 #define IDE_ISP_5_CLOCKS (0 << 12)
105 #define IDE_ISP_4_CLOCKS (1 << 12)
106 #define IDE_ISP_3_CLOCKS (2 << 12)
107 #define IDE_RCT_4_CLOCKS (0 << 8)
108 #define IDE_RCT_3_CLOCKS (1 << 8)
109 #define IDE_RCT_2_CLOCKS (2 << 8)
110 #define IDE_RCT_1_CLOCKS (3 << 8)
111 #define IDE_DTE1 (1 << 7)
112 #define IDE_PPE1 (1 << 6)
113 #define IDE_IE1 (1 << 5)
114 #define IDE_TIME1 (1 << 4)
115 #define IDE_DTE0 (1 << 3)
116 #define IDE_PPE0 (1 << 2)
117 #define IDE_IE0 (1 << 1)
118 #define IDE_TIME0 (1 << 0)
119 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
121 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
122 #define IDE_SSDE1 (1 << 3)
123 #define IDE_SSDE0 (1 << 2)
124 #define IDE_PSDE1 (1 << 1)
125 #define IDE_PSDE0 (1 << 0)
127 #define IDE_SDMA_TIM 0x4a
129 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
130 #define SIG_MODE_SEC_NORMAL (0 << 18)
131 #define SIG_MODE_SEC_TRISTATE (1 << 18)
132 #define SIG_MODE_SEC_DRIVELOW (2 << 18)
133 #define SIG_MODE_PRI_NORMAL (0 << 16)
134 #define SIG_MODE_PRI_TRISTATE (1 << 16)
135 #define SIG_MODE_PRI_DRIVELOW (2 << 16)
136 #define FAST_SCB1 (1 << 15)
137 #define FAST_SCB0 (1 << 14)
138 #define FAST_PCB1 (1 << 13)
139 #define FAST_PCB0 (1 << 12)
140 #define SCB1 (1 << 3)
141 #define SCB0 (1 << 2)
142 #define PCB1 (1 << 1)
143 #define PCB0 (1 << 0)
145 /* PCI Configuration Space (D31:F3): SMBus */
146 #define SMB_BASE 0x20
150 #define I2C_EN (1 << 2)
151 #define SMB_SMI_EN (1 << 1)
152 #define HST_EN (1 << 0)
154 /* SMBus I/O bits. */
155 #define SMBHSTSTAT 0x0
156 #define SMBHSTCTL 0x2
157 #define SMBHSTCMD 0x3
158 #define SMBXMITADD 0x4
159 #define SMBHSTDAT0 0x5
160 #define SMBHSTDAT1 0x6
161 #define SMBBLKDAT 0x7
162 #define SMBTRNSADD 0x9
163 #define SMBSLVDATA 0xa
164 #define SMLINK_PIN_CTL 0xe
165 #define SMBUS_PIN_CTL 0xf
167 #define SMBUS_TIMEOUT (10 * 1000 * 100)
170 /* Southbridge IO BARs */
172 #define GPIOBASE 0x48
176 /* Root Complex Register Block */
179 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
180 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
181 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
183 #define VCH 0x0000 /* 32bit */
184 #define VCAP1 0x0004 /* 32bit */
185 #define VCAP2 0x0008 /* 32bit */
186 #define PVC 0x000c /* 16bit */
187 #define PVS 0x000e /* 16bit */
189 #define V0CAP 0x0010 /* 32bit */
190 #define V0CTL 0x0014 /* 32bit */
191 #define V0STS 0x001a /* 16bit */
193 #define V1CAP 0x001c /* 32bit */
194 #define V1CTL 0x0020 /* 32bit */
195 #define V1STS 0x0026 /* 16bit */
197 #define RCTCL 0x0100 /* 32bit */
198 #define ESD 0x0104 /* 32bit */
199 #define ULD 0x0110 /* 32bit */
200 #define ULBA 0x0118 /* 64bit */
202 #define RP1D 0x0120 /* 32bit */
203 #define RP1BA 0x0128 /* 64bit */
204 #define RP2D 0x0130 /* 32bit */
205 #define RP2BA 0x0138 /* 64bit */
206 #define RP3D 0x0140 /* 32bit */
207 #define RP3BA 0x0148 /* 64bit */
208 #define RP4D 0x0150 /* 32bit */
209 #define RP4BA 0x0158 /* 64bit */
210 #define HDD 0x0160 /* 32bit */
211 #define HDBA 0x0168 /* 64bit */
212 #define RP5D 0x0170 /* 32bit */
213 #define RP5BA 0x0178 /* 64bit */
214 #define RP6D 0x0180 /* 32bit */
215 #define RP6BA 0x0188 /* 64bit */
217 #define ILCL 0x01a0 /* 32bit */
218 #define LCAP 0x01a4 /* 32bit */
219 #define LCTL 0x01a8 /* 16bit */
220 #define LSTS 0x01aa /* 16bit */
222 #define RPC 0x0224 /* 32bit */
223 #define RPFN 0x0238 /* 32bit */
225 #define TRSR 0x1e00 /* 8bit */
226 #define TRCR 0x1e10 /* 64bit */
227 #define TWDR 0x1e18 /* 64bit */
229 #define IOTR0 0x1e80 /* 64bit */
230 #define IOTR1 0x1e88 /* 64bit */
231 #define IOTR2 0x1e90 /* 64bit */
232 #define IOTR3 0x1e98 /* 64bit */
234 #define TCTL 0x3000 /* 8bit */
236 #define D31IP 0x3100 /* 32bit */
237 #define D30IP 0x3104 /* 32bit */
238 #define D29IP 0x3108 /* 32bit */
239 #define D28IP 0x310c /* 32bit */
240 #define D27IP 0x3110 /* 32bit */
241 #define D31IR 0x3140 /* 16bit */
242 #define D30IR 0x3142 /* 16bit */
243 #define D29IR 0x3144 /* 16bit */
244 #define D28IR 0x3146 /* 16bit */
245 #define D27IR 0x3148 /* 16bit */
246 #define OIC 0x31ff /* 8bit */
248 #define RC 0x3400 /* 32bit */
249 #define HPTC 0x3404 /* 32bit */
250 #define GCS 0x3410 /* 32bit */
251 #define BUC 0x3414 /* 32bit */
252 #define FD 0x3418 /* 32bit */
253 #define CG 0x341c /* 32bit */
255 /* Function Disable (FD) register values.
256 * Setting a bit disables the corresponding
258 * Not all features might be disabled on
259 * all chipsets. Esp. ICH-7U is picky.
261 #define FD_PCIE6 (1 << 21)
262 #define FD_PCIE5 (1 << 20)
263 #define FD_PCIE4 (1 << 19)
264 #define FD_PCIE3 (1 << 18)
265 #define FD_PCIE2 (1 << 17)
266 #define FD_PCIE1 (1 << 16)
267 #define FD_EHCI (1 << 15)
268 #define FD_LPCB (1 << 14)
270 /* UHCI must be disabled from 4 downwards.
271 * If UHCI controllers get disabled, EHCI
272 * must know about it, too! */
273 #define FD_UHCI4 (1 << 11)
274 #define FD_UHCI34 (1 << 10) | FD_UHCI4
275 #define FD_UHCI234 (1 << 9) | FD_UHCI3
276 #define FD_UHCI1234 (1 << 8) | FD_UHCI2
278 #define FD_INTLAN (1 << 7)
279 #define FD_ACMOD (1 << 6)
280 #define FD_ACAUD (1 << 5)
281 #define FD_HDAUD (1 << 4)
282 #define FD_SMBUS (1 << 3)
283 #define FD_SATA (1 << 2)
284 #define FD_PATA (1 << 1)
287 #define GPIO_USE_SEL 0x00
288 #define GP_IO_SEL 0x04
290 #define GPO_BLINK 0x18
292 #define GPIO_USE_SEL2 0x30
293 #define GP_IO_SEL2 0x34
298 #define WAK_STS (1 << 15)
299 #define PCIEXPWAK_STS (1 << 14)
300 #define PRBTNOR_STS (1 << 11)
301 #define RTC_STS (1 << 10)
302 #define PWRBTN_STS (1 << 8)
303 #define GBL_STS (1 << 5)
304 #define BM_STS (1 << 4)
305 #define TMROF_STS (1 << 0)
307 #define PCIEXPWAK_DIS (1 << 14)
308 #define RTC_EN (1 << 10)
309 #define PWRBTN_EN (1 << 8)
310 #define GBL_EN (1 << 5)
311 #define TMROF_EN (1 << 0)
313 #define SLP_EN (1 << 13)
314 #define SLP_TYP (7 << 10)
315 #define GBL_RLS (1 << 2)
316 #define BM_RLD (1 << 1)
317 #define SCI_EN (1 << 0)
319 #define PROC_CNT 0x10
323 #define PM2_CNT 0x20 // mobile only
324 #define GPE0_STS 0x28
325 #define USB4_STS (1 << 14)
326 #define PME_B0_STS (1 << 13)
327 #define USB3_STS (1 << 12)
328 #define PME_STS (1 << 11)
329 #define BATLOW_STS (1 << 10)
330 #define PCI_EXP_STS (1 << 9)
331 #define RI_STS (1 << 8)
332 #define SMB_WAK_STS (1 << 7)
333 #define TCOSCI_STS (1 << 6)
334 #define AC97_STS (1 << 5)
335 #define USB2_STS (1 << 4)
336 #define USB1_STS (1 << 3)
337 #define SWGPE_STS (1 << 2)
338 #define HOT_PLUG_STS (1 << 1)
339 #define THRM_STS (1 << 0)
341 #define PME_B0_EN (1 << 13)
342 #define PME_EN (1 << 11)
344 #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
345 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
346 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
347 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
348 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
349 #define MCSMI_EN (1 << 11) // Trap microcontroller range access
350 #define BIOS_RLS (1 << 7) // asserts SCI on bit set
351 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
352 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
353 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
354 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
355 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
356 #define EOS (1 << 1) // End of SMI (deassert SMI#)
357 #define GBL_SMI_EN (1 << 0) // SMI# generation at all?
359 #define ALT_GP_SMI_EN 0x38
360 #define ALT_GP_SMI_STS 0x3a
361 #define GPE_CNTL 0x42
362 #define DEVACT_STS 0x44
366 #endif /* __ACPI__ */
367 #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */