2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * for rs780 internal graphics device
22 * device id of internal grphics:
28 * RS785G: 0x9710 - just works, not much tested
34 #include <console/console.h>
35 #include <device/device.h>
36 #include <device/pci.h>
37 #include <device/pci_ids.h>
38 #include <device/pci_ops.h>
40 #include <cpu/x86/msr.h>
42 extern int is_dev3_present(void);
43 void set_pcie_reset(void);
44 void set_pcie_dereset(void);
46 extern uint64_t uma_memory_base, uma_memory_size;
48 /* Trust the original resource allocation. Don't do it again. */
49 #undef DONT_TRUST_RESOURCE_ALLOCATION
50 //#define DONT_TRUST_RESOURCE_ALLOCATION
52 #define CLK_CNTL_INDEX 0x8
53 #define CLK_CNTL_DATA 0xC
55 /* The Integrated Info Table. */
56 ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
59 static u32 clkind_read(device_t dev, u32 index)
61 u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
63 *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
64 return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
68 static void clkind_write(device_t dev, u32 index, u32 data)
70 u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
71 /* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */
73 *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
74 *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data;
78 * pci_dev_read_resources thinks it is a IO type.
79 * We have to force it to mem type.
81 static void rs780_gfx_read_resources(device_t dev)
83 printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n");
85 /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
86 Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
87 which tells us it is a memory address base.
89 pci_write_config32(dev, 0x24, 0x00000000);
91 /* Get the normal pci resources of this device */
92 pci_dev_read_resources(dev);
93 compact_resources(dev);
96 typedef struct _MMIORANGE
103 MMIORANGE MMIO[8], CreativeMMIO[8];
105 #define CIM_STATUS u32
106 #define CIM_SUCCESS 0x00000000
107 #define CIM_ERROR 0x80000000
108 #define CIM_UNSUPPORTED 0x80000001
109 #define CIM_DISABLEPORT 0x80000002
111 #define MMIO_ATTRIB_NP_ONLY 1
112 #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
113 #define MMIO_ATTRIB_SKIP_ZERO 1<<2
115 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
116 static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
119 for (i=0; i<8; i++) {
120 if (pMMIO[i].Limit == 0)
126 static void FreeMMIO(MMIORANGE* pMMIO)
132 static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
135 MMIORANGE * TempRange;
138 if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
140 TempRange = AllocMMIO(pMMIO);
141 if(TempRange == 0) return 0x80000000;
142 TempRange->Base = Limit;
143 TempRange->Limit = pMMIO[i].Limit;
144 TempRange->Attribute = pMMIO[i].Attribute;
145 pMMIO[i].Limit = Base;
148 TempRange = AllocMMIO(pMMIO);
149 if(TempRange == 0) return 0x80000000;
150 TempRange->Base = Base;
151 TempRange->Limit = Limit;
152 TempRange->Attribute = Attribute;
156 static u8 FinalizeMMIO(MMIORANGE *pMMIO)
161 if (pMMIO[i].Base == pMMIO[i].Limit)
168 if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
170 if (pMMIO[i].Base == pMMIO[j].Limit)
172 pMMIO[j].Limit = pMMIO[i].Limit;
175 if (pMMIO[i].Limit == pMMIO[j].Base)
177 pMMIO[j].Base = pMMIO[i].Base;
185 if (pMMIO[i].Limit != 0) n++;
190 static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
192 CIM_STATUS Status = CIM_UNSUPPORTED;
193 u8 Bus, Dev, Reg, BusStart, BusEnd;
195 device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
197 Value = pci_read_config32(dev0x14, 0x18);
198 BusStart = (Value >> 8) & 0xFF;
199 BusEnd = (Value >> 16) & 0xFF;
200 for(Bus = BusStart; Bus <= BusEnd; Bus++)
202 for(Dev = 0; Dev <= 0x1f; Dev++)
204 tempdev = dev_find_slot(Bus, Dev << 3);
205 Value = pci_read_config32(tempdev, 0);
206 printk(BIOS_DEBUG, "Dev ID %x \n", Value);
207 if((Value & 0xffff) == 0x1102)
210 u32 MMIOStart = 0xffffffff;
212 for(Reg = 0x10; Reg < 0x20; Reg+=4)
215 BaseA = pci_read_config32(tempdev, Reg);
219 Value = Value & 0xffffff00;
222 if(MMIOStart > Value)
225 //WritePCI(PciAddress,AccWidthUint32,&LimitA);
226 pci_write_config32(tempdev, Reg, LimitA);
227 //ReadPCI(PciAddress,AccWidthUint32,&LimitA);
228 LimitA = pci_read_config32(tempdev, Reg);
229 LimitA = Value + (~LimitA + 1);
230 //WritePCI(PciAddress,AccWidthUint32,&BaseA);
231 pci_write_config32(tempdev, Reg, BaseA);
232 if (LimitA > MMIOLimit)
237 printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
238 if (MMIOStart < MMIOLimit)
240 Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
241 if(Status == CIM_ERROR) return Status;
246 if(Status == CIM_SUCCESS)
249 if(FinalizeMMIO(pMMIO) > 4)
258 static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
263 k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
265 for(i = 0; i < 8; i++)
270 for(j = 0; j < 8; j++)
272 if (Base < pMMIO[j].Base)
274 Base = pMMIO[j].Base;
278 if(pMMIO[k].Limit != 0)
280 if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
286 Base = pMMIO[k].Base | 0x3;
287 Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4);
291 if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue;
292 MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n);
294 //RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0);
295 pci_write_config32(k8_f1, 0x80+MmioReg*8, 0);
297 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit);
298 pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit);
300 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base);
301 pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
306 static void internal_gfx_pci_dev_init(struct device *dev)
308 unsigned char * bpointer;
309 volatile u32 * GpuF0MMReg;
310 volatile u32 * pointer;
314 u16 deviceid, vendorid;
315 device_t nb_dev = dev_find_slot(0, 0);
316 device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
317 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
318 static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
319 static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
320 static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
321 static const u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800};
323 /* We definetely will use this in future. Just leave it here. */
324 /*struct southbridge_amd_rs780_config *cfg =
325 (struct southbridge_amd_rs780_config *)dev->chip_info;*/
327 deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
328 vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
329 printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
332 command = pci_read_config16(dev, 0x04);
334 pci_write_config16(dev, 0x04, command);
337 bpointer = (unsigned char *) &vgainfo;
338 for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
344 GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18);
346 /* GFX_InitFBAccess. */
347 value = nbmc_read_index(nb_dev, 0x10);
348 *(GpuF0MMReg + 0x2000/4) = 0x11;
349 *(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
350 *(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
351 *(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
352 *(GpuF0MMReg + 0xF774/4) = 0xffffffff;
353 *(GpuF0MMReg + 0xF770/4) = 0x00000001;
354 *(GpuF0MMReg + 0x2000/4) = 0x00000011;
355 *(GpuF0MMReg + 0x200c/4) = 0x00000020;
356 *(GpuF0MMReg + 0x2010/4) = 0x10204810;
357 *(GpuF0MMReg + 0x2010/4) = 0x00204810;
358 *(GpuF0MMReg + 0x2014/4) = 0x10408810;
359 *(GpuF0MMReg + 0x2014/4) = 0x00408810;
360 *(GpuF0MMReg + 0x2414/4) = 0x00000080;
361 *(GpuF0MMReg + 0x2418/4) = 0x84422415;
362 *(GpuF0MMReg + 0x2418/4) = 0x04422415;
363 *(GpuF0MMReg + 0x5490/4) = 0x00000001;
364 *(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
365 /* Force allow LDT_STOP Cool'n'Quiet workaround. */
366 *(GpuF0MMReg + 0x655c/4) |= 1<<4;
368 // disable write combining, needed for stability
369 // reference bios does this only for RS780 rev A11
370 // need to figure out why we need it for all revs
371 *(GpuF0MMReg + 0x2000/4) = 0x00000010;
372 *(GpuF0MMReg + 0x2408/4) = 1 << 9;
373 *(GpuF0MMReg + 0x2000/4) = 0x00000011;
375 /* GFX_InitFBAccess finished. */
377 #if (CONFIG_GFXUMA == 1) /* for UMA mode. */
379 set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
380 set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
381 set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004);
382 set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000);
383 set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040);
384 set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001);
385 set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018);
386 set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102);
387 set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008);
388 set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000);
389 /* GFX_StartMC finished. */
392 set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30);
393 set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30);
394 set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000);
395 set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000);
396 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0);
397 set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31);
398 set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f);
399 set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6);
400 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0);
401 set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0);
402 nbmc_write_index(nb_dev, 0xa4, 0x3484576f);
403 nbmc_write_index(nb_dev, 0xa5, 0x222222df);
404 nbmc_write_index(nb_dev, 0xa6, 0x00000000);
405 nbmc_write_index(nb_dev, 0xa7, 0x00000000);
406 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0);
408 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0);
410 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2);
412 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3);
413 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31);
415 set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31);
416 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30);
417 set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0);
418 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29);
419 nbmc_write_index(nb_dev, 0xa4, 0x23484576);
420 nbmc_write_index(nb_dev, 0xa5, 0x00000000);
421 nbmc_write_index(nb_dev, 0xa6, 0x00000000);
422 nbmc_write_index(nb_dev, 0xa7, 0x00000000);
423 /* GFX_StartMC finished. */
425 /* GFX_SPPowerManagment, don't care for new. */
426 /* Post MC Init table programming. */
427 set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b);
429 /* Do we need Write and Read Calibration? */
430 /* GFX_Init finished. */
433 /* GFX_InitIntegratedInfo. */
434 /* fill the Integrated Info Table. */
435 vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2);
436 vgainfo.sHeader.ucTableFormatRevision = 1;
437 vgainfo.sHeader.ucTableContentRevision = 2;
439 #if (CONFIG_GFXUMA == 0) /* SP mode. */
440 // Side port support is incomplete, do not use it
441 // These parameters must match the motherboard
442 vgainfo.ulBootUpSidePortClock = 667*100;
443 vgainfo.ucMemoryType = 3; // 3=ddr3 sp mem, 2=ddr2 sp mem
444 vgainfo.ulMinSidePortClock = 333*100;
447 vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default
449 // find the DDR memory frequency
450 if (is_family10h()) {
451 value = pci_read_config32(k8_f2, 0x94); // read channel 0 DRAM Configuration High Register
452 if (extractbit(value, 14)) // if channel 0 disabled, channel 1 must have memory
453 value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register
454 vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100;
456 if (is_family0Fh()) {
457 value = pci_read_config32(k8_f2, 0x94);
458 vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100;
461 /* UMA Channel Number: 1 or 2. */
462 vgainfo.ucUMAChannelNumber = 1;
463 if (is_family0Fh()) {
464 value = pci_read_config32(k8_f2, 0x90);
465 if (extractbit(value, 11)) // 128-bit mode
466 vgainfo.ucUMAChannelNumber = 2;
468 if (is_family10h()) {
469 u32 dch0 = pci_read_config32(k8_f2, 0x94);
470 u32 dch1 = pci_read_config32(k8_f2, 0x194);
471 if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled
472 value = pci_read_config32(k8_f2, 0x110);
473 if (extractbit(value, 4)) // ganged mode
474 vgainfo.ucUMAChannelNumber = 2;
480 vgainfo.ulCPUCapInfo = 3;
482 vgainfo.ulCPUCapInfo = 2;
485 value = pci_read_config8(nb_dev, 0xd1);
486 value = ht_freq_lookup [value] * 100; // HT link frequency in MHz
487 vgainfo.ulHTLinkFreq = value * 100; // HT frequency in units of 100 MHz
488 vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
489 vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
492 vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
494 int sblink, cpuLnkFreqCap, nbLnkFreqCap;
495 value = pci_read_config32(k8_f0, 0x64);
496 sblink = extractbits(value, 8, 10);
497 cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20);
498 nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2);
499 if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable
500 vgainfo.ulLowVoltageHTLinkFreq = 1800*100;
504 value = pci_read_config8(nb_dev, 0xcb);
505 vgainfo.usMinDownStreamHTLinkWidth =
506 vgainfo.usMaxDownStreamHTLinkWidth =
507 vgainfo.usMinUpStreamHTLinkWidth =
508 vgainfo.usMaxUpStreamHTLinkWidth =
509 vgainfo.usMinHTLinkWidth =
510 vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
512 if (is_family0Fh()) {
513 vgainfo.usUMASyncStartDelay = 322;
514 vgainfo.usUMADataReturnTime = 286;
517 if (is_family10h()) {
518 static u16 t0mult_lookup [] = {10, 50, 200, 2000};
520 value = pci_read_config32(k8_f0, 0x16c);
521 t0time = extractbits(value, 0, 3);
522 t0scale = extractbits(value, 4, 5);
523 vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time;
524 vgainfo.usUMASyncStartDelay = 100;
525 if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz
526 vgainfo.usUMADataReturnTime = 300;
527 vgainfo.usLinkStatusZeroTime = 6 * 100; // 6us for GH in HT1 mode
531 value = pci_read_config32(nb_dev, 0xac);
532 lssel = extractbits (value, 7, 8);
533 vgainfo.usUMADataReturnTime = 1300;
534 if (lssel == 0) vgainfo.usUMADataReturnTime = 150;
538 /* Transfer the Table to VBIOS. */
539 pointer = (u32 *)&vgainfo;
540 for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
542 #if (CONFIG_GFXUMA == 1)
543 *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
545 *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
547 *(GpuF0MMReg+1) = *pointer++;
553 temp = pci_read_config8(dev, 0x4);
554 //temp &= ~1; /* CIM clears this bit. Strangely, I can'd. */
556 pci_write_config8(dev, 0x4, temp);
558 // if the GFX debug bar is writable, then it has
559 // been programmed and can be safely enabled now
560 temp = pci_read_config32(nb_dev, 0x8c);
562 // if bits 1 (intgfx_enable) and 9 (gfx_debug_bar_enable)
563 // then enable gfx debug bar (set gxf_debug_decode_enable)
566 pci_write_config32(nb_dev, 0x8c, temp);
570 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
571 /* NB_SetupMGMMIO. */
573 /* clear MMIO and CreativeMMIO. */
574 bpointer = (unsigned char *)MMIO;
575 for(i=0; i<sizeof(MMIO); i++)
580 bpointer = (unsigned char *)CreativeMMIO;
581 for(i=0; i<sizeof(CreativeMMIO); i++)
587 /* Set MMIO ranges in K8. */
588 /* Set MMIO TOM - 4G. */
589 SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]);
590 /* Set MMIO for VGA Legacy FB. */
591 SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]);
593 /* Set MMIO for non prefetchable P2P. */
594 temp = pci_read_config32(dev0x14, 0x20);
595 Base32 = (temp & 0x0fff0) << 8;
596 Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
599 Status = GetCreativeMMIO(&CreativeMMIO[0]);
600 if(Status != CIM_ERROR)
601 SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
603 /* Set MMIO for prefetchable P2P. */
604 if(Status != CIM_ERROR)
606 temp = pci_read_config32(dev0x14, 0x24);
608 Base32 = (temp & 0x0fff0) <<8;
609 Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
611 SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
614 FinalizeMMIO(&MMIO[0]);
616 ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY);
617 ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO);
623 clkind_write(dev, 0x08, 0x01);
624 clkind_write(dev, 0x0C, 0x22);
625 clkind_write(dev, 0x0F, 0x0);
626 clkind_write(dev, 0x11, 0x0);
627 clkind_write(dev, 0x12, 0x0);
628 clkind_write(dev, 0x14, 0x0);
629 clkind_write(dev, 0x15, 0x0);
630 clkind_write(dev, 0x16, 0x0);
631 clkind_write(dev, 0x17, 0x0);
632 clkind_write(dev, 0x18, 0x0);
633 clkind_write(dev, 0x19, 0x0);
634 clkind_write(dev, 0x1A, 0x0);
635 clkind_write(dev, 0x1B, 0x0);
636 clkind_write(dev, 0x1C, 0x0);
637 clkind_write(dev, 0x1D, 0x0);
638 clkind_write(dev, 0x1E, 0x0);
639 clkind_write(dev, 0x26, 0x0);
640 clkind_write(dev, 0x27, 0x0);
641 clkind_write(dev, 0x28, 0x0);
642 clkind_write(dev, 0x5C, 0x0);
647 * Set registers in RS780 and CPU to enable the internal GFX.
648 * Please refer to CIM source code and BKDG.
651 static void rs780_internal_gfx_enable(device_t dev)
655 device_t nb_dev = dev_find_slot(0, 0);
658 #if (CONFIG_GFXUMA == 0)
659 u32 FB_Start, FB_End;
662 printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
664 sysmem = rdmsr(0xc001001a);
665 printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
667 /* The system top memory in 780. */
668 pci_write_config32(nb_dev, 0x90, sysmem.lo);
669 htiu_write_index(nb_dev, 0x30, 0);
670 htiu_write_index(nb_dev, 0x31, 0);
672 /* Disable external GFX and enable internal GFX. */
673 l_dword = pci_read_config32(nb_dev, 0x8c);
676 pci_write_config32(nb_dev, 0x8c, l_dword);
678 /* NB_SetDefaultIndexes */
679 pci_write_config32(nb_dev, 0x94, 0x7f);
680 pci_write_config32(nb_dev, 0x60, 0x7f);
681 pci_write_config32(nb_dev, 0xe0, 0);
683 /* NB_InitEarlyNB finished. */
685 /* LPC DMA Deadlock workaround? */
687 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
688 l_dword = pci_read_config32(k8_f0, 0x68);
689 l_dword &= ~(3 << 21);
690 l_dword |= (1 << 21);
691 pci_write_config32(k8_f0, 0x68, l_dword);
693 /* GFX_InitCommon. */
694 nbmc_write_index(nb_dev, 0x23, 0x00c00010);
695 set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15);
696 set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
697 set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
699 #if (CONFIG_GFXUMA == 1)
701 /* Copy CPU DDR Controller to NB MC. */
702 device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
703 device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
704 device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
705 for (i = 0; i < 12; i++)
707 l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
708 nbmc_write_index(nb_dev, 0x30 + i, l_dword);
711 l_dword = pci_read_config32(k8_f2, 0x80);
712 nbmc_write_index(nb_dev, 0x3c, l_dword);
713 l_dword = pci_read_config32(k8_f2, 0x94);
714 set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16);
715 set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
716 l_dword = pci_read_config32(k8_f2, 0x90);
717 set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
720 for (i = 0; i < 12; i++)
722 l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
723 nbmc_write_index(nb_dev, 0x3d + i, l_dword);
726 l_dword = pci_read_config32(k8_f2, 0x180);
727 nbmc_write_index(nb_dev, 0x49, l_dword);
728 l_dword = pci_read_config32(k8_f2, 0x194);
729 set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16);
730 set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17);
731 l_dword = pci_read_config32(k8_f2, 0x190);
732 set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18);
734 l_dword = pci_read_config32(k8_f2, 0x110);
735 nbmc_write_index(nb_dev, 0x4a, l_dword);
736 l_dword = pci_read_config32(k8_f2, 0x114);
737 nbmc_write_index(nb_dev, 0x4b, l_dword);
738 l_dword = pci_read_config32(k8_f4, 0x44);
739 set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24);
740 l_dword = pci_read_config32(k8_f1, 0x40);
741 nbmc_write_index(nb_dev, 0x4c, l_dword);
742 l_dword = pci_read_config32(k8_f1, 0xf0);
743 nbmc_write_index(nb_dev, 0x4d, l_dword);
747 /* Set UMA in the 780 side. */
748 /* UMA start address, size. */
749 /* The UMA starts at 0xC0000000 of internal RS780 address space
750 [31:16] addr of last byte | [31:16] addr of first byte
752 nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
753 nbmc_write_index(nb_dev, 0x11, uma_memory_base);
754 nbmc_write_index(nb_dev, 0x12, 0);
755 nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20);
756 /* GFX_InitUMA finished. */
759 /* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */
761 /* Enable Async mode. */
762 set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8);
763 set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0);
764 /* The last item in AsynchMclkTaskFileIndex. Why? */
765 /* MC_MPLL_CONTROL2. */
766 nbmc_write_index(nb_dev, 0x07, 0x40100028);
767 /* MC_MPLL_DIV_CONTROL. */
768 nbmc_write_index(nb_dev, 0x0b, 0x00000028);
769 /* MC_MPLL_FREQ_CONTROL. */
770 set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8);
771 /* MC_MPLL_CONTROL3. For PM. */
772 set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18);
773 /* MPLL_CAL_TRIGGER. */
774 set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0);
775 udelay(200); /* time is long enough? */
776 set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1);
777 set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0);
778 /* MCLK_SRC_USE_MPLL. */
779 set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20);
782 nbmc_write_index(nb_dev, 0x01, 0x88108280);
783 set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200);
784 nbmc_write_index(nb_dev, 0x04, 0x08881018);
785 nbmc_write_index(nb_dev, 0x05, 0x000000bb);
786 nbmc_write_index(nb_dev, 0x0c, 0x0f00001f);
787 nbmc_write_index(nb_dev, 0xa1, 0x01f10000);
788 /* MCA_INIT_DLL_PM. */
789 set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24);
790 nbmc_write_index(nb_dev, 0xa2, 0x74f20000);
791 nbmc_write_index(nb_dev, 0xa3, 0x8af30000);
792 nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c);
793 nbmc_write_index(nb_dev, 0xb0, 0x88800130);
794 nbmc_write_index(nb_dev, 0xb1, 0x00000040);
795 nbmc_write_index(nb_dev, 0xb4, 0x41247000);
796 nbmc_write_index(nb_dev, 0xb5, 0x00066664);
797 nbmc_write_index(nb_dev, 0xb6, 0x00000022);
798 nbmc_write_index(nb_dev, 0xb7, 0x00000044);
799 nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb);
800 nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb);
801 nbmc_write_index(nb_dev, 0xba, 0x55555555);
802 nbmc_write_index(nb_dev, 0xc1, 0x00000000);
803 nbmc_write_index(nb_dev, 0xc2, 0x00000000);
804 nbmc_write_index(nb_dev, 0xc3, 0x80006b00);
805 nbmc_write_index(nb_dev, 0xc4, 0x00066664);
806 nbmc_write_index(nb_dev, 0xc5, 0x00000000);
807 nbmc_write_index(nb_dev, 0xd2, 0x00000022);
808 nbmc_write_index(nb_dev, 0xd3, 0x00000044);
809 nbmc_write_index(nb_dev, 0xd6, 0x00050005);
810 nbmc_write_index(nb_dev, 0xd7, 0x00000000);
811 nbmc_write_index(nb_dev, 0xd8, 0x00700070);
812 nbmc_write_index(nb_dev, 0xd9, 0x00700070);
813 nbmc_write_index(nb_dev, 0xe0, 0x00200020);
814 nbmc_write_index(nb_dev, 0xe1, 0x00200020);
815 nbmc_write_index(nb_dev, 0xe8, 0x00200020);
816 nbmc_write_index(nb_dev, 0xe9, 0x00200020);
817 nbmc_write_index(nb_dev, 0xe0, 0x00180018);
818 nbmc_write_index(nb_dev, 0xe1, 0x00180018);
819 nbmc_write_index(nb_dev, 0xe8, 0x00180018);
820 nbmc_write_index(nb_dev, 0xe9, 0x00180018);
823 /* Memory Termination. */
824 set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044);
825 set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00);
827 /* Controller Termation. */
828 set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000);
831 /* OEM Init MC. 667MHz. */
832 nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78);
833 nbmc_write_index(nb_dev, 0xa9, 0x514a2319);
834 nbmc_write_index(nb_dev, 0xaa, 0x54400520);
835 nbmc_write_index(nb_dev, 0xab, 0x441460ff);
836 nbmc_write_index(nb_dev, 0xa0, 0x20f00a48);
837 set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10);
838 nbmc_write_index(nb_dev, 0xb2, 0x00000303);
839 set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45);
841 /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
843 /* Init PM timing. */
846 l_dword = nbmc_read_index(nb_dev, 0xa0+i);
847 nbmc_write_index(nb_dev, 0xc8+i, l_dword);
851 l_dword = nbmc_read_index(nb_dev, 0xa8+i);
852 nbmc_write_index(nb_dev, 0xcc+i, l_dword);
854 l_dword = nbmc_read_index(nb_dev, 0xb1);
855 set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20));
858 /* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */
859 nbmc_write_index(nb_dev, 0x11, 0x40000000);
860 FB_Start = 0xc00 + 0x080;
861 FB_End = 0xc00 + 0x080;
862 nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4));
863 set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20);
864 nbmc_write_index(nb_dev, 0x0f, 0);
865 nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12));
868 /* GFX_InitSP finished. */
871 static struct pci_operations lops_pci = {
872 .set_subsystem = pci_dev_set_subsystem,
875 static struct device_operations pcie_ops = {
876 .read_resources = rs780_gfx_read_resources,
877 .set_resources = pci_dev_set_resources,
878 .enable_resources = pci_dev_enable_resources,
879 .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */
881 .enable = rs780_internal_gfx_enable,
882 .ops_pci = &lops_pci,
886 * We should list all of them here.
888 static const struct pci_driver pcie_driver_780 __pci_driver = {
890 .vendor = PCI_VENDOR_ID_ATI,
891 .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
894 static const struct pci_driver pcie_driver_780c __pci_driver = {
896 .vendor = PCI_VENDOR_ID_ATI,
897 .device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX,
899 static const struct pci_driver pcie_driver_780m __pci_driver = {
901 .vendor = PCI_VENDOR_ID_ATI,
902 .device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX,
904 static const struct pci_driver pcie_driver_780mc __pci_driver = {
906 .vendor = PCI_VENDOR_ID_ATI,
907 .device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX,
909 static const struct pci_driver pcie_driver_780e __pci_driver = {
911 .vendor = PCI_VENDOR_ID_ATI,
912 .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
914 static const struct pci_driver pcie_driver_785g __pci_driver = {
916 .vendor = PCI_VENDOR_ID_ATI,
917 .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX,
919 static const struct pci_driver pcie_driver_785c __pci_driver = {
921 .vendor = PCI_VENDOR_ID_ATI,
922 .device = PCI_DEVICE_ID_ATI_RS785C_INT_GFX,
924 static const struct pci_driver pcie_driver_785m __pci_driver = {
926 .vendor = PCI_VENDOR_ID_ATI,
927 .device = PCI_DEVICE_ID_ATI_RS785M_INT_GFX,
929 static const struct pci_driver pcie_driver_785mc __pci_driver = {
931 .vendor = PCI_VENDOR_ID_ATI,
932 .device = PCI_DEVICE_ID_ATI_RS785MC_INT_GFX,
934 static const struct pci_driver pcie_driver_785d __pci_driver = {
936 .vendor = PCI_VENDOR_ID_ATI,
937 .device = PCI_DEVICE_ID_ATI_RS785D_INT_GFX,
940 /* step 12 ~ step 14 from rpr */
941 static void single_port_configuration(device_t nb_dev, device_t dev)
945 struct southbridge_amd_rs780_config *cfg =
946 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
948 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n");
950 /* step 12 training, releases hold training for GFX port 0 (device 2) */
951 PcieReleasePortTraining(nb_dev, dev, 2);
952 result = PcieTrainPort(nb_dev, dev, 2);
953 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n");
955 /* step 13 Power Down Control */
956 /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
957 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
959 /* step 13.a Link Training was NOT successful */
961 set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
962 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
964 nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
966 nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
967 set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
969 } else { /* step 13.b Link Training was successful */
970 set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
971 reg32 = nbpcie_p_read_index(dev, 0x29);
972 width = reg32 & 0xFF;
973 printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
977 nbpcie_ind_write_index(nb_dev, 0x65,
978 cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
981 nbpcie_ind_write_index(nb_dev, 0x65,
982 cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
985 nbpcie_ind_write_index(nb_dev, 0x65,
986 cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
990 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n");
992 /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
993 set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
994 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n");
997 static void dual_port_configuration(device_t nb_dev, device_t dev)
1000 u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
1001 struct southbridge_amd_rs780_config *cfg =
1002 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1004 /* 5.4.1.2 Dual Port Configuration */
1005 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1006 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
1007 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1009 /* 5.7. Training for Device 2 */
1010 /* 5.7.1. Releases hold training for GFX port 0 (device 2) */
1011 PcieReleasePortTraining(nb_dev, dev, dev_ind);
1012 /* 5.7.2- 5.7.9. PCIE Link Training Sequence */
1013 result = PcieTrainPort(nb_dev, dev, dev_ind);
1015 /* Power Down Control for Device 2 */
1016 /* Link Training was NOT successful */
1018 /* Powers down all lanes for port A */
1019 /* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */
1020 /* Note: I have to disable the slot where there isnt a device,
1021 * otherwise the system will hang. I dont know why. */
1022 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
1024 } else { /* step 16.b Link Training was successful */
1025 reg32 = nbpcie_p_read_index(dev, 0xa2);
1026 width = (reg32 >> 4) & 0x7;
1027 printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
1031 nbpcie_ind_write_index(nb_dev, 0x65,
1032 cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
1035 nbpcie_ind_write_index(nb_dev, 0x65,
1036 cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
1042 /* For single port GFX configuration Only
1049 * 101 = x12 (not supported)
1052 static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
1056 struct southbridge_amd_rs780_config *cfg =
1057 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1060 reg32 = nbpcie_p_read_index(dev, 0xa2);
1063 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
1065 set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
1067 set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
1069 if (0 == cfg->gfx_reconfiguration)
1070 set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
1074 reg32 = nbpcie_p_read_index(dev, 0xa2);
1076 while (reg32 & 0x100);
1079 sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
1081 reg32 = pci_ext_read_config32(nb_dev, sb_dev,
1082 PCIE_VC0_RESOURCE_STATUS);
1083 } while (reg32 & VC_NEGOTIATION_PENDING);
1086 reg32 = nbpcie_p_read_index(dev, 0xa2);
1087 if (((reg32 & 0x70) >> 4) != 0x6) {
1088 /* the unused lanes should be powered off. */
1092 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
1096 * GFX Core initialization, dev2, dev3
1098 void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
1101 struct southbridge_amd_rs780_config *cfg =
1102 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1104 printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
1107 /* GFX Core Initialization */
1108 //if (port == 2) return;
1110 /* step 2, TMDS, (only need if CMOS option is enabled) */
1111 if (cfg->gfx_tmds) {
1114 #if 1 /* external clock mode */
1115 /* table 5-22, 5.9.1. REFCLK */
1116 /* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
1117 * REFCLK PAD can be driven by an external source. */
1118 /* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
1119 set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28);
1121 /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1122 /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1123 /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1124 set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1125 1 << 6 | 1 << 8 | 1 << 10);
1126 reg32 = nbmisc_read_index(nb_dev, 0x28);
1127 printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1129 /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1130 set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
1131 #else /* internal clock mode */
1132 /* table 5-23, 5.9.1. REFCLK */
1133 /* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX
1134 * REFCLK PAD can be driven by the SB REFCLK. */
1135 /* 5.9.1.2. Disables GFX REFCLK receiver from receiving the
1136 * REFCLK from an external source.*/
1137 set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28);
1139 /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1140 /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1141 /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1142 set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1144 reg32 = nbmisc_read_index(nb_dev, 0x28);
1145 printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1147 /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1148 set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
1151 /* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */
1152 /* 5.9.3.1. Increases PLL BW for 6G operation.*/
1153 /* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */
1156 /* step 5.9.4, reset the GFX link */
1157 /* step 5.9.4.1 asserts both calibration reset and global reset */
1158 set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
1160 /* step 5.9.4.2 de-asserts calibration reset */
1161 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
1163 /* step 5.9.4.3 wait for at least 200us */
1166 /* step 5.9.4.4 de-asserts global reset */
1167 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
1169 /* 5.9.5 Reset PCIE_GFX Slot */
1170 /* It is done in mainboard.c */
1175 /* step 5.9.8 program PCIE memory mapped configuration space */
1176 /* done by enable_pci_bar3() before */
1178 /* step 7 compliance state, (only need if CMOS option is enabled) */
1179 /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
1180 if (cfg->gfx_compliance) {
1181 /* force compliance */
1182 set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
1183 /* release hold training for device 2. GFX initialization is done. */
1184 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
1185 dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
1186 printk(BIOS_DEBUG, "rs780_gfx_init step7.\n");
1190 /* 5.9.12 Core Initialization. */
1191 /* 5.9.12.1 sets RCB timeout to be 25ms */
1192 /* 5.9.12.2. RCB Cpl timeout on link down. */
1193 set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
1194 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n");
1196 /* step 5.9.12.3 disables slave ordering logic */
1197 set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
1198 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n");
1200 /* step 5.9.12.4 sets DMA payload size to 64 bytes */
1201 set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
1202 /* 5.9.12.5. Blocks DMA traffic during C3 state. */
1203 set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
1205 /* 5.9.12.6. Disables RC ordering logic */
1206 set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9);
1208 /* Enabels TLP flushing. */
1209 /* Note: It is got from RS690. The system will hang without this action. */
1210 set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
1212 /* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */
1213 set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0);
1215 /* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */
1216 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1218 /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
1219 set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
1220 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n");
1222 /* 5.9.12.10 Sets the timer in Config state from 20us to */
1223 /* 5.9.12.11 De-asserts RX_EN in L0s. */
1224 /* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock
1225 * recovery parameter when lane is in electrical idle in L0s.*/
1226 set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28);
1228 /* 5.9.12.13. Turns off offset calibration. */
1229 /* 5.9.12.14. Enables Rx Clock gating in CDR */
1230 set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */);
1232 /* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */
1233 set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4);
1235 /* 5.9.12.16. Lets PI use Electrical Idle from PHY when
1236 * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */
1237 set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14);
1239 /* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */
1240 set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
1242 /* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already
1243 * acknowledged a request to go to L1. */
1244 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1246 /* 5.9.12.19. LDSK only taking deskew on deskewing error detect */
1247 set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28);
1249 /* 5.9.12.20. Bypasses lane de-skew logic if in x1 */
1250 set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14);
1252 /* 5.9.12.21. Sets Electrical Idle Threshold. */
1253 set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21);
1255 /* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier
1256 * Only if CMOS Option in section. skip */
1258 /* 5.9.12.23. Disables GEN2 capability of the device. */
1259 set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
1261 /* 5.9.12.24.Disables advertising Upconfigure Support. */
1262 set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
1264 /* 5.9.12.25. No comment in RPR. */
1265 set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10);
1267 /* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link
1268 * speed are supported */
1269 set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0);
1271 /* 5.9.12.27. Enables NVG86 ECO. A13 above only. */
1272 if (get_nb_rev(nb_dev) == REV_RS780_A12) /* A12 */
1273 set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11);
1275 /* 5.9.12.28 Hides and disables the completion timeout method. */
1276 set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2);
1278 /* 5.9.12.29. Use the bif_core de-emphasis strength by default. */
1279 /* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */
1281 /* 5.9.12.30. Set TX arbitration algorithm to round robin */
1282 set_pcie_enable_bits(nb_dev, 0x1C,
1283 1 << 0 | 0x1F << 1 | 0x1F << 6,
1284 1 << 0 | 0x04 << 1 | 0x04 << 6);
1286 /* Single-port/Dual-port configureation. */
1287 switch (cfg->gfx_dual_slot) {
1289 /* step 1, lane reversal (only need if build config option is enabled) */
1290 if (cfg->gfx_lane_reversal) {
1291 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1292 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1293 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1295 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1297 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1298 if((dev->path.pci.devfn >> 3) == 2) {
1299 single_port_configuration(nb_dev, dev);
1301 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1302 printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3
1307 /* step 1, lane reversal (only need if build config option is enabled) */
1308 if (cfg->gfx_lane_reversal) {
1309 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1310 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1311 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1312 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1314 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1315 /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1316 /* AMD calls the configuration CrossFire */
1317 set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1318 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1320 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1321 dual_port_configuration(nb_dev, dev);
1325 if(is_dev3_present()){
1326 /* step 1, lane reversal (only need if CMOS option is enabled) */
1327 if (cfg->gfx_lane_reversal) {
1328 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1329 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1330 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1331 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1333 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1334 /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1335 /* AMD calls the configuration CrossFire */
1336 set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1337 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1340 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1341 dual_port_configuration(nb_dev, dev);
1344 if (cfg->gfx_lane_reversal) {
1345 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1346 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1347 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1349 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1351 if((dev->path.pci.devfn >> 3) == 2)
1352 single_port_configuration(nb_dev, dev);
1354 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1355 printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
1361 printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");