src/southbridge/amd/rs780/gfx.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /*
  21  *  for rs780 internal graphics device
  22  *  device id of internal grphics:
  23  *      RS780:  0x9610
  24  *      RS780C: 0x9611
  25  *      RS780M: 0x9612
  26  *      RS780MC:0x9613
  27  *      RS780E: 0x9615
  28  *      RS785G: 0x9710 - just works, not much tested
  29  *      RS785C: 0x9711
  30  *      RS785M: 0x9712
  31  *      RS785MC:0x9713
  32  *      RS785D: 0x9714
  33  */
  34 #include <console/console.h>
  35 #include <device/device.h>
  36 #include <device/pci.h>
  37 #include <device/pci_ids.h>
  38 #include <device/pci_ops.h>
  39 #include <delay.h>
  40 #include <cpu/x86/msr.h>
  41 #include "rs780.h"
  42 extern int is_dev3_present(void);
  43 void set_pcie_reset(void);
  44 void set_pcie_dereset(void);
  45
  46 extern uint64_t uma_memory_base, uma_memory_size;
  47
  48 /* Trust the original resource allocation. Don't do it again. */
  49 #undef DONT_TRUST_RESOURCE_ALLOCATION
  50 //#define DONT_TRUST_RESOURCE_ALLOCATION
  51
  52 #define CLK_CNTL_INDEX  0x8
  53 #define CLK_CNTL_DATA   0xC
  54
  55 /* The Integrated Info Table. */
  56 ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
  57
  58 #ifdef UNUSED_CODE
  59 static u32 clkind_read(device_t dev, u32 index)
  60 {
  61         u32     gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
  62
  63         *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
  64         return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
  65 }
  66 #endif
  67
  68 static void clkind_write(device_t dev, u32 index, u32 data)
  69 {
  70         u32     gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
  71         /* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */
  72
  73         *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
  74         *(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
  75 }
  76
  77 /*
  78 * pci_dev_read_resources thinks it is a IO type.
  79 * We have to force it to mem type.
  80 */
  81 static void rs780_gfx_read_resources(device_t dev)
  82 {
  83         printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n");
  84
  85         /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
  86            Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
  87            which tells us it is a memory address base.
  88          */
  89         pci_write_config32(dev, 0x24, 0x00000000);
  90
  91         /* Get the normal pci resources of this device */
  92         pci_dev_read_resources(dev);
  93         compact_resources(dev);
  94 }
  95
  96 typedef struct _MMIORANGE
  97 {
  98         u32     Base;
  99         u32     Limit;
 100         u8      Attribute;
 101 } MMIORANGE;
 102
 103 MMIORANGE MMIO[8], CreativeMMIO[8];
 104
 105 #define CIM_STATUS u32
 106 #define CIM_SUCCESS 0x00000000
 107 #define CIM_ERROR       0x80000000
 108 #define CIM_UNSUPPORTED 0x80000001
 109 #define CIM_DISABLEPORT 0x80000002
 110
 111 #define MMIO_ATTRIB_NP_ONLY     1
 112 #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
 113 #define MMIO_ATTRIB_SKIP_ZERO 1<<2
 114
 115 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
 116 static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
 117 {
 118         int i;
 119         for (i=0; i<8; i++) {
 120                 if (pMMIO[i].Limit == 0)
 121                                 return &pMMIO[i];
 122         }
 123         return 0;
 124 }
 125
 126 static void FreeMMIO(MMIORANGE* pMMIO)
 127 {
 128         pMMIO->Base = 0;
 129         pMMIO->Limit = 0;
 130 }
 131
 132 static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 133 {
 134         int i;
 135         MMIORANGE * TempRange;
 136         for(i=0; i<8; i++)
 137         {
 138                 if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
 139                 {
 140                         TempRange = AllocMMIO(pMMIO);
 141                         if(TempRange == 0) return 0x80000000;
 142                         TempRange->Base = Limit;
 143                         TempRange->Limit = pMMIO[i].Limit;
 144                         TempRange->Attribute = pMMIO[i].Attribute;
 145                         pMMIO[i].Limit = Base;
 146                 }
 147         }
 148         TempRange = AllocMMIO(pMMIO);
 149         if(TempRange == 0) return 0x80000000;
 150         TempRange->Base = Base;
 151         TempRange->Limit = Limit;
 152         TempRange->Attribute = Attribute;
 153         return 0;
 154 }
 155
 156 static u8 FinalizeMMIO(MMIORANGE *pMMIO)
 157 {
 158         int i, j, n = 0;
 159         for(i=0; i<8; i++)
 160         {
 161                 if (pMMIO[i].Base == pMMIO[i].Limit)
 162                 {
 163                         FreeMMIO(&pMMIO[i]);
 164                         continue;
 165                 }
 166                 for(j=0; j<i; j++)
 167                 {
 168                         if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
 169                         {
 170                                 if (pMMIO[i].Base == pMMIO[j].Limit)
 171                                 {
 172                                         pMMIO[j].Limit = pMMIO[i].Limit;
 173                                          FreeMMIO(&pMMIO[i]);
 174                                 }
 175                                 if (pMMIO[i].Limit == pMMIO[j].Base)
 176                                 {
 177                                         pMMIO[j].Base = pMMIO[i].Base;
 178                                    FreeMMIO(&pMMIO[i]);
 179                                 }
 180                         }
 181                 }
 182         }
 183         for (i=0; i<8; i++)
 184         {
 185                 if (pMMIO[i].Limit != 0) n++;
 186         }
 187         return n;
 188 }
 189
 190 static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 191 {
 192         CIM_STATUS Status = CIM_UNSUPPORTED;
 193         u8 Bus, Dev, Reg, BusStart, BusEnd;
 194         u32     Value;
 195         device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
 196         device_t tempdev;
 197         Value = pci_read_config32(dev0x14, 0x18);
 198         BusStart = (Value >> 8) & 0xFF;
 199         BusEnd = (Value >> 16) & 0xFF;
 200         for(Bus = BusStart; Bus <= BusEnd; Bus++)
 201         {
 202                 for(Dev = 0; Dev <= 0x1f; Dev++)
 203                 {
 204                         tempdev = dev_find_slot(Bus, Dev << 3);
 205                         Value = pci_read_config32(tempdev, 0);
 206                         printk(BIOS_DEBUG, "Dev ID %x \n", Value);
 207                         if((Value & 0xffff) == 0x1102)
 208                         {//Creative
 209                                 //Found Creative SB
 210                                 u32     MMIOStart = 0xffffffff;
 211                                 u32 MMIOLimit = 0;
 212                                 for(Reg = 0x10; Reg < 0x20; Reg+=4)
 213                                 {
 214                                         u32     BaseA, LimitA;
 215                                         BaseA = pci_read_config32(tempdev, Reg);
 216                                         Value = BaseA;
 217                                         if(!(Value & 0x01))
 218                                         {
 219                                                 Value = Value & 0xffffff00;
 220                                                 if(Value !=  0)
 221                                                 {
 222                                                         if(MMIOStart > Value)
 223                                                                 MMIOStart = Value;
 224                                                         LimitA = 0xffffffff;
 225                                                         //WritePCI(PciAddress,AccWidthUint32,&LimitA);
 226                                                         pci_write_config32(tempdev, Reg, LimitA);
 227                                                         //ReadPCI(PciAddress,AccWidthUint32,&LimitA);
 228                                                         LimitA = pci_read_config32(tempdev, Reg);
 229                                                         LimitA = Value + (~LimitA + 1);
 230                                                         //WritePCI(PciAddress,AccWidthUint32,&BaseA);
 231                                                         pci_write_config32(tempdev, Reg, BaseA);
 232                                                         if (LimitA > MMIOLimit)
 233                                                                 MMIOLimit = LimitA;
 234                                                 }
 235                                         }
 236                                 }
 237                                 printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
 238                                 if (MMIOStart < MMIOLimit)
 239                                 {
 240                                         Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
 241                                         if(Status == CIM_ERROR) return Status;
 242                                 }
 243                         }
 244                 }
 245         }
 246         if(Status == CIM_SUCCESS)
 247         {
 248                 //Lets optimize MMIO
 249                 if(FinalizeMMIO(pMMIO) > 4)
 250                 {
 251                         Status = CIM_ERROR;
 252                 }
 253         }
 254
 255         return Status;
 256 }
 257
 258 static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
 259 {
 260         int i, j, n = 7;
 261         device_t k8_f1;
 262
 263         k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 264
 265         for(i = 0; i < 8; i++)
 266         {
 267                 int k = 0, MmioReg;
 268                 u32 Base = 0;
 269                 u32 Limit = 0;
 270                 for(j = 0; j < 8; j++)
 271                 {
 272                         if (Base < pMMIO[j].Base)
 273                         {
 274                                 Base = pMMIO[j].Base;
 275                                 k = j;
 276                         }
 277                 }
 278                 if(pMMIO[k].Limit != 0)
 279                 {
 280                         if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
 281                         {
 282                                 Base = 0;
 283                         }
 284                         else
 285                         {
 286                                 Base = pMMIO[k].Base | 0x3;
 287                                 Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4);
 288                         }
 289                         FreeMMIO(&pMMIO[k]);
 290                 }
 291                 if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue;
 292                 MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n);
 293                 n--;
 294                 //RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0);
 295                 pci_write_config32(k8_f1, 0x80+MmioReg*8, 0);
 296
 297                 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit);
 298                 pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit);
 299
 300                 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base);
 301                 pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
 302         }
 303 }
 304 #endif
 305
 306 #define GFX_CONFIG_DDI1         0x04
 307 #define GFX_CONFIG_DDI2         0x08
 308 #define GFX_CONFIG_DDI          (GFX_CONFIG_DDI1 | GFX_CONFIG_DDI2)
 309
 310 /**
 311  * Force poweron pads for lanes used for DDI
 312  * reference CIMx PCIEL_PowerOnDDILanes()
 313  *
 314  * Inactive    B_PRX_PDNB_FDIS  B_PTX_PDNB_FDIS
 315  *  Lanes
 316  * Lanes  0-1   Bit  8           Bit 0
 317  * Lanes  2-3   Bit  9           Bit 1
 318  * Lanes  4-5   Bit 10           Bit 2
 319  * Lanes  6-7   Bit 11           Bit 3
 320  * Lanes  8-9   Bit 12           Bit 4
 321  * Lanes 10-11  Bit 13           Bit 5
 322  * Lanes 12-13  Bit 14           Bit 6
 323  * Lanes 14-15  Bit 15           Bit 7
 324  */
 325 static void poweron_ddi_lanes(device_t nb_dev)
 326 {
 327         u8 i;
 328         u32 gfx_cfg = 0;
 329         u32 ddi_pads = 0;
 330
 331         ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */
 332         gfx_cfg = nbmisc_read_index(nb_dev, 0x74);
 333         for (i = 0; i < 3 ; i++) {
 334                 if (gfx_cfg & GFX_CONFIG_DDI) {
 335                         ddi_pads |= (3 << (i * 2));
 336                 }
 337                 gfx_cfg >>= 8;
 338         }
 339         ddi_pads |= ddi_pads << 8; /* both TX and RX */
 340         nbpcie_ind_write_index(nb_dev, 0x65, ~ddi_pads);
 341 }
 342
 343 static void internal_gfx_pci_dev_init(struct device *dev)
 344 {
 345         unsigned char * bpointer;
 346         volatile u32 * GpuF0MMReg;
 347         volatile u32 * pointer;
 348         int i;
 349         u16 command;
 350         u32 value;
 351         u16 deviceid, vendorid;
 352         device_t nb_dev = dev_find_slot(0, 0);
 353         device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 354         device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 355         static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
 356         static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
 357         static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
 358         static const u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800};
 359
 360         /* We definetely will use this in future. Just leave it here. */
 361         /*struct southbridge_amd_rs780_config *cfg =
 362            (struct southbridge_amd_rs780_config *)dev->chip_info;*/
 363
 364         deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
 365         vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
 366         printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
 367              deviceid, vendorid);
 368
 369         command = pci_read_config16(dev, 0x04);
 370         command |= 0x7;
 371         pci_write_config16(dev, 0x04, command);
 372
 373         /* Clear vgainfo. */
 374         bpointer = (unsigned char *) &vgainfo;
 375         for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
 376         {
 377                 *bpointer = 0;
 378                 bpointer++;
 379         }
 380
 381         GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18);
 382
 383         /* GFX_InitFBAccess. */
 384         value = nbmc_read_index(nb_dev, 0x10);
 385         *(GpuF0MMReg + 0x2000/4) = 0x11;
 386         *(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
 387         *(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
 388         *(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
 389         *(GpuF0MMReg + 0xF774/4) = 0xffffffff;
 390         *(GpuF0MMReg + 0xF770/4) = 0x00000001;
 391         *(GpuF0MMReg + 0x2000/4) = 0x00000011;
 392         *(GpuF0MMReg + 0x200c/4) = 0x00000020;
 393         *(GpuF0MMReg + 0x2010/4) = 0x10204810;
 394         *(GpuF0MMReg + 0x2010/4) = 0x00204810;
 395         *(GpuF0MMReg + 0x2014/4) = 0x10408810;
 396         *(GpuF0MMReg + 0x2014/4) = 0x00408810;
 397         *(GpuF0MMReg + 0x2414/4) = 0x00000080;
 398         *(GpuF0MMReg + 0x2418/4) = 0x84422415;
 399         *(GpuF0MMReg + 0x2418/4) = 0x04422415;
 400         *(GpuF0MMReg + 0x5490/4) = 0x00000001;
 401         *(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
 402         /* Force allow LDT_STOP Cool'n'Quiet workaround. */
 403         *(GpuF0MMReg + 0x655c/4) |= 1<<4;
 404
 405         // disable write combining, needed for stability
 406         // reference bios does this only for RS780 rev A11
 407         // need to figure out why we need it for all revs
 408         *(GpuF0MMReg + 0x2000/4) = 0x00000010;
 409         *(GpuF0MMReg + 0x2408/4) = 1 << 9;
 410         *(GpuF0MMReg + 0x2000/4) = 0x00000011;
 411
 412         /* GFX_InitFBAccess finished. */
 413
 414 #if (CONFIG_GFXUMA == 1) /* for UMA mode. */
 415         /* GFX_StartMC. */
 416         set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
 417         set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
 418         set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004);
 419         set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000);
 420         set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040);
 421         set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001);
 422         set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018);
 423         set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102);
 424         set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008);
 425         set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000);
 426         /* GFX_StartMC finished. */
 427 #else
 428         /* for SP mode. */
 429         set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30);
 430         set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30);
 431         set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000);
 432         set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000);
 433         set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0);
 434         set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31);
 435         set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f);
 436         set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6);
 437         set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0);
 438         set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0);
 439         nbmc_write_index(nb_dev, 0xa4, 0x3484576f);
 440         nbmc_write_index(nb_dev, 0xa5, 0x222222df);
 441         nbmc_write_index(nb_dev, 0xa6, 0x00000000);
 442         nbmc_write_index(nb_dev, 0xa7, 0x00000000);
 443         set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0);
 444         udelay(10);
 445         set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0);
 446         udelay(10);
 447         set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2);
 448         udelay(200);
 449         set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3);
 450         set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31);
 451         udelay(500);
 452         set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31);
 453         set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30);
 454         set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0);
 455         set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29);
 456         nbmc_write_index(nb_dev, 0xa4, 0x23484576);
 457         nbmc_write_index(nb_dev, 0xa5, 0x00000000);
 458         nbmc_write_index(nb_dev, 0xa6, 0x00000000);
 459         nbmc_write_index(nb_dev, 0xa7, 0x00000000);
 460         /* GFX_StartMC finished. */
 461
 462         /* GFX_SPPowerManagment, don't care for new. */
 463         /* Post MC Init table programming. */
 464         set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b);
 465
 466         /* Do we need Write and Read Calibration? */
 467         /* GFX_Init finished. */
 468 #endif
 469
 470         /* GFX_InitIntegratedInfo. */
 471         /* fill the Integrated Info Table. */
 472         vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2);
 473         vgainfo.sHeader.ucTableFormatRevision = 1;
 474         vgainfo.sHeader.ucTableContentRevision = 2;
 475
 476 #if (CONFIG_GFXUMA == 0) /* SP mode. */
 477         // Side port support is incomplete, do not use it
 478         // These parameters must match the motherboard
 479         vgainfo.ulBootUpSidePortClock = 667*100;
 480         vgainfo.ucMemoryType = 3;  // 3=ddr3 sp mem, 2=ddr2 sp mem
 481         vgainfo.ulMinSidePortClock = 333*100;
 482 #endif
 483
 484         vgainfo.ulBootUpEngineClock = 500 * 100;                // setup option on reference BIOS, 500 is default
 485
 486         // find the DDR memory frequency
 487         if (is_family10h()) {
 488                 value = pci_read_config32(k8_f2, 0x94);         // read channel 0 DRAM Configuration High Register
 489                 if (extractbit(value, 14))                      // if channel 0 disabled, channel 1 must have memory
 490                         value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register
 491                 vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100;
 492         }
 493         if (is_family0Fh()) {
 494                 value = pci_read_config32(k8_f2, 0x94);
 495                 vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100;
 496         }
 497
 498         /* UMA Channel Number: 1 or 2. */
 499         vgainfo.ucUMAChannelNumber = 1;
 500         if (is_family0Fh()) {
 501                 value = pci_read_config32(k8_f2, 0x90);
 502         if (extractbit(value, 11))  // 128-bit mode
 503                 vgainfo.ucUMAChannelNumber = 2;
 504         }
 505         if (is_family10h()) {
 506                 u32 dch0 = pci_read_config32(k8_f2, 0x94);
 507                 u32 dch1 = pci_read_config32(k8_f2, 0x194);
 508                 if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled
 509                         value = pci_read_config32(k8_f2, 0x110);
 510                         if (extractbit(value, 4))  // ganged mode
 511                         vgainfo.ucUMAChannelNumber = 2;
 512                 }
 513         }
 514
 515         // processor type
 516         if (is_family0Fh())
 517                 vgainfo.ulCPUCapInfo = 3;
 518         if (is_family10h())
 519                 vgainfo.ulCPUCapInfo = 2;
 520
 521         /* HT speed */
 522         value = pci_read_config8(nb_dev, 0xd1);
 523         value = ht_freq_lookup [value] * 100;  // HT link frequency in MHz
 524         vgainfo.ulHTLinkFreq = value * 100;    // HT frequency in units of 100 MHz
 525         vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
 526         vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
 527
 528         if (value <= 1800)
 529                 vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
 530         else {
 531                 int sblink, cpuLnkFreqCap, nbLnkFreqCap;
 532                 value = pci_read_config32(k8_f0, 0x64);
 533                 sblink = extractbits(value, 8, 10);
 534                 cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20);
 535                 nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2);
 536                 if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable
 537                 vgainfo.ulLowVoltageHTLinkFreq = 1800*100;
 538         }
 539
 540         /* HT width. */
 541         value = pci_read_config8(nb_dev, 0xcb);
 542         vgainfo.usMinDownStreamHTLinkWidth =
 543         vgainfo.usMaxDownStreamHTLinkWidth =
 544         vgainfo.usMinUpStreamHTLinkWidth =
 545         vgainfo.usMaxUpStreamHTLinkWidth =
 546         vgainfo.usMinHTLinkWidth =
 547         vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
 548
 549         if (is_family0Fh()) {
 550                 vgainfo.usUMASyncStartDelay = 322;
 551                 vgainfo.usUMADataReturnTime = 286;
 552         }
 553
 554         if (is_family10h()) {
 555                 static u16 t0mult_lookup [] = {10, 50, 200, 2000};
 556                 int t0time, t0scale;
 557                 value = pci_read_config32(k8_f0, 0x16c);
 558                 t0time = extractbits(value, 0, 3);
 559                 t0scale = extractbits(value, 4, 5);
 560                 vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time;
 561                 vgainfo.usUMASyncStartDelay = 100;
 562                 if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz
 563                         vgainfo.usUMADataReturnTime = 300;
 564                         vgainfo.usLinkStatusZeroTime = 6 * 100;   // 6us for GH in HT1 mode
 565                 }
 566                 else {
 567                         int lssel;
 568                         value = pci_read_config32(nb_dev, 0xac);
 569                         lssel = extractbits (value, 7, 8);
 570                         vgainfo.usUMADataReturnTime = 1300;
 571                         if (lssel == 0) vgainfo.usUMADataReturnTime = 150;
 572                 }
 573         }
 574
 575         /* Poweron DDI Lanes */
 576         poweron_ddi_lanes(nb_dev);
 577
 578         printk(BIOS_DEBUG,"vgainfo:\n"
 579                         "  ulBootUpEngineClock:%lu \n"
 580                         "  ulBootUpUMAClock:%lu \n"
 581                         "  ulBootUpSidePortClock:%lu \n"
 582                         "  ulMinSidePortClock:%lu \n"
 583                         "  ulSystemConfig:%lu \n"
 584                         "  ulBootUpReqDisplayVector:%lu \n"
 585                         "  ulOtherDisplayMisc:%lu \n"
 586                         "  ulDDISlot1Config:%lu \n"
 587                         "  ulDDISlot2Config:%lu \n"
 588
 589                         "  ucMemoryType:%u \n"
 590                         "  ucUMAChannelNumber:%u \n"
 591                         "  ucDockingPinBit:%u \n"
 592                         "  ucDockingPinPolarity:%u \n"
 593
 594                         "  ulDockingPinCFGInfo:%lu \n"
 595                         "  ulCPUCapInfo: %lu \n"
 596
 597                         "  usNumberOfCyclesInPeriod:%hu \n"
 598                         "  usMaxNBVoltage:%hu \n"
 599                         "  usMinNBVoltage:%hu \n"
 600                         "  usBootUpNBVoltage:%hu \n"
 601
 602                         "  ulHTLinkFreq:%lu \n"
 603
 604                         "  usMinHTLinkWidth:%hu \n"
 605                         "  usMaxHTLinkWidth:%hu \n"
 606                         "  usUMASyncStartDelay:%hu \n"
 607                         "  usUMADataReturnTime:%hu \n"
 608                         "  usLinkStatusZeroTime:%hu \n"
 609
 610                         "  ulHighVoltageHTLinkFreq:%lu \n"
 611                         "  ulLowVoltageHTLinkFreq:%lu \n"
 612
 613                         "  usMaxUpStreamHTLinkWidth:%hu \n"
 614                         "  usMaxDownStreamHTLinkWidth:%hu \n"
 615                         "  usMinUpStreamHTLinkWidth:%hu \n"
 616                         "  usMinDownStreamHTLinkWidth:%hu \n",
 617
 618                         (unsigned long)vgainfo.ulBootUpEngineClock,
 619                         (unsigned long)vgainfo.ulBootUpUMAClock,
 620                         (unsigned long)vgainfo.ulBootUpSidePortClock,
 621                         (unsigned long)vgainfo.ulMinSidePortClock,
 622                         (unsigned long)vgainfo.ulSystemConfig,
 623                         (unsigned long)vgainfo.ulBootUpReqDisplayVector,
 624                         (unsigned long)vgainfo.ulOtherDisplayMisc,
 625                         (unsigned long)vgainfo.ulDDISlot1Config,
 626                         (unsigned long)vgainfo.ulDDISlot2Config,
 627
 628                         vgainfo.ucMemoryType,
 629                         vgainfo.ucUMAChannelNumber,
 630                         vgainfo.ucDockingPinBit,
 631                         vgainfo.ucDockingPinPolarity,
 632
 633                         (unsigned long)vgainfo.ulDockingPinCFGInfo,
 634                         (unsigned long)vgainfo.ulCPUCapInfo,
 635
 636                         vgainfo.usNumberOfCyclesInPeriod,
 637                         vgainfo.usMaxNBVoltage,
 638                         vgainfo.usMinNBVoltage,
 639                         vgainfo.usBootUpNBVoltage,
 640
 641                         (unsigned long)vgainfo.ulHTLinkFreq,
 642
 643                         vgainfo.usMinHTLinkWidth,
 644                         vgainfo.usMaxHTLinkWidth,
 645                         vgainfo.usUMASyncStartDelay,
 646                         vgainfo.usUMADataReturnTime,
 647                         vgainfo.usLinkStatusZeroTime,
 648
 649                         (unsigned long)vgainfo.ulHighVoltageHTLinkFreq,
 650                         (unsigned long)vgainfo.ulLowVoltageHTLinkFreq,
 651
 652                         vgainfo.usMaxUpStreamHTLinkWidth,
 653                         vgainfo.usMaxDownStreamHTLinkWidth,
 654                         vgainfo.usMinUpStreamHTLinkWidth,
 655                         vgainfo.usMinDownStreamHTLinkWidth);
 656
 657
 658         /* Transfer the Table to VBIOS. */
 659         pointer = (u32 *)&vgainfo;
 660         for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
 661         {
 662 #if (CONFIG_GFXUMA == 1)
 663                 *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
 664 #else
 665                 *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
 666 #endif
 667                 *(GpuF0MMReg+1) = *pointer++;
 668         }
 669
 670         /* GFX_InitLate. */
 671         {
 672                 u32 temp;
 673                 temp = pci_read_config8(dev, 0x4);
 674                 //temp &= ~1; /* CIM clears this bit. Strangely, I can'd. */
 675                 temp |= 1<<1|1<<2;
 676                 pci_write_config8(dev, 0x4, temp);
 677
 678                 // if the GFX debug bar is writable, then it has
 679                 // been programmed and can be safely enabled now
 680                 temp = pci_read_config32(nb_dev, 0x8c);
 681
 682                 // if bits 1 (intgfx_enable) and 9 (gfx_debug_bar_enable)
 683                 // then enable gfx debug bar (set gxf_debug_decode_enable)
 684                 if (temp & 0x202)
 685                         temp |= (1 << 10);
 686                 pci_write_config32(nb_dev, 0x8c, temp);
 687
 688         }
 689
 690 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
 691         /* NB_SetupMGMMIO. */
 692
 693         /* clear MMIO and CreativeMMIO. */
 694         bpointer = (unsigned char *)MMIO;
 695         for(i=0; i<sizeof(MMIO); i++)
 696         {
 697                 *bpointer = 0;
 698                 bpointer++;
 699         }
 700         bpointer = (unsigned char *)CreativeMMIO;
 701         for(i=0; i<sizeof(CreativeMMIO); i++)
 702         {
 703                 *bpointer = 0;
 704                 bpointer++;
 705         }
 706
 707         /* Set MMIO ranges in K8. */
 708         /* Set MMIO TOM - 4G. */
 709         SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]);
 710         /* Set MMIO for VGA Legacy FB. */
 711         SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]);
 712
 713         /* Set MMIO for non prefetchable P2P. */
 714         temp = pci_read_config32(dev0x14, 0x20);
 715         Base32 = (temp & 0x0fff0) << 8;
 716         Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
 717         if(Base32 < Limit32)
 718         {
 719                 Status = GetCreativeMMIO(&CreativeMMIO[0]);
 720                 if(Status != CIM_ERROR)
 721                         SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
 722         }
 723         /* Set MMIO for prefetchable P2P. */
 724         if(Status != CIM_ERROR)
 725         {
 726                 temp = pci_read_config32(dev0x14, 0x24);
 727
 728                 Base32 = (temp & 0x0fff0) <<8;
 729                 Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
 730                 if(Base32 < Limit32)
 731                         SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
 732         }
 733
 734         FinalizeMMIO(&MMIO[0]);
 735
 736         ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY);
 737         ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO);
 738 #endif
 739
 740         pci_dev_init(dev);
 741
 742         /* clk ind */
 743         clkind_write(dev, 0x08, 0x01);
 744         clkind_write(dev, 0x0C, 0x22);
 745         clkind_write(dev, 0x0F, 0x0);
 746         clkind_write(dev, 0x11, 0x0);
 747         clkind_write(dev, 0x12, 0x0);
 748         clkind_write(dev, 0x14, 0x0);
 749         clkind_write(dev, 0x15, 0x0);
 750         clkind_write(dev, 0x16, 0x0);
 751         clkind_write(dev, 0x17, 0x0);
 752         clkind_write(dev, 0x18, 0x0);
 753         clkind_write(dev, 0x19, 0x0);
 754         clkind_write(dev, 0x1A, 0x0);
 755         clkind_write(dev, 0x1B, 0x0);
 756         clkind_write(dev, 0x1C, 0x0);
 757         clkind_write(dev, 0x1D, 0x0);
 758         clkind_write(dev, 0x1E, 0x0);
 759         clkind_write(dev, 0x26, 0x0);
 760         clkind_write(dev, 0x27, 0x0);
 761         clkind_write(dev, 0x28, 0x0);
 762         clkind_write(dev, 0x5C, 0x0);
 763 }
 764
 765
 766 /*
 767 * Set registers in RS780 and CPU to enable the internal GFX.
 768 * Please refer to CIM source code and BKDG.
 769 */
 770
 771 static void rs780_internal_gfx_enable(device_t dev)
 772 {
 773         u32 l_dword;
 774         int i;
 775         device_t nb_dev = dev_find_slot(0, 0);
 776         msr_t sysmem;
 777
 778 #if (CONFIG_GFXUMA == 0)
 779         u32 FB_Start, FB_End;
 780 #endif
 781
 782         printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
 783
 784         /* The system top memory in 780. */
 785         sysmem = rdmsr(0xc001001a);
 786         printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
 787         pci_write_config32(nb_dev, 0x90, sysmem.lo);
 788
 789         sysmem = rdmsr(0xc001001D);
 790         printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
 791         htiu_write_index(nb_dev, 0x31, sysmem.hi);
 792         htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
 793
 794         /* Disable external GFX and enable internal GFX. */
 795         l_dword = pci_read_config32(nb_dev, 0x8c);
 796         l_dword &= ~(1<<0);
 797         l_dword |= 1<<1;
 798         pci_write_config32(nb_dev, 0x8c, l_dword);
 799
 800         /* NB_SetDefaultIndexes */
 801         pci_write_config32(nb_dev, 0x94, 0x7f);
 802         pci_write_config32(nb_dev, 0x60, 0x7f);
 803         pci_write_config32(nb_dev, 0xe0, 0);
 804
 805         /* NB_InitEarlyNB finished. */
 806
 807         /* LPC DMA Deadlock workaround? */
 808         /* GFX_InitCommon*/
 809         device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 810         l_dword = pci_read_config32(k8_f0, 0x68);
 811         l_dword &= ~(3 << 21);
 812         l_dword |= (1 << 21);
 813         pci_write_config32(k8_f0, 0x68, l_dword);
 814
 815         /* GFX_InitCommon. */
 816         nbmc_write_index(nb_dev, 0x23, 0x00c00010);
 817         set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15);
 818         set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
 819         set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
 820
 821 #if (CONFIG_GFXUMA == 1)
 822         /* GFX_InitUMA. */
 823         /* Copy CPU DDR Controller to NB MC. */
 824         device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 825         device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 826         device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
 827         for (i = 0; i < 12; i++)
 828         {
 829                 l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
 830                 nbmc_write_index(nb_dev, 0x30 + i, l_dword);
 831         }
 832
 833         l_dword = pci_read_config32(k8_f2, 0x80);
 834         nbmc_write_index(nb_dev, 0x3c, l_dword);
 835         l_dword = pci_read_config32(k8_f2, 0x94);
 836         set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16);
 837         set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
 838         l_dword = pci_read_config32(k8_f2, 0x90);
 839         set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
 840    if (is_family10h())
 841    {
 842            for (i = 0; i < 12; i++)
 843            {
 844                    l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
 845                    nbmc_write_index(nb_dev, 0x3d + i, l_dword);
 846            }
 847
 848            l_dword = pci_read_config32(k8_f2, 0x180);
 849            nbmc_write_index(nb_dev, 0x49, l_dword);
 850            l_dword = pci_read_config32(k8_f2, 0x194);
 851            set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16);
 852            set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17);
 853            l_dword = pci_read_config32(k8_f2, 0x190);
 854            set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18);
 855
 856            l_dword = pci_read_config32(k8_f2, 0x110);
 857            nbmc_write_index(nb_dev, 0x4a, l_dword);
 858            l_dword = pci_read_config32(k8_f2, 0x114);
 859            nbmc_write_index(nb_dev, 0x4b, l_dword);
 860            l_dword = pci_read_config32(k8_f4, 0x44);
 861            set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24);
 862            l_dword = pci_read_config32(k8_f1, 0x40);
 863            nbmc_write_index(nb_dev, 0x4c, l_dword);
 864            l_dword = pci_read_config32(k8_f1, 0xf0);
 865            nbmc_write_index(nb_dev, 0x4d, l_dword);
 866    }
 867
 868
 869         /* Set UMA in the 780 side. */
 870         /* UMA start address, size. */
 871         /* The UMA starts at 0xC0000000 of internal RS780 address space
 872             [31:16] addr of last byte | [31:16] addr of first byte
 873         */
 874         nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
 875         nbmc_write_index(nb_dev, 0x11, uma_memory_base);
 876         nbmc_write_index(nb_dev, 0x12, 0);
 877         nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20);
 878         /* GFX_InitUMA finished. */
 879 #else
 880         /* GFX_InitSP. */
 881         /* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */
 882
 883         /* Enable Async mode. */
 884         set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8);
 885         set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0);
 886         /* The last item in AsynchMclkTaskFileIndex. Why? */
 887         /* MC_MPLL_CONTROL2. */
 888         nbmc_write_index(nb_dev, 0x07, 0x40100028);
 889         /* MC_MPLL_DIV_CONTROL. */
 890         nbmc_write_index(nb_dev, 0x0b, 0x00000028);
 891         /* MC_MPLL_FREQ_CONTROL. */
 892         set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8);
 893         /* MC_MPLL_CONTROL3. For PM. */
 894         set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18);
 895         /* MPLL_CAL_TRIGGER. */
 896         set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0);
 897         udelay(200); /* time is long enough? */
 898         set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1);
 899         set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0);
 900         /* MCLK_SRC_USE_MPLL. */
 901         set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20);
 902
 903         /* Pre Init MC. */
 904         nbmc_write_index(nb_dev, 0x01, 0x88108280);
 905         set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200);
 906         nbmc_write_index(nb_dev, 0x04, 0x08881018);
 907         nbmc_write_index(nb_dev, 0x05, 0x000000bb);
 908         nbmc_write_index(nb_dev, 0x0c, 0x0f00001f);
 909         nbmc_write_index(nb_dev, 0xa1, 0x01f10000);
 910         /* MCA_INIT_DLL_PM. */
 911         set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24);
 912         nbmc_write_index(nb_dev, 0xa2, 0x74f20000);
 913         nbmc_write_index(nb_dev, 0xa3, 0x8af30000);
 914         nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c);
 915         nbmc_write_index(nb_dev, 0xb0, 0x88800130);
 916         nbmc_write_index(nb_dev, 0xb1, 0x00000040);
 917         nbmc_write_index(nb_dev, 0xb4, 0x41247000);
 918         nbmc_write_index(nb_dev, 0xb5, 0x00066664);
 919         nbmc_write_index(nb_dev, 0xb6, 0x00000022);
 920         nbmc_write_index(nb_dev, 0xb7, 0x00000044);
 921         nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb);
 922         nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb);
 923         nbmc_write_index(nb_dev, 0xba, 0x55555555);
 924         nbmc_write_index(nb_dev, 0xc1, 0x00000000);
 925         nbmc_write_index(nb_dev, 0xc2, 0x00000000);
 926         nbmc_write_index(nb_dev, 0xc3, 0x80006b00);
 927         nbmc_write_index(nb_dev, 0xc4, 0x00066664);
 928         nbmc_write_index(nb_dev, 0xc5, 0x00000000);
 929         nbmc_write_index(nb_dev, 0xd2, 0x00000022);
 930         nbmc_write_index(nb_dev, 0xd3, 0x00000044);
 931         nbmc_write_index(nb_dev, 0xd6, 0x00050005);
 932         nbmc_write_index(nb_dev, 0xd7, 0x00000000);
 933         nbmc_write_index(nb_dev, 0xd8, 0x00700070);
 934         nbmc_write_index(nb_dev, 0xd9, 0x00700070);
 935         nbmc_write_index(nb_dev, 0xe0, 0x00200020);
 936         nbmc_write_index(nb_dev, 0xe1, 0x00200020);
 937         nbmc_write_index(nb_dev, 0xe8, 0x00200020);
 938         nbmc_write_index(nb_dev, 0xe9, 0x00200020);
 939         nbmc_write_index(nb_dev, 0xe0, 0x00180018);
 940         nbmc_write_index(nb_dev, 0xe1, 0x00180018);
 941         nbmc_write_index(nb_dev, 0xe8, 0x00180018);
 942         nbmc_write_index(nb_dev, 0xe9, 0x00180018);
 943
 944         /* Misc options. */
 945         /* Memory Termination. */
 946         set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044);
 947         set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00);
 948 #if 0
 949         /* Controller Termation. */
 950         set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000);
 951 #endif
 952
 953         /* OEM Init MC. 667MHz. */
 954         nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78);
 955         nbmc_write_index(nb_dev, 0xa9, 0x514a2319);
 956         nbmc_write_index(nb_dev, 0xaa, 0x54400520);
 957         nbmc_write_index(nb_dev, 0xab, 0x441460ff);
 958         nbmc_write_index(nb_dev, 0xa0, 0x20f00a48);
 959         set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10);
 960         nbmc_write_index(nb_dev, 0xb2, 0x00000303);
 961         set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45);
 962         /* Do it later. */
 963         /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
 964
 965         /* Init PM timing. */
 966         for(i=0; i<4; i++)
 967         {
 968                 l_dword = nbmc_read_index(nb_dev, 0xa0+i);
 969                 nbmc_write_index(nb_dev, 0xc8+i, l_dword);
 970         }
 971         for(i=0; i<4; i++)
 972         {
 973                 l_dword = nbmc_read_index(nb_dev, 0xa8+i);
 974                 nbmc_write_index(nb_dev, 0xcc+i, l_dword);
 975         }
 976         l_dword = nbmc_read_index(nb_dev, 0xb1);
 977         set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20));
 978
 979         /* Init MC FB. */
 980         /* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */
 981         nbmc_write_index(nb_dev, 0x11, 0x40000000);
 982         FB_Start = 0xc00 + 0x080;
 983         FB_End = 0xc00 + 0x080;
 984         nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4));
 985         set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20);
 986         nbmc_write_index(nb_dev, 0x0f, 0);
 987         nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12));
 988 #endif
 989
 990         /* GFX_InitSP finished. */
 991 }
 992
 993 static struct pci_operations lops_pci = {
 994         .set_subsystem = pci_dev_set_subsystem,
 995 };
 996
 997 static struct device_operations pcie_ops = {
 998         .read_resources = rs780_gfx_read_resources,
 999         .set_resources = pci_dev_set_resources,
1000         .enable_resources = pci_dev_enable_resources,
1001         .init = internal_gfx_pci_dev_init,      /* The option ROM initializes the device. rs780_gfx_init, */
1002         .scan_bus = 0,
1003         .enable = rs780_internal_gfx_enable,
1004         .ops_pci = &lops_pci,
1005 };
1006
1007 /*
1008  * We should list all of them here.
1009  * */
1010 static const struct pci_driver pcie_driver_780 __pci_driver = {
1011         .ops = &pcie_ops,
1012         .vendor = PCI_VENDOR_ID_ATI,
1013         .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
1014 };
1015
1016 static const struct pci_driver pcie_driver_780c __pci_driver = {
1017         .ops = &pcie_ops,
1018         .vendor = PCI_VENDOR_ID_ATI,
1019         .device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX,
1020 };
1021 static const struct pci_driver pcie_driver_780m __pci_driver = {
1022         .ops = &pcie_ops,
1023         .vendor = PCI_VENDOR_ID_ATI,
1024         .device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX,
1025 };
1026 static const struct pci_driver pcie_driver_780mc __pci_driver = {
1027         .ops = &pcie_ops,
1028         .vendor = PCI_VENDOR_ID_ATI,
1029         .device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX,
1030 };
1031 static const struct pci_driver pcie_driver_780e __pci_driver = {
1032         .ops = &pcie_ops,
1033         .vendor = PCI_VENDOR_ID_ATI,
1034         .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
1035 };
1036 static const struct pci_driver pcie_driver_785g __pci_driver = {
1037         .ops = &pcie_ops,
1038         .vendor = PCI_VENDOR_ID_ATI,
1039         .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX,
1040 };
1041 static const struct pci_driver pcie_driver_785c __pci_driver = {
1042         .ops = &pcie_ops,
1043         .vendor = PCI_VENDOR_ID_ATI,
1044         .device = PCI_DEVICE_ID_ATI_RS785C_INT_GFX,
1045 };
1046 static const struct pci_driver pcie_driver_785m __pci_driver = {
1047         .ops = &pcie_ops,
1048         .vendor = PCI_VENDOR_ID_ATI,
1049         .device = PCI_DEVICE_ID_ATI_RS785M_INT_GFX,
1050 };
1051 static const struct pci_driver pcie_driver_785mc __pci_driver = {
1052         .ops = &pcie_ops,
1053         .vendor = PCI_VENDOR_ID_ATI,
1054         .device = PCI_DEVICE_ID_ATI_RS785MC_INT_GFX,
1055 };
1056 static const struct pci_driver pcie_driver_785d __pci_driver = {
1057         .ops = &pcie_ops,
1058         .vendor = PCI_VENDOR_ID_ATI,
1059         .device = PCI_DEVICE_ID_ATI_RS785D_INT_GFX,
1060 };
1061
1062 /* step 12 ~ step 14 from rpr */
1063 static void single_port_configuration(device_t nb_dev, device_t dev)
1064 {
1065         u8 result, width;
1066         u32 reg32;
1067         struct southbridge_amd_rs780_config *cfg =
1068             (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1069
1070         printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n");
1071
1072         /* step 12 training, releases hold training for GFX port 0 (device 2) */
1073         PcieReleasePortTraining(nb_dev, dev, 2);
1074         result = PcieTrainPort(nb_dev, dev, 2);
1075         printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n");
1076
1077         /* step 13 Power Down Control */
1078         /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
1079         set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
1080
1081         /* step 13.a Link Training was NOT successful */
1082         if (!result) {
1083                 set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
1084                 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
1085                 if (cfg->gfx_tmds)
1086                         nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
1087                 else {
1088                         nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
1089                         set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
1090                 }
1091         } else {                /* step 13.b Link Training was successful */
1092                 AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */
1093                 set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
1094                 reg32 = nbpcie_p_read_index(dev, 0x29);
1095                 width = reg32 & 0xFF;
1096                 printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
1097                 switch (width) {
1098                 case 1:
1099                 case 2:
1100                         nbpcie_ind_write_index(nb_dev, 0x65,
1101                                                cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
1102                         break;
1103                 case 4:
1104                         nbpcie_ind_write_index(nb_dev, 0x65,
1105                                                cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
1106                         break;
1107                 case 8:
1108                         nbpcie_ind_write_index(nb_dev, 0x65,
1109                                                cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
1110                         break;
1111                 }
1112         }
1113         printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n");
1114
1115         /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
1116         set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
1117         printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n");
1118 }
1119
1120 static void dual_port_configuration(device_t nb_dev, device_t dev)
1121 {
1122         u8 result, width;
1123         u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
1124         struct southbridge_amd_rs780_config *cfg =
1125                     (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1126
1127         /* 5.4.1.2 Dual Port Configuration */
1128         set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1129         set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
1130         set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1131
1132         /* 5.7. Training for Device 2 */
1133         /* 5.7.1. Releases hold training for GFX port 0 (device 2) */
1134         PcieReleasePortTraining(nb_dev, dev, dev_ind);
1135         /* 5.7.2- 5.7.9. PCIE Link Training Sequence */
1136         result = PcieTrainPort(nb_dev, dev, dev_ind);
1137
1138         /* Power Down Control for Device 2 */
1139         /* Link Training was NOT successful */
1140         if (!result) {
1141                 /* Powers down all lanes for port A */
1142                 /* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */
1143                 /* Note: I have to disable the slot where there isnt a device,
1144                  * otherwise the system will hang. I dont know why. */
1145                 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
1146
1147         } else {                /* step 16.b Link Training was successful */
1148                 AtiPcieCfg.PortDetect |= 1 << dev_ind;
1149                 reg32 = nbpcie_p_read_index(dev, 0xa2);
1150                 width = (reg32 >> 4) & 0x7;
1151                 printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
1152                 switch (width) {
1153                 case 1:
1154                 case 2:
1155                         nbpcie_ind_write_index(nb_dev, 0x65,
1156                                                cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
1157                         break;
1158                 case 4:
1159                         nbpcie_ind_write_index(nb_dev, 0x65,
1160                                                cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
1161                         break;
1162                 }
1163         }
1164 }
1165
1166 /* For single port GFX configuration Only
1167 * width:
1168 *       000 = x16
1169 *       001 = x1
1170 *       010 = x2
1171 *       011 = x4
1172 *       100 = x8
1173 *       101 = x12 (not supported)
1174 *       110 = x16
1175 */
1176 static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
1177 {
1178         u32 reg32;
1179         device_t sb_dev;
1180         struct southbridge_amd_rs780_config *cfg =
1181             (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1182
1183         /* step 5.9.1.1 */
1184         reg32 = nbpcie_p_read_index(dev, 0xa2);
1185
1186         /* step 5.9.1.2 */
1187         set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
1188         /* step 5.9.1.3 */
1189         set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
1190         /* step 5.9.1.4 */
1191         set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
1192         /* step 5.9.2.4 */
1193         if (0 == cfg->gfx_reconfiguration)
1194                 set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
1195
1196         /* step 5.9.1.5 */
1197         do {
1198                 reg32 = nbpcie_p_read_index(dev, 0xa2);
1199         }
1200         while (reg32 & 0x100);
1201
1202         /* step 5.9.1.6 */
1203         sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
1204         do {
1205                 reg32 = pci_ext_read_config32(nb_dev, sb_dev,
1206                                           PCIE_VC0_RESOURCE_STATUS);
1207         } while (reg32 & VC_NEGOTIATION_PENDING);
1208
1209         /* step 5.9.1.7 */
1210         reg32 = nbpcie_p_read_index(dev, 0xa2);
1211         if (((reg32 & 0x70) >> 4) != 0x6) {
1212                 /* the unused lanes should be powered off. */
1213         }
1214
1215         /* step 5.9.1.8 */
1216         set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
1217 }
1218
1219 /*
1220 * GFX Core initialization, dev2, dev3
1221 */
1222 void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
1223 {
1224         u32 reg32;
1225         struct southbridge_amd_rs780_config *cfg =
1226             (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1227
1228         printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
1229                     nb_dev, dev, port);
1230
1231         /* GFX Core Initialization */
1232         //if (port == 2) return;
1233
1234         /* step 2, TMDS, (only need if CMOS option is enabled) */
1235         if (cfg->gfx_tmds) {
1236                 /**
1237                  * PCIe Initialization for DDI.
1238                  * The VBIOS/Driver is responsible for DDI programming sequence,
1239                  * The SBIOS is responsible for programming the lane and clock muxing specific to each case.
1240                  * Refer to RPR Chapter 7: "PCIe Initialization for DDI".
1241                  * Note: This programming must be done before hold training is released.
1242                  */
1243                 switch (cfg->gfx_pcie_config) {
1244                         case 1: /* 1x16 GFX -default case, no programming required */
1245                                 break;
1246                         case 2: /* 1x8 GFX on Lanes 0-7 */
1247                         case 5: /* 1x4 GPP on Lanes 0-3 */
1248                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6); /* Disables PCIe mode on PHY Lanes  8-11 */
1249                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7); /* Disables PCIe mode on PHY Lanes 12-15 */
1250                                 break;
1251                         case 3: /* 1x8 on Lanes 8-15 */
1252                         case 7: /* 1x4 GPP on Lanes 8-11 */
1253                                 /* TXCLK */
1254                                 set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
1255                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
1256                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
1257                                 set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x0 << 0);
1258                                 /* RXCLK */
1259                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
1260                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
1261                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x2 << 12);
1262                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
1263                                 /* TX Lane Muxing */
1264                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
1265                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
1266                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
1267                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
1268                                 break;
1269                         case 4:  /* 2x8 */
1270                         case 10: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 8-11 */
1271                         case 14: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 8-11 */
1272                         case 17: /* 1x4 GPP on Lanes 0-3 and 1x8 GFX on Lanes 8-15 */
1273                                 /* Set dual slot configuration */
1274                                 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
1275                                 break;
1276                         case 9: /* PCIe 2x4 GPPs on Lanes 0-7 */
1277                         case 6: /* PCIe 1x4 GPP on Lanes 4-7 */
1278                                 /* Set dual slot configuration */
1279                                 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
1280                                 /* TXCLK */
1281                                 set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
1282                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
1283                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
1284                                 set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 0, 0x0 << 0);
1285                                 /* RXCLK */
1286                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
1287                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x1 << 10);
1288                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
1289                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x0 << 14);
1290                                 /* TX Lane Muxing */
1291                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
1292                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
1293                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7);
1294                                 break;
1295                         case 13: /* 2x4 GPPs on Lanes 8-15 */
1296                         case 8:  /* 1x4 GPP on Lanes 12-15 */
1297                                 /* Set dual slot configuration */
1298                                 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
1299                                 /* TXCLK */
1300                                 set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
1301                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
1302                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
1303                                 set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x3 << 0);
1304                                 /* RXCLK */
1305                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
1306                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x3 << 10);
1307                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
1308                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
1309                                 /* TX Lane Muxing */
1310                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
1311                                 set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
1312                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
1313                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
1314                                 break;
1315                         case 15: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 12-15 */
1316                         case 11: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 12-15 */
1317                                 /* Set dual slot configuration */
1318                                 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
1319                                 /* TXCLK */
1320                                 set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
1321                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
1322                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
1323                                 set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x1 << 0);
1324                                 /* RXCLK */
1325                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
1326                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x0 << 10);
1327                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
1328                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x3 << 14);
1329                                 /* TX Lane Muxing */
1330                                 set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
1331                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
1332                                 break;
1333                         case 16: /* 1x8 GFX on Lanes 8-15 and 1x4 GPP on Lanes 4-7 */
1334                         case 12: /* 1x4 GPP on Lanes 4-7 and 1x8 GFX on Lanes 8-15 */
1335                                 /* Set dual slot configuration */
1336                                 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
1337                                 /* TXCLK */
1338                                 set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
1339                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
1340                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
1341                                 set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 22, 0x2 << 22);
1342                                 set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x2 << 0);
1343                                 /* RXCLK */
1344                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
1345                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
1346                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
1347                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x1 << 14);
1348                                 /* TX Lane Muxing */
1349                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
1350                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
1351                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
1352                                 set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
1353                                 break;
1354                         default:
1355                                 printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
1356                                 break;
1357                 }
1358
1359                 /* DDI Configuration */
1360                 switch (cfg->gfx_ddi_config) {
1361                         case 1: /* DDI_SL lanes0-3 */
1362                                 nbmisc_write_index(nb_dev, 0x74, GFX_CONFIG_DDI);
1363                                 break;
1364                         case 2: /* DDI_SL lanes4-7 */
1365                                 nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8));
1366                                 break;
1367                         case 5: /* DDI_SL lanes0-4, lanes4-7 */
1368                                 nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
1369                                 break;
1370                         case 6: /* DDI_DL lanes0-7 */
1371                                 nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
1372                                 break;
1373                         default:
1374                                 printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
1375                                 break;
1376                 }
1377         }
1378
1379 #if 1                           /* external clock mode */
1380         /* table 5-22, 5.9.1. REFCLK */
1381         /* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
1382          * REFCLK PAD can be driven by an external source. */
1383         /* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
1384         set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28);
1385
1386         /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1387         /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1388         /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1389         reg32 = nbmisc_read_index(nb_dev, 0x28);
1390         printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1391
1392         /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1393         set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
1394 #else                           /* internal clock mode */
1395         /* table 5-23, 5.9.1. REFCLK */
1396         /* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX
1397          * REFCLK PAD can be driven by the SB REFCLK. */
1398         /* 5.9.1.2. Disables GFX REFCLK receiver from receiving the
1399          * REFCLK from an external source.*/
1400         set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28);
1401
1402         /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1403         /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1404         /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1405         set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1406                                0);
1407         reg32 = nbmisc_read_index(nb_dev, 0x28);
1408         printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1409
1410         /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1411         set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
1412 #endif
1413
1414         /* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */
1415         /* 5.9.3.1. Increases PLL BW for 6G operation.*/
1416         /* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */
1417         /* skip */
1418
1419         /* step 5.9.4, reset the GFX link */
1420         /* step 5.9.4.1 asserts both calibration reset and global reset */
1421         set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
1422
1423         /* step 5.9.4.2 de-asserts calibration reset */
1424         set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
1425
1426         /* step 5.9.4.3 wait for at least 200us */
1427         udelay(300);
1428
1429         /* step 5.9.4.4 de-asserts global reset */
1430         set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
1431
1432         /* 5.9.5 Reset PCIE_GFX Slot */
1433         /* It is done in mainboard.c */
1434         set_pcie_reset();
1435         mdelay(1);
1436         set_pcie_dereset();
1437
1438         /* step 5.9.8 program PCIE memory mapped configuration space */
1439         /* done by enable_pci_bar3() before */
1440
1441         /* step 7 compliance state, (only need if CMOS option is enabled) */
1442         /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
1443         if (cfg->gfx_compliance) {
1444                 /* force compliance */
1445                 set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
1446                 /* release hold training for device 2. GFX initialization is done. */
1447                 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
1448                 dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
1449                 printk(BIOS_DEBUG, "rs780_gfx_init step7.\n");
1450                 return;
1451         }
1452
1453         /* 5.9.12 Core Initialization. */
1454         /* 5.9.12.1 sets RCB timeout to be 25ms */
1455         /* 5.9.12.2. RCB Cpl timeout on link down. */
1456         set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
1457         printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n");
1458
1459         /* step 5.9.12.3 disables slave ordering logic */
1460         set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
1461         printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n");
1462
1463         /* step 5.9.12.4 sets DMA payload size to 64 bytes */
1464         set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
1465         /* 5.9.12.5. Blocks DMA traffic during C3 state. */
1466         set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
1467
1468         /* 5.9.12.6. Disables RC ordering logic */
1469         set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9);
1470
1471         /* Enabels TLP flushing. */
1472         /* Note: It is got from RS690. The system will hang without this action. */
1473         set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
1474
1475         /* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */
1476         set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0);
1477
1478         /* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */
1479         set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1480
1481         /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
1482         set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
1483         printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n");
1484
1485         /* 5.9.12.10 Sets the timer in Config state from 20us to */
1486         /* 5.9.12.11 De-asserts RX_EN in L0s. */
1487         /* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock
1488          * recovery parameter when lane is in electrical idle in L0s.*/
1489         set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28);
1490
1491         /* 5.9.12.13. Turns off offset calibration. */
1492         /* 5.9.12.14. Enables Rx Clock gating in CDR */
1493         set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */);
1494
1495         /* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */
1496         set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4);
1497
1498         /* 5.9.12.16. Lets PI use Electrical Idle from PHY when
1499          * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */
1500         set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14);
1501
1502         /* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */
1503         set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
1504
1505         /* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already
1506          * acknowledged a request to go to L1. */
1507         set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1508
1509         /* 5.9.12.19. LDSK only taking deskew on deskewing error detect */
1510         set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28);
1511
1512         /* 5.9.12.20. Bypasses lane de-skew logic if in x1 */
1513         set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14);
1514
1515         /* 5.9.12.21. Sets Electrical Idle Threshold. */
1516         set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21);
1517
1518         /* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier
1519          * Only if CMOS Option in section. skip */
1520
1521         /* 5.9.12.23. Disables GEN2 capability of the device. */
1522         set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
1523
1524         /* 5.9.12.24.Disables advertising Upconfigure Support. */
1525         set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
1526
1527         /* 5.9.12.25. No comment in RPR. */
1528         set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10);
1529
1530         /* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link
1531          * speed are supported */
1532         set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0);
1533
1534         /* 5.9.12.27. Enables NVG86 ECO. A13 above only. */
1535         if (get_nb_rev(nb_dev) == REV_RS780_A12)                        /* A12 */
1536                 set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11);
1537
1538         /* 5.9.12.28 Hides and disables the completion timeout method. */
1539         set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2);
1540
1541         /* 5.9.12.29. Use the bif_core de-emphasis strength by default. */
1542         /* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */
1543
1544         /* 5.9.12.30. Set TX arbitration algorithm to round robin */
1545         set_pcie_enable_bits(nb_dev, 0x1C,
1546                              1 << 0 | 0x1F << 1 | 0x1F << 6,
1547                              1 << 0 | 0x04 << 1 | 0x04 << 6);
1548
1549         /* Single-port/Dual-port configureation. */
1550         switch (cfg->gfx_dual_slot) {
1551         case 0:
1552                 /* step 1, lane reversal (only need if build config option is enabled) */
1553                 if (cfg->gfx_lane_reversal) {
1554                         set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1555                         set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1556                         set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1557                 }
1558                 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1559
1560                 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1561                 if((dev->path.pci.devfn >> 3) == 2) {
1562                         single_port_configuration(nb_dev, dev);
1563                 } else {
1564                         set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1565                         printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3
1566                 }
1567
1568                 break;
1569         case 1:
1570                 /* step 1, lane reversal (only need if build config option is enabled) */
1571                 if (cfg->gfx_lane_reversal) {
1572                         set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1573                         set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1574                         set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1575                         set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1576                 }
1577                 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1578                 /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1579                 /* AMD calls the configuration CrossFire */
1580                 set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1581                 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1582
1583                 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1584                 dual_port_configuration(nb_dev, dev);
1585                 break;
1586
1587         case 2:
1588                 if(is_dev3_present()){
1589                         /* step 1, lane reversal (only need if CMOS option is enabled) */
1590                         if (cfg->gfx_lane_reversal) {
1591                                 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1592                                 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1593                                 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1594                                 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1595                         }
1596                         printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1597                         /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1598                         /* AMD calls the configuration CrossFire */
1599                         set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1600                         printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1601
1602
1603                         printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1604                         dual_port_configuration(nb_dev, dev);
1605
1606                 }else{
1607                         if (cfg->gfx_lane_reversal) {
1608                                 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1609                                 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1610                                 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1611                         }
1612                         printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1613
1614                         if((dev->path.pci.devfn >> 3) == 2)
1615                                 single_port_configuration(nb_dev, dev);
1616                         else{
1617                                 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1618                                 printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
1619                             }
1620                 }
1621                 break;
1622
1623         default:
1624                 printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
1625                 break;
1626         }
1627 }