src/southbridge/amd/cimx/sb900/late.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #include <device/device.h>      /* device_t */
  22 #include <device/pci.h>         /* device_operations */
  23 #include <device/pci_ids.h>
  24 #include <device/smbus.h>       /* smbus_bus_operations */
  25 #include <console/console.h>    /* printk */
  26 #include "lpc.h"                /* lpc_read_resources */
  27 #include "SbPlatform.h"         /* Platfrom Specific Definitions */
  28 #include "cfg.h"                /* sb900 Cimx configuration */
  29 #include "chip.h"               /* struct southbridge_amd_cimx_sb900_config */
  30
  31
  32 /*implement in mainboard.c*/
  33 //void set_pcie_assert(void);
  34 //void set_pcie_deassert(void);
  35 void set_pcie_reset(void);
  36 void set_pcie_dereset(void);
  37
  38
  39 #ifndef _RAMSTAGE_
  40 #define _RAMSTAGE_
  41 #endif
  42 static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config
  43 static AMDSBCFG *sb_config = &sb_late_cfg;
  44
  45
  46 /**
  47  * @brief Entry point of Southbridge CIMx callout
  48  *
  49  * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
  50  *
  51  * @param[in] func      Southbridge CIMx Function ID.
  52  * @param[in] data      Southbridge Input Data.
  53  * @param[in] sb_config Southbridge configuration structure pointer.
  54  *
  55  */
  56 u32 sb900_callout_entry(u32 func, u32 data, void* config)
  57 {
  58         u32 ret = 0;
  59
  60         printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n");
  61         switch (func) {
  62         case CB_SBGPP_RESET_ASSERT:
  63                 //set_pcie_assert();
  64 //-             set_pcie_reset();
  65                 break;
  66
  67         case CB_SBGPP_RESET_DEASSERT:
  68                 //set_pcie_deassert();
  69 //-             set_pcie_dereset();
  70                 break;
  71
  72 //-     case IMC_FIRMWARE_FAIL:
  73 //-             break;
  74
  75         default:
  76                 break;
  77         }
  78
  79         printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n");
  80         return ret;
  81 }
  82
  83
  84 static struct pci_operations lops_pci = {
  85         .set_subsystem = 0,
  86 };
  87
  88 static void lpc_enable_resources(device_t dev)
  89 {
  90
  91         printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n");
  92         pci_dev_enable_resources(dev);
  93         //lpc_enable_childrens_resources(dev);
  94         printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n");
  95 }
  96
  97 static void lpc_init(device_t dev)
  98 {
  99         printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
 100         /* SB Configure HPET base and enable bit */
 101 //-     hpetInit(sb_config, &(sb_config->BuildParameters));
 102         printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
 103 }
 104
 105 static struct device_operations lpc_ops = {
 106         .read_resources = lpc_read_resources,
 107         .set_resources = lpc_set_resources,
 108         .enable_resources = lpc_enable_resources,
 109         .init = lpc_init,
 110         .scan_bus = scan_static_bus,
 111         .ops_pci = &lops_pci,
 112 };
 113
 114 static const struct pci_driver lpc_driver __pci_driver = {
 115         .ops = &lpc_ops,
 116         .vendor = PCI_VENDOR_ID_AMD,
 117         .device = PCI_DEVICE_ID_ATI_SB900_LPC,
 118 };
 119
 120
 121 static void sata_enable_resources(struct device *dev)
 122 {
 123         printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n");
 124 //-     sataInitAfterPciEnum(sb_config);
 125         pci_dev_enable_resources(dev);
 126         printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n");
 127 }
 128
 129 static void sata_init(struct device *dev)
 130 {
 131         printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n");
 132         sb_config->StdHeader.Func = SB_MID_POST_INIT;
 133 //-     AmdSbDispatcher(sb_config); //sataInitMidPost only
 134 //-     commonInitLateBoot(sb_config);
 135 //-     sataInitLatePost(sb_config);
 136         printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n");
 137 }
 138
 139 static struct device_operations sata_ops = {
 140         .read_resources = pci_dev_read_resources,
 141         .set_resources = pci_dev_set_resources,
 142         .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
 143         .init = sata_init,
 144         .scan_bus = 0,
 145         .ops_pci = &lops_pci,
 146 };
 147
 148 static const struct pci_driver sata_driver __pci_driver = {
 149         .ops = &sata_ops,
 150         .vendor = PCI_VENDOR_ID_AMD,
 151 #if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3)
 152         .device = PCI_DEVICE_ID_ATI_SB900_SATA, //SATA IDE Mode
 153 #endif
 154 #if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4)
 155         .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI,    //SATA AHCI Mode
 156 #endif
 157 #if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6)
 158         .device = PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI, //SATA AMDAHCI Mode
 159 #endif
 160 #if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0)
 161         .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID5,   //SATA RAID5 Mode
 162 #endif
 163 #if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1)
 164         .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID,    //SATA RAID Mode
 165 #endif
 166 };
 167
 168
 169 #if CONFIG_USBDEBUG
 170 static void usb_set_resources(struct device *dev)
 171 {
 172         struct resource *res;
 173         u32 base;
 174         u32 old_debug;
 175
 176         printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - Start.\n");
 177         old_debug = get_ehci_debug();
 178         set_ehci_debug(0);
 179
 180         pci_dev_set_resources(dev);
 181
 182         res = find_resource(dev, 0x10);
 183         set_ehci_debug(old_debug);
 184         if (!res)
 185                 return;
 186         base = res->base;
 187         set_ehci_base(base);
 188         report_resource_stored(dev, res, "");
 189         printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - End.\n");
 190 }
 191 #endif
 192
 193 static void usb_init(struct device *dev)
 194 {
 195         printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n");
 196 //-     usbInitAfterPciInit(sb_config);
 197 //-     commonInitLateBoot(sb_config);
 198         printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n");
 199 }
 200
 201 static struct device_operations usb_ops = {
 202         .read_resources = pci_dev_read_resources,
 203 #if CONFIG_USBDEBUG
 204         .set_resources = usb_set_resources,
 205 #else
 206         .set_resources = pci_dev_set_resources,
 207 #endif
 208         .enable_resources = pci_dev_enable_resources,
 209         .init = usb_init,
 210         .scan_bus = 0,
 211         .ops_pci = &lops_pci,
 212 };
 213
 214 /*
 215  * The pci id of usb ctrl 0 and 1 are the same.
 216  */
 217 static const struct pci_driver usb_xhci123_driver __pci_driver = {
 218         .ops = &usb_ops,
 219         .vendor = PCI_VENDOR_ID_AMD,
 220         .device = PCI_DEVICE_ID_ATI_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */
 221 };
 222
 223 static const struct pci_driver usb_ohci123_driver __pci_driver = {
 224         .ops = &usb_ops,
 225         .vendor = PCI_VENDOR_ID_AMD,
 226         .device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
 227 };
 228
 229 static const struct pci_driver usb_ehci123_driver __pci_driver = {
 230         .ops = &usb_ops,
 231         .vendor = PCI_VENDOR_ID_AMD,
 232         .device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
 233 };
 234
 235 static const struct pci_driver usb_ohci4_driver __pci_driver = {
 236         .ops = &usb_ops,
 237         .vendor = PCI_VENDOR_ID_AMD,
 238         .device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, /* OHCI-USB4 */
 239 };
 240
 241
 242 static void azalia_init(struct device *dev)
 243 {
 244         printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n");
 245 //-     azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
 246         printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n");
 247 }
 248
 249 static struct device_operations azalia_ops = {
 250         .read_resources = pci_dev_read_resources,
 251         .set_resources = pci_dev_set_resources,
 252         .enable_resources = pci_dev_enable_resources,
 253         .init = azalia_init,
 254         .scan_bus = 0,
 255         .ops_pci = &lops_pci,
 256 };
 257
 258 static const struct pci_driver azalia_driver __pci_driver = {
 259         .ops = &azalia_ops,
 260         .vendor = PCI_VENDOR_ID_AMD,
 261         .device = PCI_DEVICE_ID_ATI_SB900_HDA,
 262 };
 263
 264
 265 static void gec_init(struct device *dev)
 266 {
 267         printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n");
 268 //-     gecInitAfterPciEnum(sb_config);
 269 //-     gecInitLatePost(sb_config);
 270         printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n");
 271 }
 272
 273 static struct device_operations gec_ops = {
 274         .read_resources = pci_dev_read_resources,
 275         .set_resources = pci_dev_set_resources,
 276         .enable_resources = pci_dev_enable_resources,
 277         .init = gec_init,
 278         .scan_bus = 0,
 279         .ops_pci = &lops_pci,
 280 };
 281
 282 static const struct pci_driver gec_driver __pci_driver = {
 283         .ops = &gec_ops,
 284         .vendor = PCI_VENDOR_ID_AMD,
 285         .device = PCI_DEVICE_ID_ATI_SB900_GEC,
 286 };
 287
 288
 289 static void pcie_init(device_t dev)
 290 {
 291         printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n");
 292 //-     sbPcieGppLateInit(sb_config);
 293         printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n");
 294 }
 295
 296 static struct device_operations pci_ops = {
 297         .read_resources = pci_bus_read_resources,
 298         .set_resources = pci_dev_set_resources,
 299         .enable_resources = pci_bus_enable_resources,
 300         .init = pcie_init,
 301         .scan_bus = pci_scan_bridge,
 302         .reset_bus = pci_bus_reset,
 303         .ops_pci = &lops_pci,
 304 };
 305
 306 static const struct pci_driver pci_driver __pci_driver = {
 307         .ops = &pci_ops,
 308         .vendor = PCI_VENDOR_ID_AMD,
 309         .device = PCI_DEVICE_ID_ATI_SB900_PCI,
 310 };
 311
 312
 313 struct device_operations bridge_ops = {
 314         .read_resources   = pci_bus_read_resources,
 315         .set_resources    = pci_dev_set_resources,
 316         .enable_resources = pci_bus_enable_resources,
 317         .init             = pcie_init,
 318         .scan_bus         = pci_scan_bridge,
 319         .enable           = 0,
 320         .reset_bus        = pci_bus_reset,
 321         .ops_pci          = &lops_pci,
 322 };
 323
 324 /* 0:15:0 PCIe PortA */
 325 static const struct pci_driver PORTA_driver __pci_driver = {
 326         .ops = &bridge_ops,
 327         .vendor = PCI_VENDOR_ID_AMD,
 328         .device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
 329 };
 330
 331 /* 0:15:1 PCIe PortB */
 332 static const struct pci_driver PORTB_driver __pci_driver = {
 333         .ops = &bridge_ops,
 334         .vendor = PCI_VENDOR_ID_AMD,
 335         .device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
 336 };
 337
 338 /* 0:15:2 PCIe PortC */
 339 static const struct pci_driver PORTC_driver __pci_driver = {
 340         .ops = &bridge_ops,
 341         .vendor = PCI_VENDOR_ID_AMD,
 342         .device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
 343 };
 344
 345 /* 0:15:3 PCIe PortD */
 346 static const struct pci_driver PORTD_driver __pci_driver = {
 347         .ops = &bridge_ops,
 348         .vendor = PCI_VENDOR_ID_AMD,
 349         .device = PCI_DEVICE_ID_ATI_SB900_PCIED,
 350 };
 351
 352
 353 /**
 354  * @brief SB Cimx entry point sbBeforePciInit wrapper
 355  */
 356 static void sb900_enable(device_t dev)
 357 {
 358         u8 gpp_port = 0;
 359         struct southbridge_amd_cimx_sb900_config *sb_chip =
 360                 (struct southbridge_amd_cimx_sb900_config *)(dev->chip_info);
 361
 362         sb900_cimx_config(sb_config);
 363         printk(BIOS_DEBUG, "sb900_enable() ");
 364
 365         /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
 366 //-     commonInitEarlyBoot(sb_config);
 367 //-     commonInitEarlyPost(sb_config);
 368
 369         switch (dev->path.pci.devfn) {
 370         case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */
 371 //-             usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
 372                 break;
 373
 374         case (0x11 << 3) | 0: /* 0:11.0  SATA */
 375                 if (dev->enabled) {
 376                         sb_config->SATAMODE.SataMode.SataController = ENABLED;
 377                         if (1 == sb_chip->boot_switch_sata_ide)
 378                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 379                         else if (0 == sb_chip->boot_switch_sata_ide)
 380                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 381                 } else {
 382                         sb_config->SATAMODE.SataMode.SataController = DISABLED;
 383                 }
 384
 385 //-             sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 386                 break;
 387
 388         case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 389         case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
 390         case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
 391         case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
 392         case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
 393 //-             usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
 394                 break;
 395
 396         case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
 397                 break;
 398
 399         case (0x14 << 3) | 1: /* 0:14:1 IDE */
 400                 if (dev->enabled) {
 401                         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
 402                 } else {
 403                         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
 404                 }
 405 //-             sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 406                 break;
 407
 408         case (0x14 << 3) | 2: /* 0:14:2 HDA */
 409                 if (dev->enabled) {
 410                         if (AZALIA_DISABLE == sb_config->AzaliaController) {
 411                                 sb_config->AzaliaController = AZALIA_AUTO;
 412                         }
 413                         printk(BIOS_DEBUG, "hda enabled\n");
 414                 } else {
 415                         sb_config->AzaliaController = AZALIA_DISABLE;
 416                         printk(BIOS_DEBUG, "hda disabled\n");
 417                 }
 418 //-             azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
 419                 break;
 420
 421
 422         case (0x14 << 3) | 3: /* 0:14:3 LPC */
 423                 break;
 424
 425         case (0x14 << 3) | 4: /* 0:14:4 PCI */
 426                 break;
 427
 428         case (0x14 << 3) | 6: /* 0:14:6 GEC */
 429                 if (dev->enabled) {
 430                         sb_config->GecConfig = 0;
 431                         printk(BIOS_DEBUG, "gec enabled\n");
 432                 } else {
 433                         sb_config->GecConfig = 1;
 434                         printk(BIOS_DEBUG, "gec disabled\n");
 435                 }
 436 //-             gecInitBeforePciEnum(sb_config); // Init GEC
 437                 break;
 438
 439         case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
 440         case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
 441         case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
 442         case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
 443                 gpp_port = (dev->path.pci.devfn) & 0x03;
 444                 if (dev->enabled) {
 445                         sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
 446                 } else {
 447                         sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
 448                 }
 449
 450                 /*
 451                  * GPP_CFGMODE_X4000: PortA Lanes[3:0]
 452                  * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
 453                  * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
 454                  * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
 455                  */
 456                 if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
 457                         sb_config->GppLinkConfig = sb_chip->gpp_configuration;
 458                 }
 459
 460 //-             sbPcieGppEarlyInit(sb_config);
 461                 break;
 462
 463         default:
 464                 break;
 465         }
 466
 467         /* Special setting ABCFG registers before PCI emulation. */
 468 //-     abSpecialSetBeforePciEnum(sb_config);
 469 //-     usbDesertPll(sb_config);
 470         //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
 471         //AmdSbDispatcher(sb_config);
 472 }
 473
 474 struct chip_operations southbridge_amd_cimx_sb900_ops = {
 475         CHIP_NAME("ATI SB900")
 476         .enable_dev = sb900_enable,
 477 };