2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/hypertransport.h>
26 #include <device/pci_ids.h>
31 #include <cpu/x86/mtrr.h>
33 #include "northbridge.h"
35 static void pci_domain_read_resources(device_t dev)
37 struct resource *resource;
39 /* Initialize the system wide io space constraints */
40 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
41 resource->limit = 0xffffUL;
42 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
44 /* Initialize the system wide memory resources constraints */
45 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
46 resource->limit = 0xffffffffULL;
47 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
50 static void ram_resource(device_t dev, unsigned long index,
51 unsigned long basek, unsigned long sizek)
53 struct resource *resource;
58 resource = new_resource(dev, index);
59 resource->base = ((resource_t) basek) << 10;
60 resource->size = ((resource_t) sizek) << 10;
61 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
62 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
65 static void tolm_test(void *gp, struct device *dev, struct resource *new)
67 struct resource **best_p = gp;
68 struct resource *best;
70 if (!best || (best->base > new->base)) {
76 static u32 find_pci_tolm(struct bus *bus)
78 struct resource *min = NULL;
81 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
83 if (min && tolm > min->base) {
90 #if CONFIG_HAVE_HIGH_TABLES==1
91 /* maximum size of high tables in KB */
92 #define HIGH_TABLES_SIZE 64
93 extern uint64_t high_tables_base, high_tables_size;
96 static void pci_domain_set_resources(device_t dev)
101 unsigned long tomk, tolmk;
102 unsigned char rambits;
105 pci_tolm = find_pci_tolm(&dev->link[0]);
106 mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
108 rambits = pci_read_config8(mc_dev, 0x88);
111 /* Get memory size and frame buffer from northbridge's registers.
113 * If register contains an invalid value we set frame buffer size to a
114 * default of 32M, but that probably won't happen.
116 reg = pci_read_config8(mc_dev, 0xa1);
120 /* TOP 1M SMM Memory */
121 if (reg == 0x0 || reg == 0x6 || reg == 0x7)
122 tomk = (((rambits << 6) - 32 - 1) * 1024); // Set frame buffer 32M for default
124 tomk = (((rambits << 6) - (4 << reg) - 1) * 1024);
126 /* Compute the top of Low memory */
127 tolmk = pci_tolm >> 10;
129 /* The PCI hole does does not overlap the memory. */
131 tolmk -= 1024; // TOP 1M SM Memory
134 #if CONFIG_HAVE_HIGH_TABLES == 1
135 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
136 high_tables_size = HIGH_TABLES_SIZE* 1024;
137 printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
140 /* Report the memory regions */
143 /* TODO: Hole needed? Should this go elsewhere? */
144 ram_resource(dev, idx++, 0, 640); /* first 640k */
145 ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */
146 assign_resources(&dev->link[0]);
149 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
151 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
155 static struct device_operations pci_domain_ops = {
156 .read_resources = pci_domain_read_resources,
157 .set_resources = pci_domain_set_resources,
158 .enable_resources = enable_childrens_resources,
160 .scan_bus = pci_domain_scan_bus,
163 static void cpu_bus_init(device_t dev)
165 initialize_cpus(&dev->link[0]);
168 static void cpu_bus_noop(device_t dev)
172 static struct device_operations cpu_bus_ops = {
173 .read_resources = cpu_bus_noop,
174 .set_resources = cpu_bus_noop,
175 .enable_resources = cpu_bus_noop,
176 .init = cpu_bus_init,
180 static void enable_dev(struct device *dev)
182 /* Our wonderful device model */
183 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
184 dev->ops = &pci_domain_ops;
186 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
187 dev->ops = &cpu_bus_ops;
191 struct chip_operations northbridge_via_cx700_ops = {
192 CHIP_NAME("VIA CX700 Northbridge")
193 .enable_dev = enable_dev