2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include "../../../northbridge/intel/sch/acpi/hostbridge.asl"
24 /* PCI Device Resource Consumption */
27 Name (_HID, EISAID("PNP0C02"))
30 // This does not seem to work correctly yet - set values statically for
33 //Name (PDRS, ResourceTemplate() {
34 // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
35 // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
36 // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
37 // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
38 // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
39 // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
42 Name (PDRS, ResourceTemplate() {
43 Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
44 Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
45 Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
46 Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
47 Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
48 Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
49 Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
50 Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
53 // Current Resource Settings
54 Method (_CRS, 0, Serialized)
56 //CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
57 //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
59 //CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
60 //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
62 //CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
63 //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
65 //CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
66 //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
68 //CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
69 //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
71 //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
72 //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
78 // PCIe graphics port 0:1.0
79 #include "../../../northbridge/intel/sch/acpi/peg.asl"
81 // Integrated graphics 0:2.0
82 #include "../../../northbridge/intel/sch/acpi/igd.asl"
86 // backlight control, display switching, lid
87 #include "acpi/video.asl"