src/northbridge/intel/i3100/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 /* This code is based on src/northbridge/intel/e7520/raminit.c */
  22
  23 #include <cpu/x86/mem.h>
  24 #include <cpu/x86/mtrr.h>
  25 #include <cpu/x86/cache.h>
  26 #include "raminit.h"
  27 #include "i3100.h"
  28
  29 /* DDR2 memory controller register space */
  30 #define MCBAR 0x90000000
  31
  32 static void sdram_set_registers(const struct mem_controller *ctrl)
  33 {
  34         static const u32 register_values[] = {
  35
  36                 /* CKDIS 0x8c disable clocks */
  37         PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
  38
  39                 /* 0x9c Device present and extended RAM control
  40                  * DEVPRES is very touchy, hard code the initialization
  41                  * of PCI-E ports here.
  42                  */
  43         PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
  44
  45                 /* 0xc8 Remap RAM base and limit off */
  46         PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
  47
  48                 /* ??? */
  49         PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
  50         PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
  51
  52                 /* 0x50 scrub */
  53         PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
  54
  55                 /* 0x58 0x5c PAM */
  56         PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
  57         PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
  58
  59                 /* 0xf4 */
  60         PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
  61
  62                 /* 0x14 */
  63         PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0,
  64         };
  65         int i;
  66         int max;
  67
  68         max = sizeof(register_values)/sizeof(register_values[0]);
  69         for(i = 0; i < max; i += 3) {
  70                 device_t dev;
  71                 u32 where;
  72                 u32 reg;
  73                 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
  74                 where = register_values[i] & 0xff;
  75                 reg = pci_read_config32(dev, where);
  76                 reg &= register_values[i+1];
  77                 reg |= register_values[i+2];
  78                 pci_write_config32(dev, where, reg);
  79         }
  80         print_spew("done.\r\n");
  81 }
  82
  83 struct dimm_size {
  84         u32 side1;
  85         u32 side2;
  86 };
  87
  88 static struct dimm_size spd_get_dimm_size(u16 device)
  89 {
  90         /* Calculate the log base 2 size of a DIMM in bits */
  91         struct dimm_size sz;
  92         int value, low, ddr2;
  93         sz.side1 = 0;
  94         sz.side2 = 0;
  95
  96         /* Note it might be easier to use byte 31 here, it has the DIMM size as
  97          * a multiple of 4MB.  The way we do it now we can size both
  98          * sides of an assymetric dimm.
  99          */
 100         value = spd_read_byte(device, 3);       /* rows */
 101         if (value < 0) goto hw_err;
 102         if ((value & 0xf) == 0) goto val_err;
 103         sz.side1 += value & 0xf;
 104
 105         value = spd_read_byte(device, 4);       /* columns */
 106         if (value < 0) goto hw_err;
 107         if ((value & 0xf) == 0) goto val_err;
 108         sz.side1 += value & 0xf;
 109
 110         value = spd_read_byte(device, 17);      /* banks */
 111         if (value < 0) goto hw_err;
 112         if ((value & 0xff) == 0) goto val_err;
 113         sz.side1 += log2(value & 0xff);
 114
 115         /* Get the module data width and convert it to a power of two */
 116         value = spd_read_byte(device, 7);       /* (high byte) */
 117         if (value < 0) goto hw_err;
 118         value &= 0xff;
 119         value <<= 8;
 120
 121         low = spd_read_byte(device, 6); /* (low byte) */
 122         if (low < 0) goto hw_err;
 123         value = value | (low & 0xff);
 124         if ((value != 72) && (value != 64)) goto val_err;
 125         sz.side1 += log2(value);
 126
 127         /* side 2 */
 128         value = spd_read_byte(device, 5);       /* number of physical banks */
 129
 130         if (value < 0) goto hw_err;
 131         value &= 7;
 132         value++;
 133         if (value == 1) goto out;
 134         if (value != 2) goto val_err;
 135
 136         /* Start with the symmetrical case */
 137         sz.side2 = sz.side1;
 138
 139         value = spd_read_byte(device, 3);       /* rows */
 140         if (value < 0) goto hw_err;
 141         if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
 142         sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
 143         sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
 144
 145         value = spd_read_byte(device, 4);       /* columns */
 146         if (value < 0) goto hw_err;
 147         if ((value & 0xff) == 0) goto val_err;
 148         sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
 149         sz.side2 += ((value >> 4) & 0x0f);      /* Add in columns on side 2 */
 150         goto out;
 151
 152  val_err:
 153         die("Bad SPD value\r\n");
 154         /* If an hw_error occurs report that I have no memory */
 155  hw_err:
 156         sz.side1 = 0;
 157         sz.side2 = 0;
 158  out:
 159         return sz;
 160
 161 }
 162
 163 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 164 {
 165         int i;
 166         int cum;
 167
 168         for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 169                 struct dimm_size sz;
 170                 if (dimm_mask & (1 << i)) {
 171                         sz = spd_get_dimm_size(ctrl->channel0[i]);
 172                         if (sz.side1 < 29) {
 173                                 return -1; /* Report SPD error */
 174                         }
 175                         /* convert bits to multiples of 64MB */
 176                         sz.side1 -= 29;
 177                         cum += (1 << sz.side1);
 178                         /* DRB = 0x60 */
 179                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 180                         if( sz.side2 > 28) {
 181                                 sz.side2 -= 29;
 182                                 cum += (1 << sz.side2);
 183                         }
 184                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 185                 }
 186                 else {
 187                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 188                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 189                 }
 190         }
 191         cum >>= 1;
 192         /* set TOM top of memory 0xcc */
 193         pci_write_config16(ctrl->f0, TOM, cum);
 194         /* set TOLM top of low memory */
 195         if(cum > 0x18) {
 196                 cum = 0x18;
 197         }
 198         cum <<= 11;
 199         /* 0xc4 TOLM */
 200         pci_write_config16(ctrl->f0, TOLM, cum);
 201         return 0;
 202 }
 203
 204
 205 static u32 spd_detect_dimms(const struct mem_controller *ctrl)
 206 {
 207         u32 dimm_mask;
 208         int i;
 209         dimm_mask = 0;
 210         for(i = 0; i < DIMM_SOCKETS; i++) {
 211                 int byte;
 212                 u16 device;
 213                 device = ctrl->channel0[i];
 214                 if (device) {
 215                         byte = spd_read_byte(device, 2);  /* Type */
 216                         if (byte == 8) {
 217                                 dimm_mask |= (1 << i);
 218                         }
 219                 }
 220                 device = ctrl->channel1[i];
 221                 if (device) {
 222                         byte = spd_read_byte(device, 2);
 223                         if (byte == 8) {
 224                                 dimm_mask |= (1 << (i + DIMM_SOCKETS));
 225                         }
 226                 }
 227         }
 228         return dimm_mask;
 229 }
 230
 231
 232 static int spd_set_row_attributes(const struct mem_controller *ctrl,
 233                 long dimm_mask)
 234 {
 235         int value;
 236         int reg;
 237         int dra;
 238         int cnt;
 239
 240         dra = 0;
 241         for(cnt=0; cnt < 4; cnt++) {
 242                 if (!(dimm_mask & (1 << cnt))) {
 243                         continue;
 244                 }
 245                 reg =0;
 246                 value = spd_read_byte(ctrl->channel0[cnt], 3);  /* rows */
 247                 if (value < 0) goto hw_err;
 248                 if ((value & 0xf) == 0) goto val_err;
 249                 reg += value & 0xf;
 250
 251                 value = spd_read_byte(ctrl->channel0[cnt], 4);  /* columns */
 252                 if (value < 0) goto hw_err;
 253                 if ((value & 0xf) == 0) goto val_err;
 254                 reg += value & 0xf;
 255
 256                 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
 257                 if (value < 0) goto hw_err;
 258                 if ((value & 0xff) == 0) goto val_err;
 259                 reg += log2(value & 0xff);
 260
 261                 /* Get the device width and convert it to a power of two */
 262                 value = spd_read_byte(ctrl->channel0[cnt], 13);
 263                 if (value < 0) goto hw_err;
 264                 value = log2(value & 0xff);
 265                 reg += value;
 266                 if(reg < 27) goto hw_err;
 267                 reg -= 27;
 268                 reg += (value << 2);
 269
 270                 dra += reg << (cnt*8);
 271                 value = spd_read_byte(ctrl->channel0[cnt], 5);
 272                 if (value & 2)
 273                         dra += reg << ((cnt*8)+4);
 274         }
 275
 276         /* 0x70 DRA */
 277         pci_write_config32(ctrl->f0, DRA, dra);
 278         goto out;
 279
 280  val_err:
 281         die("Bad SPD value\r\n");
 282         /* If an hw_error occurs report that I have no memory */
 283  hw_err:
 284         dra = 0;
 285  out:
 286         return dra;
 287
 288 }
 289
 290
 291 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 292                 long dimm_mask, u32 drc)
 293 {
 294         int value;
 295         int reg;
 296         u32 drt;
 297         int cnt;
 298         int first_dimm;
 299         int cas_latency=0;
 300         int latency;
 301         u32 index = 0;
 302         u32 index2 = 0;
 303         static const u8 cycle_time[3] = { 0x75, 0x60, 0x50 };
 304         static const u8 latency_indicies[] = { 26, 23, 9 };
 305
 306         /* 0x78 DRT */
 307         drt = pci_read_config32(ctrl->f0, DRT);
 308         drt &= 3;  /* save bits 1:0 */
 309
 310         for(first_dimm = 0; first_dimm < 4; first_dimm++) {
 311                 if (dimm_mask & (1 << first_dimm))
 312                         break;
 313         }
 314
 315         drt |= (1<<6); /* back to back write turn around */
 316
 317         drt |= (3<<18);  /* Trasmax */
 318
 319         for(cnt=0; cnt < 4; cnt++) {
 320                 if (!(dimm_mask & (1 << cnt))) {
 321                         continue;
 322                 }
 323                 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 324                 /* Compute the lowest cas latency supported */
 325                 latency = log2(reg) -2;
 326
 327                 /* Loop through and find a fast clock with a low latency */
 328                 for(index = 0; index < 3; index++, latency++) {
 329                         if ((latency < 2) || (latency > 4) ||
 330                                 (!(reg & (1 << latency)))) {
 331                                 continue;
 332                         }
 333                         value = spd_read_byte(ctrl->channel0[cnt],
 334                                         latency_indicies[index]);
 335
 336                         if(value <= cycle_time[drc&3]) {
 337                                 if( latency > cas_latency) {
 338                                         cas_latency = latency;
 339                                 }
 340                                 break;
 341                         }
 342                 }
 343         }
 344         index = (cas_latency-2);
 345         if((index)==0) cas_latency = 20;
 346         else if((index)==1) cas_latency = 25;
 347         else cas_latency = 30;
 348
 349         for(cnt=0;cnt<4;cnt++) {
 350                 if (!(dimm_mask & (1 << cnt))) {
 351                         continue;
 352                 }
 353                 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
 354                 if(((index>>8)&0x0ff)<reg) {
 355                         index &= ~(0x0ff << 8);
 356                         index |= (reg << 8);
 357                 }
 358                 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
 359                 if(((index>>16)&0x0ff)<reg) {
 360                         index &= ~(0x0ff << 16);
 361                         index |= (reg<<16);
 362                 }
 363                 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
 364                 if(((index2>>0)&0x0ff)<reg) {
 365                         index2 &= ~(0x0ff << 0);
 366                         index2 |= (reg<<0);
 367                 }
 368                 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
 369                 if(((index2>>8)&0x0ff)<reg) {
 370                         index2 &= ~(0x0ff << 8);
 371                         index2 |= (reg<<8);
 372                 }
 373                 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
 374                 if(((index2>>16)&0x0ff)<reg) {
 375                         index2 &= ~(0x0ff << 16);
 376                         index2 |= (reg<<16);
 377                 }
 378         }
 379
 380         /* get dimm speed */
 381         value = cycle_time[drc&3];
 382         if(value <= 0x50) {  /* 200 MHz */
 383                 if((index&7) > 2) {
 384                         drt |= (2<<2);  /* CAS latency 4 */
 385                         cas_latency = 40;
 386                 } else {
 387                         drt |= (1<<2);  /* CAS latency 3 */
 388                         cas_latency = 30;
 389                 }
 390                 if((index&0x0ff00)<=0x03c00) {
 391                         drt |= (1<<8);  /* Trp RAS Precharg */
 392                 } else {
 393                         drt |= (2<<8);  /* Trp RAS Precharg */
 394                 }
 395
 396                 /* Trcd RAS to CAS delay */
 397                 if((index2&0x0ff)<=0x03c) {
 398                         drt |= (0<<10);
 399                 } else {
 400                         drt |= (1<<10);
 401                 }
 402
 403                 /* Tdal Write auto precharge recovery delay */
 404                 drt |= (1<<12);
 405
 406                 /* Trc TRS min */
 407                 if((index2&0x0ff00)<=0x03700)
 408                         drt |= (0<<14);
 409                 else if((index2&0xff00)<=0x03c00)
 410                         drt |= (1<<14);
 411                 else
 412                         drt |= (2<<14); /* spd 41 */
 413
 414                 drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 415
 416                 /* Trrd Row Delay */
 417                 if((index&0x0ff0000)<=0x0140000) {
 418                         drt |= (0<<20);
 419                 } else if((index&0x0ff0000)<=0x0280000) {
 420                         drt |= (1<<20);
 421                 } else if((index&0x0ff0000)<=0x03c0000) {
 422                         drt |= (2<<20);
 423                 } else {
 424                         drt |= (3<<20);
 425                 }
 426
 427                 /* Trfc Auto refresh cycle time */
 428                 if((index2&0x0ff0000)<=0x04b0000) {
 429                         drt |= (0<<22);
 430                 } else if((index2&0x0ff0000)<=0x0690000) {
 431                         drt |= (1<<22);
 432                 } else {
 433                         drt |= (2<<22);
 434                 }
 435                 /* Docs say use 55 for all 200Mhz */
 436                 drt |= (0x055<<24);
 437         }
 438         else if(value <= 0x60) { /* 167 Mhz */
 439                 /* according to new documentation CAS latency is 00
 440                  * for bits 3:2 for all 167 Mhz
 441                 drt |= ((index&3)<<2); */  /* set CAS latency */
 442                 if((index&0x0ff00)<=0x03000) {
 443                         drt |= (1<<8);  /* Trp RAS Precharg */
 444                 } else {
 445                         drt |= (2<<8);  /* Trp RAS Precharg */
 446                 }
 447
 448                 /* Trcd RAS to CAS delay */
 449                 if((index2&0x0ff)<=0x030) {
 450                         drt |= (0<<10);
 451                 } else {
 452                         drt |= (1<<10);
 453                 }
 454
 455                 /* Tdal Write auto precharge recovery delay */
 456                 drt |= (2<<12);
 457
 458                 /* Trc TRS min */
 459                 drt |= (2<<14); /* spd 41, but only one choice */
 460
 461                 drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 462
 463                 /* Trrd Row Delay */
 464                 if((index&0x0ff0000)<=0x0180000) {
 465                         drt |= (0<<20);
 466                 } else if((index&0x0ff0000)<=0x0300000) {
 467                         drt |= (1<<20);
 468                 } else {
 469                         drt |= (2<<20);
 470                 }
 471
 472                 /* Trfc Auto refresh cycle time */
 473                 if((index2&0x0ff0000)<=0x0480000) {
 474                         drt |= (0<<22);
 475                 } else if((index2&0x0ff0000)<=0x0780000) {
 476                         drt |= (2<<22);
 477                 } else {
 478                         drt |= (2<<22);
 479                 }
 480                 /* Docs state to use 99 for all 167 Mhz */
 481                 drt |= (0x099<<24);
 482         }
 483         else if(value <= 0x75) { /* 133 Mhz */
 484                 drt |= ((index&3)<<2);  /* set CAS latency */
 485                 if((index&0x0ff00)<=0x03c00) {
 486                         drt |= (1<<8);  /* Trp RAS Precharg */
 487                 } else {
 488                         drt |= (2<<8);  /* Trp RAS Precharg */
 489                 }
 490
 491                 /* Trcd RAS to CAS delay */
 492                 if((index2&0x0ff)<=0x03c) {
 493                         drt |= (0<<10);
 494                 } else {
 495                         drt |= (1<<10);
 496                 }
 497
 498                 /* Tdal Write auto precharge recovery delay */
 499                 drt |= (1<<12);
 500
 501                 /* Trc TRS min */
 502                 drt |= (2<<14); /* spd 41, but only one choice */
 503
 504                 drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 505
 506                 /* Trrd Row Delay */
 507                 if((index&0x0ff0000)<=0x01e0000) {
 508                         drt |= (0<<20);
 509                 } else if((index&0x0ff0000)<=0x03c0000) {
 510                         drt |= (1<<20);
 511                 } else {
 512                         drt |= (2<<20);
 513                 }
 514
 515                 /* Trfc Auto refresh cycle time */
 516                 if((index2&0x0ff0000)<=0x04b0000) {
 517                         drt |= (0<<22);
 518                 } else if((index2&0x0ff0000)<=0x0780000) {
 519                         drt |= (2<<22);
 520                 } else {
 521                         drt |= (2<<22);
 522                 }
 523
 524                 /* Based on CAS latency */
 525                 if(index&7)
 526                         drt |= (0x099<<24);
 527                 else
 528                         drt |= (0x055<<24);
 529
 530         }
 531         else {
 532                 die("Invalid SPD 9 bus speed.\r\n");
 533         }
 534
 535         /* 0x78 DRT */
 536         pci_write_config32(ctrl->f0, DRT, drt);
 537
 538         return(cas_latency);
 539 }
 540
 541 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 542                 long dimm_mask)
 543 {
 544         int value;
 545         int drc;
 546         int cnt;
 547         msr_t msr;
 548         u8 rate = 62;
 549         static const u8 spd_rates[6] = {15,3,7,7,62,62};
 550         static const u8 drc_rates[5] = {0,15,7,62,3};
 551         static const u8 fsb_conversion[8] = {0,1,3,2,3,0,3,3};
 552
 553         /* 0x7c DRC */
 554         drc = pci_read_config32(ctrl->f0, DRC);
 555         for(cnt=0; cnt < 4; cnt++) {
 556                 if (!(dimm_mask & (1 << cnt))) {
 557                         continue;
 558                 }
 559                 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
 560                 if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
 561
 562                 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
 563                 value &= 0x0f;    /* clip self refresh bit */
 564                 if (value > 5) goto hw_err;
 565                 if (rate > spd_rates[value])
 566                         rate = spd_rates[value];
 567
 568                 value = spd_read_byte(ctrl->channel0[cnt], 9);  /* cycle time */
 569                 if (value > 0x75) goto hw_err;
 570         }
 571         drc |= (1 << 20); /* enable ECC */
 572         for (cnt = 1; cnt < 5; cnt++)
 573                 if (drc_rates[cnt] == rate)
 574                         break;
 575         if (cnt < 5) {
 576                 drc &= ~(7 << 8);  /* clear the rate bits */
 577                 drc |= (cnt << 8);
 578         }
 579
 580         drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
 581         drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
 582         drc |= (1 << 7);
 583         drc &= ~(1 << 5); /* enable ODT */
 584         drc |= (1 << 4); /* independent clocks */
 585
 586         /* set front side bus speed */
 587         msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
 588         value = msr.lo & 0x07;
 589         drc &= ~(3 << 2);
 590         drc |= (fsb_conversion[value] << 2);
 591
 592         /* set dram type to ddr2 */
 593         drc &= ~(3 << 0);
 594         drc |= (2 << 0);
 595
 596         goto out;
 597
 598  val_err:
 599         die("Bad SPD value\r\n");
 600         /* If an hw_error occurs report that I have no memory */
 601  hw_err:
 602         drc = 0;
 603  out:
 604         return drc;
 605 }
 606
 607 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 608 {
 609         long dimm_mask;
 610
 611         /* Test if we can read the spd and if ram is ddr or ddr2 */
 612         dimm_mask = spd_detect_dimms(ctrl);
 613         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 614                 print_err("No memory for this cpu\r\n");
 615                 return;
 616         }
 617         return;
 618 }
 619
 620 static void do_delay(void)
 621 {
 622         int i;
 623         u8 b;
 624         for(i=0;i<16;i++)
 625                 b=inb(0x80);
 626 }
 627
 628 #define TIMEOUT_LOOPS 300000
 629
 630 #define DCALCSR  0x100
 631 #define DCALADDR 0x104
 632 #define DCALDATA 0x108
 633
 634 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 635 {
 636         u8 c1,c2;
 637         u32 dimm,i;
 638         u32 data32;
 639         u32 t4;
 640
 641         /* Set up northbridge values */
 642         /* ODT enable */
 643         pci_write_config32(ctrl->f0, SDRC, 0x30000000);
 644         /* Figure out which slots are Empty, Single, or Double sided */
 645         for(i=0,t4=0,c2=0;i<8;i+=2) {
 646                 c1 = pci_read_config8(ctrl->f0, DRB+i);
 647                 if(c1 == c2) continue;
 648                 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
 649                 if(c1 == c2)
 650                         t4 |= (1 << (i*4));
 651                 else
 652                         t4 |= (2 << (i*4));
 653         }
 654         for(i=0;i<1;i++) {
 655             if((t4&0x0f) == 1) {
 656                 if( ((t4>>8)&0x0f) == 0 ) {
 657                         data32 = 0x00000010; /* EEES */
 658                         break;
 659                 }
 660                 if ( ((t4>>16)&0x0f) == 0 ) {
 661                         data32 = 0x00003132; /* EESS */
 662                         break;
 663                 }
 664                 if ( ((t4>>24)&0x0f)  == 0 ) {
 665                         data32 = 0x00335566; /* ESSS */
 666                         break;
 667                 }
 668                 data32 = 0x77bbddee; /* SSSS */
 669                 break;
 670             }
 671             if((t4&0x0f) == 2) {
 672                 if( ((t4>>8)&0x0f) == 0 ) {
 673                         data32 = 0x00003132; /* EEED */
 674                         break;
 675                 }
 676                 if ( ((t4>>8)&0x0f) == 2 ) {
 677                         data32 = 0xb373ecdc; /* EEDD */
 678                         break;
 679                 }
 680                 if ( ((t4>>16)&0x0f) == 0 ) {
 681                         data32 = 0x00b3a898; /* EESD */
 682                         break;
 683                 }
 684                 data32 = 0x777becdc; /* ESSD */
 685                 break;
 686             }
 687             die("Error - First dimm slot empty\r\n");
 688         }
 689
 690         print_debug("ODT Value = ");
 691         print_debug_hex32(data32);
 692         print_debug("\r\n");
 693
 694         pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 695
 696         for(dimm=0;dimm<8;dimm+=2) {
 697
 698                 write32(MCBAR+DCALADDR, 0x0b840001);
 699                 write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
 700
 701                 for(i=0;i<1001;i++) {
 702                         data32 = read32(MCBAR+DCALCSR);
 703                         if(!(data32 & (1<<31)))
 704                                 break;
 705                 }
 706         }
 707 }
 708 static void set_receive_enable(const struct mem_controller *ctrl)
 709 {
 710         u32 i;
 711         u32 cnt;
 712         u32 recena=0;
 713         u32 recenb=0;
 714
 715         {
 716         u32 dimm;
 717         u32 edge;
 718         int32_t data32;
 719         u32 data32_dram;
 720         u32 dcal_data32_0;
 721         u32 dcal_data32_1;
 722         u32 dcal_data32_2;
 723         u32 dcal_data32_3;
 724         u32 work32l;
 725         u32 work32h;
 726         u32 data32r;
 727         int32_t recen;
 728         for(dimm=0;dimm<8;dimm+=1) {
 729
 730                 if(!(dimm&1)) {
 731                         write32(MCBAR+DCALDATA+(17*4), 0x04020000);
 732                         write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
 733
 734                         for(i=0;i<1001;i++) {
 735                                 data32 = read32(MCBAR+DCALCSR);
 736                                 if(!(data32 & (1<<31)))
 737                                         break;
 738                         }
 739                         if(i>=1000)
 740                                 continue;
 741
 742                         dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
 743                         dcal_data32_1 = read32(MCBAR+DCALDATA + 4);
 744                         dcal_data32_2 = read32(MCBAR+DCALDATA + 8);
 745                         dcal_data32_3 = read32(MCBAR+DCALDATA + 12);
 746                 }
 747                 else {
 748                         dcal_data32_0 = read32(MCBAR+DCALDATA + 16);
 749                         dcal_data32_1 = read32(MCBAR+DCALDATA + 20);
 750                         dcal_data32_2 = read32(MCBAR+DCALDATA + 24);
 751                         dcal_data32_3 = read32(MCBAR+DCALDATA + 28);
 752                 }
 753
 754                 /* check if bank is installed */
 755                 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 756                         continue;
 757                 /* Calculate the timing value */
 758                 {
 759                 u32 bit;
 760                 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
 761                         work32l=dcal_data32_1,work32h=dcal_data32_3;
 762                                 (i<4) && bit; i++) {
 763                         for(;;bit--,cnt--) {
 764                                 if(work32l & (1<<cnt))
 765                                         break;
 766                                 if(!cnt) {
 767                                         work32l = dcal_data32_0;
 768                                         work32h = dcal_data32_2;
 769                                         cnt = 32;
 770                                 }
 771                                 if(!bit) break;
 772                         }
 773                         for(;;bit--,cnt--) {
 774                                 if(!(work32l & (1<<cnt)))
 775                                         break;
 776                                 if(!cnt) {
 777                                         work32l = dcal_data32_0;
 778                                         work32h = dcal_data32_2;
 779                                         cnt = 32;
 780                                 }
 781                                 if(!bit) break;
 782                         }
 783                         if(!bit) {
 784                                 break;
 785                         }
 786                         data32 = ((bit%8) << 1);
 787                         if(work32h & (1<<cnt))
 788                                 data32 += 1;
 789                         if(data32 < 4) {
 790                                 if(!edge) {
 791                                         edge = 1;
 792                                 }
 793                                 else {
 794                                         if(edge != 1) {
 795                                                 data32 = 0x0f;
 796                                         }
 797                                 }
 798                         }
 799                         if(data32 > 12) {
 800                                 if(!edge) {
 801                                         edge = 2;
 802                                 }
 803                                 else {
 804                                         if(edge != 2) {
 805                                                 data32 = 0x00;
 806                                         }
 807                                 }
 808                         }
 809                         data32r += data32;
 810                 }
 811                 }
 812                 work32l = dcal_data32_0;
 813                 work32h = dcal_data32_2;
 814                 recen = data32r;
 815                 recen += 3;
 816                 recen = recen>>2;
 817                 for(cnt=5;cnt<24;) {
 818                         for(;;cnt++)
 819                                 if(!(work32l & (1<<cnt)))
 820                                         break;
 821                         for(;;cnt++) {
 822                                 if(work32l & (1<<cnt))
 823                                         break;
 824                         }
 825                         data32 = (((cnt-1)%8)<<1);
 826                         if(work32h & (1<<(cnt-1))) {
 827                                 data32++;
 828                         }
 829                         /* test for frame edge cross overs */
 830                         if((edge == 1) && (data32 > 12) &&
 831                             (((recen+16)-data32) < 3)) {
 832                                 data32 = 0;
 833                                 cnt += 2;
 834                         }
 835                         if((edge == 2) && (data32 < 4) &&
 836                             ((recen - data32) > 12))  {
 837                                 data32 = 0x0f;
 838                                 cnt -= 2;
 839                         }
 840                         if(((recen+3) >= data32) && ((recen-3) <= data32))
 841                                 break;
 842                 }
 843                 cnt--;
 844                 cnt /= 8;
 845                 cnt--;
 846                 if(recen&1)
 847                         recen+=2;
 848                 recen >>= 1;
 849                 recen += (cnt*8);
 850                 recen+=2;      /* this is not in the spec, but matches
 851                                  the factory output, and has less failure */
 852                 recen <<= (dimm/2) * 8;
 853                 if(!(dimm&1)) {
 854                         recena |= recen;
 855                 }
 856                 else {
 857                         recenb |= recen;
 858                 }
 859         }
 860         }
 861         /* Check for Eratta problem */
 862         for(i=cnt=0;i<32;i+=8) {
 863                 if (((recena>>i)&0x0f)>7) {
 864                         cnt+= 0x101;
 865                 }
 866                 else {
 867                         if((recena>>i)&0x0f) {
 868                                 cnt++;
 869                         }
 870                 }
 871         }
 872         if(cnt&0x0f00) {
 873                 cnt = (cnt&0x0f) - (cnt>>16);
 874                 if(cnt>1) {
 875                         for(i=0;i<32;i+=8) {
 876                                 if(((recena>>i)&0x0f)>7) {
 877                                         recena &= ~(0x0f<<i);
 878                                         recena |= (7<<i);
 879                                 }
 880                         }
 881                 }
 882                 else {
 883                         for(i=0;i<32;i+=8) {
 884                                 if(((recena>>i)&0x0f)<8) {
 885                                         recena &= ~(0x0f<<i);
 886                                         recena |= (8<<i);
 887                                 }
 888                         }
 889                 }
 890         }
 891         for(i=cnt=0;i<32;i+=8) {
 892                 if (((recenb>>i)&0x0f)>7) {
 893                         cnt+= 0x101;
 894                 }
 895                 else {
 896                         if((recenb>>i)&0x0f) {
 897                                 cnt++;
 898                         }
 899                 }
 900         }
 901         if(cnt & 0x0f00) {
 902                 cnt = (cnt&0x0f) - (cnt>>16);
 903                 if(cnt>1) {
 904                         for(i=0;i<32;i+=8) {
 905                                 if(((recenb>>i)&0x0f)>7) {
 906                                         recenb &= ~(0x0f<<i);
 907                                         recenb |= (7<<i);
 908                                 }
 909                         }
 910                 }
 911                 else {
 912                         for(i=0;i<32;i+=8) {
 913                                 if(((recenb>>8)&0x0f)<8) {
 914                                         recenb &= ~(0x0f<<i);
 915                                         recenb |= (8<<i);
 916                                 }
 917                         }
 918                 }
 919         }
 920
 921         print_debug("Receive enable A = ");
 922         print_debug_hex32(recena);
 923         print_debug(",  Receive enable B = ");
 924         print_debug_hex32(recenb);
 925         print_debug("\r\n");
 926
 927         /* clear out the calibration area */
 928         write32(MCBAR+DCALDATA+(16*4), 0x00000000);
 929         write32(MCBAR+DCALDATA+(17*4), 0x00000000);
 930         write32(MCBAR+DCALDATA+(18*4), 0x00000000);
 931         write32(MCBAR+DCALDATA+(19*4), 0x00000000);
 932
 933         /* No command */
 934         write32(MCBAR+DCALCSR, 0x0000000f);
 935
 936         write32(MCBAR+0x150, recena);
 937         write32(MCBAR+0x154, recenb);
 938 }
 939
 940
 941 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 942 {
 943         int i;
 944         int cs;
 945         int cnt;
 946         int cas_latency;
 947         long mask;
 948         u32 drc;
 949         u32 data32;
 950         u32 mode_reg;
 951         u32 *iptr;
 952         volatile u32 *iptrv;
 953         msr_t msr;
 954         u32 scratch;
 955         u8 byte;
 956         u16 data16;
 957         static const struct {
 958                 u32 clkgr[4];
 959         } gearing [] = {
 960                 /* FSB 100 */
 961         {{ 0x00000010, 0x00000000, 0x00000002, 0x00000001}},
 962                 /* FSB 133 */
 963         {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
 964                 /* FSB 167 */
 965         {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
 966                 /* N/A */
 967         {{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}},
 968         };
 969
 970         static const u32 dqs_data[] = {
 971                 0xffffffff, 0xffffffff, 0x000000ff,
 972                 0xffffffff, 0xffffffff, 0x000000ff,
 973                 0xffffffff, 0xffffffff, 0x000000ff,
 974                 0xffffffff, 0xffffffff, 0x000000ff,
 975                 0xffffffff, 0xffffffff, 0x000000ff,
 976                 0xffffffff, 0xffffffff, 0x000000ff,
 977                 0xffffffff, 0xffffffff, 0x000000ff,
 978                 0xffffffff, 0xffffffff, 0x000000ff};
 979
 980         mask = spd_detect_dimms(ctrl);
 981         print_debug("Starting SDRAM Enable\r\n");
 982
 983         /* 0x80 */
 984 #ifdef DIMM_MAP_LOGICAL
 985         pci_write_config32(ctrl->f0, DRM,
 986                 0x00410000 | DIMM_MAP_LOGICAL);
 987 #else
 988         pci_write_config32(ctrl->f0, DRM, 0x00411248);
 989 #endif
 990         /* set dram type and Front Side Bus freq. */
 991         drc = spd_set_dram_controller_mode(ctrl, mask);
 992         if( drc == 0) {
 993                 die("Error calculating DRC\r\n");
 994         }
 995         data32 = drc & ~(3 << 20);  /* clear ECC mode */
 996         data32 = data32 & ~(7 << 8);  /* clear refresh rates */
 997         data32 = data32 | (1 << 5);  /* temp turn off ODT */
 998         /* Set gearing, then dram controller mode */
 999         /* drc bits 3:2 = FSB speed */
1000         for(iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
1001                 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1002         }
1003         /* 0x7c DRC */
1004         pci_write_config32(ctrl->f0, DRC, data32);
1005
1006                 /* turn the clocks on */
1007         /* 0x8c CKDIS */
1008         pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1009
1010                 /* 0x9a DDRCSR Take subsystem out of idle */
1011         data16 = pci_read_config16(ctrl->f0, DDRCSR);
1012         data16 &= ~(7 << 12);
1013         data16 |= (1 << 12);
1014         pci_write_config16(ctrl->f0, DDRCSR, data16);
1015
1016                 /* program row size DRB */
1017         spd_set_ram_size(ctrl, mask);
1018
1019                 /* program page size DRA */
1020         spd_set_row_attributes(ctrl, mask);
1021
1022                 /* program DRT timing values */
1023         cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1024
1025         for(i=0;i<8;i+=2) { /* loop through each dimm to test */
1026                 print_debug("DIMM ");
1027                 print_debug_hex8(i);
1028                 print_debug("\r\n");
1029                 /* Apply NOP */
1030                 do_delay();
1031
1032                 write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
1033                 write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
1034
1035                 data32 = read32(MCBAR+DCALCSR);
1036                 while(data32 & 0x80000000)
1037                         data32 = read32(MCBAR+DCALCSR);
1038         }
1039
1040         /* Apply NOP */
1041         do_delay();
1042
1043         for(cs=0;cs<8;cs+=2) {
1044                 write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
1045                 data32 = read32(MCBAR+DCALCSR);
1046                 while(data32 & 0x80000000)
1047                         data32 = read32(MCBAR+DCALCSR);
1048         }
1049
1050         /* Precharg all banks */
1051         do_delay();
1052         for(cs=0;cs<8;cs+=2) {
1053                 write32(MCBAR+DCALADDR, 0x04000000);
1054                 write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1055                 data32 = read32(MCBAR+DCALCSR);
1056                 while(data32 & 0x80000000)
1057                         data32 = read32(MCBAR+DCALCSR);
1058         }
1059
1060         /* EMRS dll's enabled */
1061         do_delay();
1062         for(cs=0;cs<8;cs+=2) {
1063                 /* fixme hard code AL additive latency */
1064                 write32(MCBAR+DCALADDR, 0x0b940001);
1065                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1066                 data32 = read32(MCBAR+DCALCSR);
1067                 while(data32 & 0x80000000)
1068                         data32 = read32(MCBAR+DCALCSR);
1069         }
1070         /* MRS reset dll's */
1071         do_delay();
1072         if(cas_latency == 30)
1073                 mode_reg = 0x053a0000;
1074         else
1075                 mode_reg = 0x054a0000;
1076         for(cs=0;cs<8;cs+=2) {
1077                 write32(MCBAR+DCALADDR, mode_reg);
1078                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1079                 data32 = read32(MCBAR+DCALCSR);
1080                 while(data32 & 0x80000000)
1081                         data32 = read32(MCBAR+DCALCSR);
1082         }
1083
1084         /* Precharg all banks */
1085         do_delay();
1086         do_delay();
1087         do_delay();
1088         for(cs=0;cs<8;cs+=2) {
1089                 write32(MCBAR+DCALADDR, 0x04000000);
1090                 write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1091                 data32 = read32(MCBAR+DCALCSR);
1092                 while(data32 & 0x80000000)
1093                         data32 = read32(MCBAR+DCALCSR);
1094         }
1095
1096         /* Do 2 refreshes */
1097         do_delay();
1098         for(cs=0;cs<8;cs+=2) {
1099                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1100                 data32 = read32(MCBAR+DCALCSR);
1101                 while(data32 & 0x80000000)
1102                         data32 = read32(MCBAR+DCALCSR);
1103         }
1104         do_delay();
1105         for(cs=0;cs<8;cs+=2) {
1106                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1107                 data32 = read32(MCBAR+DCALCSR);
1108                 while(data32 & 0x80000000)
1109                         data32 = read32(MCBAR+DCALCSR);
1110         }
1111         do_delay();
1112         /* for good luck do 6 more */
1113         for(cs=0;cs<8;cs+=2) {
1114                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1115         }
1116         do_delay();
1117         for(cs=0;cs<8;cs+=2) {
1118                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1119         }
1120         do_delay();
1121         for(cs=0;cs<8;cs+=2) {
1122                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1123         }
1124         do_delay();
1125         for(cs=0;cs<8;cs+=2) {
1126                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1127         }
1128         do_delay();
1129         for(cs=0;cs<8;cs+=2) {
1130                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1131         }
1132         do_delay();
1133         for(cs=0;cs<8;cs+=2) {
1134                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1135         }
1136         do_delay();
1137         /* MRS reset dll's normal */
1138         do_delay();
1139         for(cs=0;cs<8;cs+=2) {
1140                 write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
1141                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1142                 data32 = read32(MCBAR+DCALCSR);
1143                 while(data32 & 0x80000000)
1144                         data32 = read32(MCBAR+DCALCSR);
1145         }
1146
1147         /* Do only if DDR2  EMRS dll's enabled */
1148         do_delay();
1149         for(cs=0;cs<8;cs+=2) {
1150                 write32(MCBAR+DCALADDR, (0x0b940001));
1151                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1152                 data32 = read32(MCBAR+DCALCSR);
1153                 while(data32 & 0x80000000)
1154                         data32 = read32(MCBAR+DCALCSR);
1155         }
1156
1157         do_delay();
1158         /* No command */
1159         write32(MCBAR+DCALCSR, 0x0000000f);
1160
1161         /* enable on dimm termination */
1162         set_on_dimm_termination_enable(ctrl);
1163
1164         /* receive enable calibration */
1165         set_receive_enable(ctrl);
1166
1167         /* DQS */
1168         pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
1169         for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
1170                 write32(cnt, dqs_data[i]);
1171         }
1172         pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
1173
1174         /* Enable refresh */
1175         /* 0x7c DRC */
1176         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1177         pci_write_config32(ctrl->f0, DRC, data32);
1178         write32(MCBAR+DCALCSR, 0x0008000f);
1179
1180         /* clear memory and init ECC */
1181         print_debug("Clearing memory\r\n");
1182         for(i=0;i<64;i+=4) {
1183                 write32(MCBAR+DCALDATA+i, 0x00000000);
1184         }
1185
1186         for(cs=0;cs<8;cs+=2) {
1187                 write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
1188                 data32 = read32(MCBAR+DCALCSR);
1189                 while(data32 & 0x80000000)
1190                         data32 = read32(MCBAR+DCALCSR);
1191         }
1192
1193         /* Bring memory subsystem on line */
1194         data32 = pci_read_config32(ctrl->f0, 0x98);
1195         data32 |= (1 << 31);
1196         pci_write_config32(ctrl->f0, 0x98, data32);
1197         /* wait for completion */
1198         print_debug("Waiting for mem complete\r\n");
1199         while(1) {
1200                 data32 = pci_read_config32(ctrl->f0, 0x98);
1201                 if( (data32 & (1<<31)) == 0)
1202                         break;
1203         }
1204         print_debug("Done\r\n");
1205
1206         /* Set initialization complete */
1207         /* 0x7c DRC */
1208         drc |= (1 << 29);
1209         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1210         pci_write_config32(ctrl->f0, DRC, data32);
1211
1212         /* Set the ecc mode */
1213         pci_write_config32(ctrl->f0, DRC, drc);
1214
1215         /* Enable memory scrubbing */
1216         /* 0x52 MCHSCRB */
1217         data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1218         data16 &= ~0x0f;
1219         data16 |= ((2 << 2) | (2 << 0));
1220         pci_write_config16(ctrl->f0, MCHSCRB, data16);
1221
1222         /* The memory is now setup, use it */
1223         cache_lbmem(MTRR_TYPE_WRBACK);
1224 }