src/northbridge/intel/e7525/raminit.c

   1 #include <cpu/x86/mem.h>
   2 #include <cpu/x86/mtrr.h>
   3 #include <cpu/x86/cache.h>
   4 #include "raminit.h"
   5 #include "e7525.h"
   6
   7 #define BAR 0x40000000
   8
   9 static void sdram_set_registers(const struct mem_controller *ctrl)
  10 {
  11         static const unsigned int register_values[] = {
  12
  13                 /* CKDIS 0x8c disable clocks */
  14         PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
  15
  16                 /* 0x9c Device present and extended RAM control
  17                  * DEVPRES is very touchy, hard code the initialization
  18                  * of PCI-E ports here.
  19                  */
  20         PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
  21
  22                 /* 0xc8 Remap RAM base and limit off */
  23         PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
  24
  25                 /* ??? */
  26         PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
  27         PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
  28
  29                 /* 0x50 scrub */
  30         PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
  31
  32                 /* 0x58 0x5c PAM */
  33         PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
  34         PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
  35
  36                 /* 0xf4 */
  37         PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
  38
  39                 /* 0x14 */
  40         PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
  41         };
  42         int i;
  43         int max;
  44
  45         max = sizeof(register_values)/sizeof(register_values[0]);
  46         for(i = 0; i < max; i += 3) {
  47                 device_t dev;
  48                 unsigned where;
  49                 unsigned long reg;
  50                 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
  51                 where = register_values[i] & 0xff;
  52                 reg = pci_read_config32(dev, where);
  53                 reg &= register_values[i+1];
  54                 reg |= register_values[i+2];
  55                 pci_write_config32(dev, where, reg);
  56         }
  57         print_spew("done.\r\n");
  58 }
  59
  60
  61
  62 struct dimm_size {
  63         unsigned long side1;
  64         unsigned long side2;
  65 };
  66
  67 static struct dimm_size spd_get_dimm_size(unsigned device)
  68 {
  69         /* Calculate the log base 2 size of a DIMM in bits */
  70         struct dimm_size sz;
  71         int value, low, ddr2;
  72         sz.side1 = 0;
  73         sz.side2 = 0;
  74
  75         /* test for ddr2 */
  76         ddr2=0;
  77         value = spd_read_byte(device, 2);       /* type */
  78         if (value < 0) goto hw_err;
  79         if (value == 8) ddr2 = 1;
  80
  81         /* Note it might be easier to use byte 31 here, it has the DIMM size as
  82          * a multiple of 4MB.  The way we do it now we can size both
  83          * sides of an assymetric dimm.
  84          */
  85         value = spd_read_byte(device, 3);       /* rows */
  86         if (value < 0) goto hw_err;
  87         if ((value & 0xf) == 0) goto val_err;
  88         sz.side1 += value & 0xf;
  89
  90         value = spd_read_byte(device, 4);       /* columns */
  91         if (value < 0) goto hw_err;
  92         if ((value & 0xf) == 0) goto val_err;
  93         sz.side1 += value & 0xf;
  94
  95         value = spd_read_byte(device, 17);      /* banks */
  96         if (value < 0) goto hw_err;
  97         if ((value & 0xff) == 0) goto val_err;
  98         sz.side1 += log2(value & 0xff);
  99
 100         /* Get the module data width and convert it to a power of two */
 101         value = spd_read_byte(device, 7);       /* (high byte) */
 102         if (value < 0) goto hw_err;
 103         value &= 0xff;
 104         value <<= 8;
 105
 106         low = spd_read_byte(device, 6); /* (low byte) */
 107         if (low < 0) goto hw_err;
 108         value = value | (low & 0xff);
 109         if ((value != 72) && (value != 64)) goto val_err;
 110         sz.side1 += log2(value);
 111
 112         /* side 2 */
 113         value = spd_read_byte(device, 5);       /* number of physical banks */
 114
 115         if (value < 0) goto hw_err;
 116         value &= 7;
 117         if(ddr2) value++;
 118         if (value == 1) goto out;
 119         if (value != 2) goto val_err;
 120
 121         /* Start with the symmetrical case */
 122         sz.side2 = sz.side1;
 123
 124         value = spd_read_byte(device, 3);       /* rows */
 125         if (value < 0) goto hw_err;
 126         if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
 127         sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
 128         sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
 129
 130         value = spd_read_byte(device, 4);       /* columns */
 131         if (value < 0) goto hw_err;
 132         if ((value & 0xff) == 0) goto val_err;
 133         sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
 134         sz.side2 += ((value >> 4) & 0x0f);      /* Add in columsn on side 2 */
 135         goto out;
 136
 137  val_err:
 138         die("Bad SPD value\r\n");
 139         /* If an hw_error occurs report that I have no memory */
 140 hw_err:
 141         sz.side1 = 0;
 142         sz.side2 = 0;
 143  out:
 144         return sz;
 145
 146 }
 147
 148 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 149 {
 150         int i;
 151         int cum;
 152
 153         for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 154                 struct dimm_size sz;
 155                 if (dimm_mask & (1 << i)) {
 156                         sz = spd_get_dimm_size(ctrl->channel0[i]);
 157                         if (sz.side1 < 29) {
 158                                 return -1; /* Report SPD error */
 159                         }
 160                         /* convert bits to multiples of 64MB */
 161                         sz.side1 -= 29;
 162                         cum += (1 << sz.side1);
 163                         /* DRB = 0x60 */
 164                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 165                         if( sz.side2 > 28) {
 166                                 sz.side2 -= 29;
 167                                 cum += (1 << sz.side2);
 168                         }
 169                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 170                 }
 171                 else {
 172                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 173                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 174                 }
 175         }
 176         /* set TOM top of memory 0xcc */
 177         pci_write_config16(ctrl->f0, TOM, cum);
 178         /* set TOLM top of low memory */
 179         if(cum > 0x18) {
 180                 cum = 0x18;
 181         }
 182         cum <<= 11;
 183         /* 0xc4 TOLM */
 184         pci_write_config16(ctrl->f0, TOLM, cum);
 185         return 0;
 186 }
 187
 188
 189 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 190 {
 191         unsigned dimm_mask;
 192         int i;
 193         dimm_mask = 0;
 194         for(i = 0; i < DIMM_SOCKETS; i++) {
 195                 int byte;
 196                 unsigned device;
 197                 device = ctrl->channel0[i];
 198                 if (device) {
 199                         byte = spd_read_byte(device, 2);  /* Type */
 200                         if ((byte == 7) || (byte == 8)) {
 201                                 dimm_mask |= (1 << i);
 202                         }
 203                 }
 204                 device = ctrl->channel1[i];
 205                 if (device) {
 206                         byte = spd_read_byte(device, 2);
 207                         if ((byte == 7) || (byte == 8)) {
 208                                 dimm_mask |= (1 << (i + DIMM_SOCKETS));
 209                         }
 210                 }
 211         }
 212         return dimm_mask;
 213 }
 214
 215
 216 static int spd_set_row_attributes(const struct mem_controller *ctrl,
 217                 long dimm_mask)
 218 {
 219
 220         int value;
 221         int reg;
 222         int dra;
 223         int cnt;
 224
 225         dra = 0;
 226         for(cnt=0; cnt < 4; cnt++) {
 227                 if (!(dimm_mask & (1 << cnt))) {
 228                         continue;
 229                 }
 230                 reg =0;
 231                 value = spd_read_byte(ctrl->channel0[cnt], 3);  /* rows */
 232                 if (value < 0) goto hw_err;
 233                 if ((value & 0xf) == 0) goto val_err;
 234                 reg += value & 0xf;
 235
 236                 value = spd_read_byte(ctrl->channel0[cnt], 4);  /* columns */
 237                 if (value < 0) goto hw_err;
 238                 if ((value & 0xf) == 0) goto val_err;
 239                 reg += value & 0xf;
 240
 241                 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
 242                 if (value < 0) goto hw_err;
 243                 if ((value & 0xff) == 0) goto val_err;
 244                 reg += log2(value & 0xff);
 245
 246                 /* Get the device width and convert it to a power of two */
 247                 value = spd_read_byte(ctrl->channel0[cnt], 13);
 248                 if (value < 0) goto hw_err;
 249                 value = log2(value & 0xff);
 250                 reg += value;
 251                 if(reg < 27) goto hw_err;
 252                 reg -= 27;
 253                 reg += (value << 2);
 254
 255                 dra += reg << (cnt*8);
 256                 value = spd_read_byte(ctrl->channel0[cnt], 5);
 257                 if (value & 2)
 258                         dra += reg << ((cnt*8)+4);
 259         }
 260
 261         /* 0x70 DRA */
 262         pci_write_config32(ctrl->f0, DRA, dra);
 263         goto out;
 264
 265  val_err:
 266         die("Bad SPD value\r\n");
 267         /* If an hw_error occurs report that I have no memory */
 268 hw_err:
 269         dra = 0;
 270  out:
 271         return dra;
 272
 273 }
 274
 275
 276 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 277                 long dimm_mask, uint32_t drc)
 278 {
 279         int value;
 280         int reg;
 281         uint32_t drt;
 282         int cnt;
 283         int first_dimm;
 284         int cas_latency=0;
 285         int latency;
 286         uint32_t index = 0;
 287         uint32_t index2 = 0;
 288         static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
 289         static const int latency_indicies[] = { 26, 23, 9 };
 290
 291         /* 0x78 DRT */
 292         drt = pci_read_config32(ctrl->f0, DRT);
 293         drt &= 3;  /* save bits 1:0 */
 294
 295         for(first_dimm = 0; first_dimm < 4; first_dimm++) {
 296                 if (dimm_mask & (1 << first_dimm))
 297                         break;
 298         }
 299
 300         /* get dimm type */
 301         value = spd_read_byte(ctrl->channel0[first_dimm], 2);
 302         if(value == 8) {
 303                 drt |= (3<<5); /* back to bark write turn around & cycle add */
 304         }
 305
 306         drt |= (3<<18);  /* Trasmax */
 307
 308         for(cnt=0; cnt < 4; cnt++) {
 309                 if (!(dimm_mask & (1 << cnt))) {
 310                         continue;
 311                 }
 312                 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 313                 /* Compute the lowest cas latency supported */
 314                 latency = log2(reg) -2;
 315
 316                 /* Loop through and find a fast clock with a low latency */
 317                 for(index = 0; index < 3; index++, latency++) {
 318                         if ((latency < 2) || (latency > 4) ||
 319                                 (!(reg & (1 << latency)))) {
 320                                 continue;
 321                         }
 322                         value = spd_read_byte(ctrl->channel0[cnt],
 323                                         latency_indicies[index]);
 324
 325                         if(value <= cycle_time[drc&3]) {
 326                                 if( latency > cas_latency) {
 327                                         cas_latency = latency;
 328                                 }
 329                                 break;
 330                         }
 331                 }
 332         }
 333         index = (cas_latency-2);
 334         if((index)==0) cas_latency = 20;
 335         else if((index)==1) cas_latency = 25;
 336         else cas_latency = 30;
 337
 338         for(cnt=0;cnt<4;cnt++) {
 339                 if (!(dimm_mask & (1 << cnt))) {
 340                         continue;
 341                 }
 342                 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
 343                 if(((index>>8)&0x0ff)<reg) {
 344                         index &= ~(0x0ff << 8);
 345                         index |= (reg << 8);
 346                 }
 347                 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
 348                 if(((index>>16)&0x0ff)<reg) {
 349                         index &= ~(0x0ff << 16);
 350                         index |= (reg<<16);
 351                 }
 352                 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
 353                 if(((index2>>0)&0x0ff)<reg) {
 354                         index2 &= ~(0x0ff << 0);
 355                         index2 |= (reg<<0);
 356                 }
 357                 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
 358                 if(((index2>>8)&0x0ff)<reg) {
 359                         index2 &= ~(0x0ff << 8);
 360                         index2 |= (reg<<8);
 361                 }
 362                 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
 363                 if(((index2>>16)&0x0ff)<reg) {
 364                         index2 &= ~(0x0ff << 16);
 365                         index2 |= (reg<<16);
 366                 }
 367         }
 368
 369         /* get dimm speed */
 370         value = cycle_time[drc&3];
 371         if(value <= 0x50) {  /* 200 MHz */
 372                 if((index&7) > 2) {
 373                         drt |= (2<<2);  /* CAS latency 4 */
 374                         cas_latency = 40;
 375                 } else {
 376                         drt |= (1<<2);  /* CAS latency 3 */
 377                         cas_latency = 30;
 378                 }
 379                 if((index&0x0ff00)<=0x03c00) {
 380                         drt |= (1<<8);  /* Trp RAS Precharg */
 381                 } else {
 382                         drt |= (2<<8);  /* Trp RAS Precharg */
 383                 }
 384
 385                 /* Trcd RAS to CAS delay */
 386                 if((index2&0x0ff)<=0x03c) {
 387                         drt |= (0<<10);
 388                 } else {
 389                         drt |= (1<<10);
 390                 }
 391
 392                 /* Tdal Write auto precharge recovery delay */
 393                 drt |= (1<<12);
 394
 395                 /* Trc TRS min */
 396                 if((index2&0x0ff00)<=0x03700)
 397                         drt |= (0<<14);
 398                 else if((index2&0xff00)<=0x03c00)
 399                         drt |= (1<<14);
 400                 else
 401                         drt |= (2<<14); /* spd 41 */
 402
 403                 drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 404
 405                 /* Trrd Row Delay */
 406                 if((index&0x0ff0000)<=0x0140000) {
 407                         drt |= (0<<20);
 408                 } else if((index&0x0ff0000)<=0x0280000) {
 409                         drt |= (1<<20);
 410                 } else if((index&0x0ff0000)<=0x03c0000) {
 411                         drt |= (2<<20);
 412                 } else {
 413                         drt |= (3<<20);
 414                 }
 415
 416                 /* Trfc Auto refresh cycle time */
 417                 if((index2&0x0ff0000)<=0x04b0000) {
 418                         drt |= (0<<22);
 419                 } else if((index2&0x0ff0000)<=0x0690000) {
 420                         drt |= (1<<22);
 421                 } else {
 422                         drt |= (2<<22);
 423                 }
 424                 /* Docs say use 55 for all 200Mhz */
 425                 drt |= (0x055<<24);
 426         }
 427         else if(value <= 0x60) { /* 167 Mhz */
 428                 /* according to new documentation CAS latency is 00
 429                  * for bits 3:2 for all 167 Mhz
 430                 drt |= ((index&3)<<2); */  /* set CAS latency */
 431                 if((index&0x0ff00)<=0x03000) {
 432                         drt |= (1<<8);  /* Trp RAS Precharg */
 433                 } else {
 434                         drt |= (2<<8);  /* Trp RAS Precharg */
 435                 }
 436
 437                 /* Trcd RAS to CAS delay */
 438                 if((index2&0x0ff)<=0x030) {
 439                         drt |= (0<<10);
 440                 } else {
 441                         drt |= (1<<10);
 442                 }
 443
 444                 /* Tdal Write auto precharge recovery delay */
 445                 drt |= (2<<12);
 446
 447                 /* Trc TRS min */
 448                 drt |= (2<<14); /* spd 41, but only one choice */
 449
 450                 drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 451
 452                 /* Trrd Row Delay */
 453                 if((index&0x0ff0000)<=0x0180000) {
 454                         drt |= (0<<20);
 455                 } else if((index&0x0ff0000)<=0x0300000) {
 456                         drt |= (1<<20);
 457                 } else {
 458                         drt |= (2<<20);
 459                 }
 460
 461                 /* Trfc Auto refresh cycle time */
 462                 if((index2&0x0ff0000)<=0x0480000) {
 463                         drt |= (0<<22);
 464                 } else if((index2&0x0ff0000)<=0x0780000) {
 465                         drt |= (2<<22);
 466                 } else {
 467                         drt |= (2<<22);
 468                 }
 469                 /* Docs state to use 99 for all 167 Mhz */
 470                 drt |= (0x099<<24);
 471         }
 472         else if(value <= 0x75) { /* 133 Mhz */
 473                 drt |= ((index&3)<<2);  /* set CAS latency */
 474                 if((index&0x0ff00)<=0x03c00) {
 475                         drt |= (1<<8);  /* Trp RAS Precharg */
 476                 } else {
 477                         drt |= (2<<8);  /* Trp RAS Precharg */
 478                 }
 479
 480                 /* Trcd RAS to CAS delay */
 481                 if((index2&0x0ff)<=0x03c) {
 482                         drt |= (0<<10);
 483                 } else {
 484                         drt |= (1<<10);
 485                 }
 486
 487                 /* Tdal Write auto precharge recovery delay */
 488                 drt |= (1<<12);
 489
 490                 /* Trc TRS min */
 491                 drt |= (2<<14); /* spd 41, but only one choice */
 492
 493                 drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 494
 495                 /* Trrd Row Delay */
 496                 if((index&0x0ff0000)<=0x01e0000) {
 497                         drt |= (0<<20);
 498                 } else if((index&0x0ff0000)<=0x03c0000) {
 499                         drt |= (1<<20);
 500                 } else {
 501                         drt |= (2<<20);
 502                 }
 503
 504                 /* Trfc Auto refresh cycle time */
 505                 if((index2&0x0ff0000)<=0x04b0000) {
 506                         drt |= (0<<22);
 507                 } else if((index2&0x0ff0000)<=0x0780000) {
 508                         drt |= (2<<22);
 509                 } else {
 510                         drt |= (2<<22);
 511                 }
 512
 513                 /* Based on CAS latency */
 514                 if(index&7)
 515                         drt |= (0x099<<24);
 516                 else
 517                         drt |= (0x055<<24);
 518
 519         }
 520         else {
 521                 die("Invalid SPD 9 bus speed.\r\n");
 522         }
 523
 524         /* 0x78 DRT */
 525         pci_write_config32(ctrl->f0, DRT, drt);
 526
 527         return(cas_latency);
 528 }
 529
 530 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 531                 long dimm_mask)
 532 {
 533         int value;
 534         int reg;
 535         int drc;
 536         int cnt;
 537         msr_t msr;
 538         unsigned char dram_type = 0xff;
 539         unsigned char ecc = 0xff;
 540         unsigned char rate = 62;
 541         static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
 542         static const unsigned char drc_rates[5] = {0,15,7,62,3};
 543         static const unsigned char fsb_conversion[4] = {3,1,3,2};
 544
 545         /* 0x7c DRC */
 546         drc = pci_read_config32(ctrl->f0, DRC);
 547         for(cnt=0; cnt < 4; cnt++) {
 548                 if (!(dimm_mask & (1 << cnt))) {
 549                         continue;
 550                 }
 551                 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
 552                 reg = spd_read_byte(ctrl->channel0[cnt], 2); /* Type */
 553                 if (value == 2) {    /* RAM is ECC capable */
 554                         if (reg == 8) {
 555                                 if ( ecc == 0xff ) {
 556                                         ecc = 2;
 557                                 }
 558                                 else if (ecc == 1) {
 559                                         die("ERROR - Mixed DDR & DDR2 RAM\r\n");
 560                                 }
 561                         }
 562                         else if ( reg == 7 ) {
 563                                 if ( ecc == 0xff) {
 564                                         ecc = 1;
 565                                 }
 566                                 else if ( ecc > 1 ) {
 567                                         die("ERROR - Mixed DDR & DDR2 RAM\r\n");
 568                                 }
 569                         }
 570                         else {
 571                                 die("ERROR - RAM not DDR\r\n");
 572                         }
 573                 }
 574                 else {
 575                         die("ERROR - Non ECC memory dimm\r\n");
 576                 }
 577
 578                 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
 579                 value &= 0x0f;    /* clip self refresh bit */
 580                 if (value > 5) goto hw_err;
 581                 if (rate > spd_rates[value])
 582                         rate = spd_rates[value];
 583
 584                 value = spd_read_byte(ctrl->channel0[cnt], 9);  /* cycle time */
 585                 if (value > 0x75) goto hw_err;
 586                 if (value <= 0x50) {
 587                         if (dram_type >= 2) {
 588                                 if (reg == 8) { /*speed is good, is this ddr2?*/
 589                                         dram_type = 2;
 590                                 } else { /* not ddr2 so use ddr333 */
 591                                         dram_type = 1;
 592                                 }
 593                         }
 594                 }
 595                 else if (value <= 0x60) {
 596                         if (dram_type >= 1)  dram_type = 1;
 597                 }
 598                 else dram_type = 0; /* ddr266 */
 599
 600         }
 601         ecc = 2;
 602         if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
 603                 ecc = 0;  /* ECC off in CMOS so disable it */
 604                 print_debug("ECC off\r\n");
 605         }
 606         else {
 607                 print_debug("ECC on\r\n");
 608         }
 609         drc &= ~(3 << 20); /* clear the ecc bits */
 610         drc |= (ecc << 20);  /* or in the calculated ecc bits */
 611         for ( cnt = 1; cnt < 5; cnt++)
 612                 if (drc_rates[cnt] == rate)
 613                         break;
 614         if (cnt < 5) {
 615                 drc &= ~(7 << 8);  /* clear the rate bits */
 616                 drc |= (cnt << 8);
 617         }
 618
 619         if (reg == 8) { /* independant clocks */
 620                 drc |= (1 << 4);
 621         }
 622
 623         drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
 624         drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
 625         /* front side bus */
 626         msr = rdmsr(0x2c);
 627         value = msr.lo >> 16;
 628         value &= 0x03;
 629         drc &= ~(3 << 2); /* set the front side bus */
 630         drc |= (fsb_conversion[value] << 2);
 631         drc &= ~(3 << 0); /* set the dram type */
 632         drc |= (dram_type << 0);
 633
 634         goto out;
 635
 636  val_err:
 637         die("Bad SPD value\r\n");
 638         /* If an hw_error occurs report that I have no memory */
 639 hw_err:
 640         drc = 0;
 641  out:
 642         return drc;
 643 }
 644
 645 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 646 {
 647         long dimm_mask;
 648
 649         /* Test if we can read the spd and if ram is ddr or ddr2 */
 650         dimm_mask = spd_detect_dimms(ctrl);
 651         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 652                 print_err("No memory for this cpu\r\n");
 653                 return;
 654         }
 655         return;
 656 }
 657
 658 static void do_delay(void)
 659 {
 660         int i;
 661         unsigned char b;
 662         for(i=0;i<16;i++)
 663                 b=inb(0x80);
 664 }
 665
 666 #define TIMEOUT_LOOPS 300000
 667
 668 #define DCALCSR  0x100
 669 #define DCALADDR 0x104
 670 #define DCALDATA 0x108
 671
 672 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 673 {
 674         unsigned char c1,c2;
 675         unsigned int dimm,i;
 676         unsigned int data32;
 677         unsigned int t4;
 678
 679         /* Set up northbridge values */
 680         /* ODT enable */
 681         pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
 682         /* Figure out which slots are Empty, Single, or Double sided */
 683         for(i=0,t4=0,c2=0;i<8;i+=2) {
 684                 c1 = pci_read_config8(ctrl->f0, DRB+i);
 685                 if(c1 == c2) continue;
 686                 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
 687                 if(c1 == c2)
 688                         t4 |= (1 << (i*4));
 689                 else
 690                         t4 |= (2 << (i*4));
 691         }
 692         for(i=0;i<1;i++) {
 693             if((t4&0x0f) == 1) {
 694                 if( ((t4>>8)&0x0f) == 0 ) {
 695                         data32 = 0x00000010; /* EEES */
 696                         break;
 697                 }
 698                 if ( ((t4>>16)&0x0f) == 0 ) {
 699                         data32 = 0x00003132; /* EESS */
 700                         break;
 701                 }
 702                 if ( ((t4>>24)&0x0f)  == 0 ) {
 703                         data32 = 0x00335566; /* ESSS */
 704                         break;
 705                 }
 706                 data32 = 0x77bbddee; /* SSSS */
 707                 break;
 708             }
 709             if((t4&0x0f) == 2) {
 710                 if( ((t4>>8)&0x0f) == 0 ) {
 711                         data32 = 0x00003132; /* EEED */
 712                         break;
 713                 }
 714                 if ( ((t4>>8)&0x0f) == 2 ) {
 715                         data32 = 0xb373ecdc; /* EEDD */
 716                         break;
 717                 }
 718                 if ( ((t4>>16)&0x0f) == 0 ) {
 719                         data32 = 0x00b3a898; /* EESD */
 720                         break;
 721                 }
 722                 data32 = 0x777becdc; /* ESSD */
 723                 break;
 724             }
 725             die("Error - First dimm slot empty\r\n");
 726         }
 727
 728         print_debug("ODT Value = ");
 729         print_debug_hex32(data32);
 730         print_debug("\r\n");
 731
 732         pci_write_config32(ctrl->f0, 0xb0, data32);
 733
 734         for(dimm=0;dimm<8;dimm+=1) {
 735
 736                 write32(BAR+DCALADDR, 0x0b840001);
 737                 write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
 738
 739                 for(i=0;i<1001;i++) {
 740                         data32 = read32(BAR+DCALCSR);
 741                         if(!(data32 & (1<<31)))
 742                                 break;
 743                 }
 744         }
 745 }
 746 static void set_receive_enable(const struct mem_controller *ctrl)
 747 {
 748         unsigned int i;
 749         unsigned int cnt,bit;
 750         uint32_t recena=0;
 751         uint32_t recenb=0;
 752
 753         {
 754         unsigned int dimm;
 755         unsigned int edge;
 756         int32_t data32;
 757         uint32_t data32_dram;
 758         uint32_t dcal_data32_0;
 759         uint32_t dcal_data32_1;
 760         uint32_t dcal_data32_2;
 761         uint32_t dcal_data32_3;
 762         uint32_t work32l;
 763         uint32_t work32h;
 764         uint32_t data32r;
 765         int32_t recen;
 766         for(dimm=0;dimm<8;dimm+=1) {
 767
 768                 if(!(dimm&1)) {
 769                         write32(BAR+DCALDATA+(17*4), 0x04020000);
 770                         write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
 771
 772                         for(i=0;i<1001;i++) {
 773                                 data32 = read32(BAR+DCALCSR);
 774                                 if(!(data32 & (1<<31)))
 775                                         break;
 776                         }
 777                         if(i>=1000)
 778                                 continue;
 779
 780                         dcal_data32_0 = read32(BAR+DCALDATA + 0);
 781                         dcal_data32_1 = read32(BAR+DCALDATA + 4);
 782                         dcal_data32_2 = read32(BAR+DCALDATA + 8);
 783                         dcal_data32_3 = read32(BAR+DCALDATA + 12);
 784                 }
 785                 else {
 786                         dcal_data32_0 = read32(BAR+DCALDATA + 16);
 787                         dcal_data32_1 = read32(BAR+DCALDATA + 20);
 788                         dcal_data32_2 = read32(BAR+DCALDATA + 24);
 789                         dcal_data32_3 = read32(BAR+DCALDATA + 28);
 790                 }
 791
 792                 /* check if bank is installed */
 793                 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 794                         continue;
 795                 /* Calculate the timing value */
 796                 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
 797                         work32l=dcal_data32_1,work32h=dcal_data32_3;
 798                                 (i<4) && bit; i++) {
 799                         for(;;bit--,cnt--) {
 800                                 if(work32l & (1<<cnt))
 801                                         break;
 802                                 if(!cnt) {
 803                                         work32l = dcal_data32_0;
 804                                         work32h = dcal_data32_2;
 805                                         cnt = 32;
 806                                 }
 807                                 if(!bit) break;
 808                         }
 809                         for(;;bit--,cnt--) {
 810                                 if(!(work32l & (1<<cnt)))
 811                                         break;
 812                                 if(!cnt) {
 813                                         work32l = dcal_data32_0;
 814                                         work32h = dcal_data32_2;
 815                                         cnt = 32;
 816                                 }
 817                                 if(!bit) break;
 818                         }
 819                         if(!bit) {
 820                                 break;
 821                         }
 822                         data32 = ((bit%8) << 1);
 823                         if(work32h & (1<<cnt))
 824                                 data32 += 1;
 825                         if(data32 < 4) {
 826                                 if(!edge) {
 827                                         edge = 1;
 828                                 }
 829                                 else {
 830                                         if(edge != 1) {
 831                                                 data32 = 0x0f;
 832                                         }
 833                                 }
 834                         }
 835                         if(data32 > 12) {
 836                                 if(!edge) {
 837                                         edge = 2;
 838                                 }
 839                                 else {
 840                                         if(edge != 2) {
 841                                                 data32 = 0x00;
 842                                         }
 843                                 }
 844                         }
 845                         data32r += data32;
 846                 }
 847
 848                 work32l = dcal_data32_0;
 849                 work32h = dcal_data32_2;
 850                 recen = data32r;
 851                 recen += 3;
 852                 recen = recen>>2;
 853                 for(cnt=5;cnt<24;) {
 854                         for(;;cnt++)
 855                                 if(!(work32l & (1<<cnt)))
 856                                         break;
 857                         for(;;cnt++) {
 858                                 if(work32l & (1<<cnt))
 859                                         break;
 860                         }
 861                         data32 = (((cnt-1)%8)<<1);
 862                         if(work32h & (1<<(cnt-1))) {
 863                                 data32++;
 864                         }
 865                         /* test for frame edge cross overs */
 866                         if((edge == 1) && (data32 > 12) &&
 867                             (((recen+16)-data32) < 3)) {
 868                                 data32 = 0;
 869                                 cnt += 2;
 870                         }
 871                         if((edge == 2) && (data32 < 4) &&
 872                             ((recen - data32) > 12))  {
 873                                 data32 = 0x0f;
 874                                 cnt -= 2;
 875                         }
 876                         if(((recen+3) >= data32) && ((recen-3) <= data32))
 877                                 break;
 878                 }
 879                 cnt--;
 880                 cnt /= 8;
 881                 cnt--;
 882                 if(recen&1)
 883                         recen+=2;
 884                 recen >>= 1;
 885                 recen += (cnt*8);
 886         recen+=2;
 887                 recen <<= (dimm/2) * 8;
 888                 if(!(dimm&1)) {
 889                         recena |= recen;
 890                 }
 891                 else {
 892                         recenb |= recen;
 893                 }
 894         }
 895         }
 896         /* Check for Eratta problem */
 897         for(i=cnt=bit=0;i<4;i++) {
 898                 if (((recena>>(i*8))&0x0f)>7) {
 899                         cnt++; bit++;
 900                 }
 901                 else {
 902                         if((recena>>(i*8))&0x0f) {
 903                                 cnt++;
 904                         }
 905                 }
 906         }
 907         if(bit) {
 908                 cnt-=bit;
 909                 if(cnt>1) {
 910                         for(i=0;i<4;i++) {
 911                                 if(((recena>>(i*8))&0x0f)>7) {
 912                                         recena &= ~(0x0f<<(i*8));
 913                                         recena |= (7<<(i*8));
 914                                 }
 915                         }
 916                 }
 917                 else {
 918                         for(i=0;i<4;i++) {
 919                                 if(((recena>>(i*8))&0x0f)<8) {
 920                                         recena &= ~(0x0f<<(i*8));
 921                                         recena |= (8<<(i*8));
 922                                 }
 923                         }
 924                 }
 925         }
 926         for(i=cnt=bit=0;i<4;i++) {
 927                 if (((recenb>>(i*8))&0x0f)>7) {
 928                         cnt++; bit++;
 929                 }
 930                 else {
 931                         if((recenb>>(i*8))&0x0f) {
 932                                 cnt++;
 933                         }
 934                 }
 935         }
 936         if(bit) {
 937                 cnt-=bit;
 938                 if(cnt>1) {
 939                         for(i=0;i<4;i++) {
 940                                 if(((recenb>>(i*8))&0x0f)>7) {
 941                                         recenb &= ~(0x0f<<(i*8));
 942                                         recenb |= (7<<(i*8));
 943                                 }
 944                         }
 945                 }
 946                 else {
 947                         for(i=0;i<4;i++) {
 948                                 if(((recenb>>(i*8))&0x0f)<8) {
 949                                         recenb &= ~(0x0f<<(i*8));
 950                                         recenb |= (8<<(i*8));
 951                                 }
 952                         }
 953                 }
 954         }
 955
 956 //  recena = 0x0000090a;
 957 //  recenb = 0x0000090a;
 958
 959         print_debug("Receive enable A = ");
 960         print_debug_hex32(recena);
 961         print_debug(",  Receive enable B = ");
 962         print_debug_hex32(recenb);
 963         print_debug("\r\n");
 964
 965         /* clear out the calibration area */
 966         write32(BAR+DCALDATA+(16*4), 0x00000000);
 967         write32(BAR+DCALDATA+(17*4), 0x00000000);
 968         write32(BAR+DCALDATA+(18*4), 0x00000000);
 969         write32(BAR+DCALDATA+(19*4), 0x00000000);
 970
 971         /* No command */
 972         write32(BAR+DCALCSR, 0x0000000f);
 973
 974         write32(BAR+0x150, recena);
 975         write32(BAR+0x154, recenb);
 976 }
 977
 978
 979 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 980 {
 981         int i;
 982         int cs;
 983         int cnt;
 984         int cas_latency;
 985         long mask;
 986         uint32_t drc;
 987         uint32_t data32;
 988         uint32_t mode_reg;
 989         uint32_t *iptr;
 990         volatile unsigned long *iptrv;
 991         msr_t msr;
 992         uint32_t scratch;
 993         uint8_t byte;
 994         uint16_t data16;
 995         static const struct {
 996                 uint32_t clkgr[4];
 997         } gearing [] = {
 998                 /* FSB 133 DIMM 266 */
 999         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1000                 /* FSB 133 DIMM 333 */
1001         {{ 0x00000000, 0x00000000, 0x00000000, 0x00000000}},
1002                 /* FSB 133 DIMM 400 */
1003         {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
1004                 /* FSB 167 DIMM 266 */
1005         {{ 0x00005432, 0x00001000, 0x00004325, 0x00000000}},
1006                 /* FSB 167 DIMM 333 */
1007         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1008                 /* FSB 167 DIMM 400 */
1009         {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
1010                 /* FSB 200 DIMM 266 */
1011         {{ 0x00000032, 0x00000010, 0x00000120, 0x00000000}},
1012                 /* FSB 200 DIMM 333 */
1013         {{ 0x00065432, 0x00010000, 0x00054326, 0x00000000}},
1014                 /* FSB 200 DIMM 400 */
1015         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1016         };
1017
1018         static const uint32_t dqs_data[] = {
1019                 0xffffffff, 0xffffffff, 0x000000ff,
1020                 0xffffffff, 0xffffffff, 0x000000ff,
1021                 0xffffffff, 0xffffffff, 0x000000ff,
1022                 0xffffffff, 0xffffffff, 0x000000ff,
1023                 0xffffffff, 0xffffffff, 0x000000ff,
1024                 0xffffffff, 0xffffffff, 0x000000ff,
1025                 0xffffffff, 0xffffffff, 0x000000ff,
1026                 0xffffffff, 0xffffffff, 0x000000ff};
1027
1028         mask = spd_detect_dimms(ctrl);
1029         print_debug("Starting SDRAM Enable\r\n");
1030
1031         /* 0x80 */
1032 #ifdef DIMM_MAP_LOGICAL
1033         pci_write_config32(ctrl->f0, DRM,
1034                 0x00210000 | DIMM_MAP_LOGICAL);
1035 #else
1036         pci_write_config32(ctrl->f0, DRM, 0x00211248);
1037 #endif
1038         /* set dram type and Front Side Bus freq. */
1039         drc = spd_set_dram_controller_mode(ctrl, mask);
1040         if( drc == 0) {
1041                 die("Error calculating DRC\r\n");
1042         }
1043         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1044         data32 = data32 & ~(7 << 8);  /* clear refresh rates */
1045         data32 = data32 | (1 << 5);  /* temp turn off of ODT */
1046         /* Set gearing, then dram controller mode */
1047         /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
1048         for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
1049                         cnt<4;cnt++) {
1050                 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1051         }
1052         /* 0x7c DRC */
1053         pci_write_config32(ctrl->f0, DRC, data32);
1054
1055                 /* turn the clocks on */
1056         /* 0x8c CKDIS */
1057         pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1058
1059                 /* 0x9a DDRCSR Take subsystem out of idle */
1060         data16 = pci_read_config16(ctrl->f0, DDRCSR);
1061         data16 &= ~(7 << 12);
1062         data16 |= (3 << 12);   /* use dual channel lock step */
1063         pci_write_config16(ctrl->f0, DDRCSR, data16);
1064
1065                 /* program row size DRB */
1066         spd_set_ram_size(ctrl, mask);
1067
1068                 /* program page size DRA */
1069         spd_set_row_attributes(ctrl, mask);
1070
1071                 /* program DRT timing values */
1072         cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1073
1074         for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
1075                 print_debug("DIMM ");
1076                 print_debug_hex8(i);
1077                 print_debug("\r\n");
1078                 /* Apply NOP */
1079                 do_delay();
1080
1081                 write32(BAR + 0x100, (0x03000000 | (i<<20)));
1082
1083                 write32(BAR+0x100, (0x83000000 | (i<<20)));
1084
1085                 data32 = read32(BAR+DCALCSR);
1086                 while(data32 & 0x80000000)
1087                         data32 = read32(BAR+DCALCSR);
1088
1089         }
1090
1091         /* Apply NOP */
1092         do_delay();
1093
1094         for(cs=0;cs<8;cs++) {
1095                 write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
1096                 data32 = read32(BAR+DCALCSR);
1097                 while(data32 & 0x80000000)
1098                         data32 = read32(BAR+DCALCSR);
1099         }
1100
1101         /* Precharg all banks */
1102         do_delay();
1103         for(cs=0;cs<8;cs++) {
1104                 if ((drc & 3) == 2) /* DDR2  */
1105                         write32(BAR+DCALADDR, 0x04000000);
1106                 else   /* DDR1  */
1107                         write32(BAR+DCALADDR, 0x00000000);
1108                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1109                 data32 = read32(BAR+DCALCSR);
1110                 while(data32 & 0x80000000)
1111                         data32 = read32(BAR+DCALCSR);
1112         }
1113
1114         /* EMRS dll's enabled */
1115         do_delay();
1116         for(cs=0;cs<8;cs++) {
1117                 if ((drc & 3) == 2) /* DDR2  */
1118                         /* fixme hard code AL additive latency */
1119                         write32(BAR+DCALADDR, 0x0b940001);
1120                 else   /* DDR1  */
1121                         write32(BAR+DCALADDR, 0x00000001);
1122                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1123                 data32 = read32(BAR+DCALCSR);
1124                 while(data32 & 0x80000000)
1125                         data32 = read32(BAR+DCALCSR);
1126         }
1127         /* MRS reset dll's */
1128         do_delay();
1129         if ((drc & 3) == 2) {  /* DDR2  */
1130                 if(cas_latency == 30)
1131                         mode_reg = 0x053a0000;
1132                 else
1133                         mode_reg = 0x054a0000;
1134         }
1135         else {  /* DDR1  */
1136                 if(cas_latency == 20)
1137                         mode_reg = 0x012a0000;
1138                 else  /*  CAS Latency 2.5 */
1139                         mode_reg = 0x016a0000;
1140         }
1141         for(cs=0;cs<8;cs++) {
1142                 write32(BAR+DCALADDR, mode_reg);
1143                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1144                 data32 = read32(BAR+DCALCSR);
1145                 while(data32 & 0x80000000)
1146                         data32 = read32(BAR+DCALCSR);
1147         }
1148
1149         /* Precharg all banks */
1150         do_delay();
1151         do_delay();
1152         do_delay();
1153         for(cs=0;cs<8;cs++) {
1154                 if ((drc & 3) == 2) /* DDR2  */
1155                         write32(BAR+DCALADDR, 0x04000000);
1156                 else   /* DDR1  */
1157                         write32(BAR+DCALADDR, 0x00000000);
1158                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1159                 data32 = read32(BAR+DCALCSR);
1160                 while(data32 & 0x80000000)
1161                         data32 = read32(BAR+DCALCSR);
1162         }
1163
1164         /* Do 2 refreshes */
1165         do_delay();
1166         for(cs=0;cs<8;cs++) {
1167                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1168                 data32 = read32(BAR+DCALCSR);
1169                 while(data32 & 0x80000000)
1170                         data32 = read32(BAR+DCALCSR);
1171         }
1172         do_delay();
1173         for(cs=0;cs<8;cs++) {
1174                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1175                 data32 = read32(BAR+DCALCSR);
1176                 while(data32 & 0x80000000)
1177                         data32 = read32(BAR+DCALCSR);
1178         }
1179         do_delay();
1180         /* for good luck do 6 more */
1181         for(cs=0;cs<8;cs++) {
1182                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1183         }
1184         do_delay();
1185         for(cs=0;cs<8;cs++) {
1186                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1187         }
1188         do_delay();
1189         for(cs=0;cs<8;cs++) {
1190                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1191         }
1192         do_delay();
1193         for(cs=0;cs<8;cs++) {
1194                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1195         }
1196         do_delay();
1197         for(cs=0;cs<8;cs++) {
1198                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1199         }
1200         do_delay();
1201         for(cs=0;cs<8;cs++) {
1202                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1203         }
1204         do_delay();
1205         /* MRS reset dll's normal */
1206         do_delay();
1207         for(cs=0;cs<8;cs++) {
1208                 write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
1209                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1210                 data32 = read32(BAR+DCALCSR);
1211                 while(data32 & 0x80000000)
1212                         data32 = read32(BAR+DCALCSR);
1213         }
1214
1215         /* Do only if DDR2  EMRS dll's enabled */
1216         if ((drc & 3) == 2) { /* DDR2  */
1217                 do_delay();
1218                 for(cs=0;cs<8;cs++) {
1219                         write32(BAR+DCALADDR, (0x0b940001));
1220                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1221                         data32 = read32(BAR+DCALCSR);
1222                         while(data32 & 0x80000000)
1223                                 data32 = read32(BAR+DCALCSR);
1224                 }
1225         }
1226
1227         do_delay();
1228         /* No command */
1229         write32(BAR+DCALCSR, 0x0000000f);
1230
1231         /* DDR1 This is test code to copy some codes in the factory setup */
1232
1233         write32(BAR, 0x00100000);
1234
1235         if ((drc & 3) == 2) { /* DDR2  */
1236         /* enable on dimm termination */
1237                 set_on_dimm_termination_enable(ctrl);
1238         }
1239
1240         /* receive enable calibration */
1241         set_receive_enable(ctrl);
1242
1243         /* DQS */
1244         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1245         for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
1246                 write32(cnt, dqs_data[i]);
1247         }
1248         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1249
1250         /* Enable refresh */
1251         /* 0x7c DRC */
1252         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1253         pci_write_config32(ctrl->f0, DRC, data32);
1254         write32(BAR+DCALCSR, 0x0008000f);
1255
1256         /* clear memory and init ECC */
1257         print_debug("Clearing memory\r\n");
1258         for(i=0;i<64;i+=4) {
1259                 write32(BAR+DCALDATA+i, 0x00000000);
1260         }
1261
1262         for(cs=0;cs<8;cs++) {
1263                 write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
1264                 data32 = read32(BAR+DCALCSR);
1265                 while(data32 & 0x80000000)
1266                         data32 = read32(BAR+DCALCSR);
1267         }
1268
1269         /* Bring memory subsystem on line */
1270         data32 = pci_read_config32(ctrl->f0, 0x98);
1271         data32 |= (1 << 31);
1272         pci_write_config32(ctrl->f0, 0x98, data32);
1273         /* wait for completion */
1274         print_debug("Waiting for mem complete\r\n");
1275         while(1) {
1276                 data32 = pci_read_config32(ctrl->f0, 0x98);
1277                 if( (data32 & (1<<31)) == 0)
1278                         break;
1279         }
1280         print_debug("Done\r\n");
1281
1282         /* Set initialization complete */
1283         /* 0x7c DRC */
1284         drc |= (1 << 29);
1285         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1286         pci_write_config32(ctrl->f0, DRC, data32);
1287
1288         /* Set the ecc mode */
1289         pci_write_config32(ctrl->f0, DRC, drc);
1290
1291         /* Enable memory scrubbing */
1292         /* 0x52 MCHSCRB */
1293         data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1294         data16 &= ~0x0f;
1295         data16 |= ((2 << 2) | (2 << 0));
1296         pci_write_config16(ctrl->f0, MCHSCRB, data16);
1297
1298         /* The memory is now setup, use it */
1299         cache_lbmem(MTRR_TYPE_WRBACK);
1300 }