2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/mtrr.h>
22 #include <cpu/x86/cache.h>
26 #include <pc80/mc146818rtc.h>
27 #if CONFIG_HAVE_OPTION_TABLE
28 #include "option_table.h"
31 #define BAR 0x40000000
33 static void sdram_set_registers(const struct mem_controller *ctrl)
35 static const unsigned int register_values[] = {
37 /* CKDIS 0x8c disable clocks */
38 PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
40 /* 0x9c Device present and extended RAM control
41 * DEVPRES is very touchy, hard code the initialization
42 * of PCI-E ports here.
44 PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
46 /* 0xc8 Remap RAM base and limit off */
47 PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
50 PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
51 PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
54 PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
57 PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
58 PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
61 PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
64 PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
69 max = ARRAY_SIZE(register_values);
70 for(i = 0; i < max; i += 3) {
74 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
75 where = register_values[i] & 0xff;
76 reg = pci_read_config32(dev, where);
77 reg &= register_values[i+1];
78 reg |= register_values[i+2];
79 pci_write_config32(dev, where, reg);
81 print_spew("done.\n");
91 static struct dimm_size spd_get_dimm_size(unsigned device)
93 /* Calculate the log base 2 size of a DIMM in bits */
101 value = spd_read_byte(device, 2); /* type */
102 if (value < 0) goto hw_err;
103 if (value == 8) ddr2 = 1;
105 /* Note it might be easier to use byte 31 here, it has the DIMM size as
106 * a multiple of 4MB. The way we do it now we can size both
107 * sides of an assymetric dimm.
109 value = spd_read_byte(device, 3); /* rows */
110 if (value < 0) goto hw_err;
111 if ((value & 0xf) == 0) goto val_err;
112 sz.side1 += value & 0xf;
114 value = spd_read_byte(device, 4); /* columns */
115 if (value < 0) goto hw_err;
116 if ((value & 0xf) == 0) goto val_err;
117 sz.side1 += value & 0xf;
119 value = spd_read_byte(device, 17); /* banks */
120 if (value < 0) goto hw_err;
121 if ((value & 0xff) == 0) goto val_err;
122 sz.side1 += log2(value & 0xff);
124 /* Get the module data width and convert it to a power of two */
125 value = spd_read_byte(device, 7); /* (high byte) */
126 if (value < 0) goto hw_err;
130 low = spd_read_byte(device, 6); /* (low byte) */
131 if (low < 0) goto hw_err;
132 value = value | (low & 0xff);
133 if ((value != 72) && (value != 64)) goto val_err;
134 sz.side1 += log2(value);
137 value = spd_read_byte(device, 5); /* number of physical banks */
139 if (value < 0) goto hw_err;
142 if (value == 1) goto out;
143 if (value != 2) goto val_err;
145 /* Start with the symmetrical case */
148 value = spd_read_byte(device, 3); /* rows */
149 if (value < 0) goto hw_err;
150 if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
151 sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
152 sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
154 value = spd_read_byte(device, 4); /* columns */
155 if (value < 0) goto hw_err;
156 if ((value & 0xff) == 0) goto val_err;
157 sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
158 sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
162 die("Bad SPD value\n");
163 /* If an hw_error occurs report that I have no memory */
172 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
177 for(i = cum = 0; i < DIMM_SOCKETS; i++) {
179 if (dimm_mask & (1 << i)) {
180 sz = spd_get_dimm_size(ctrl->channel0[i]);
182 return -1; /* Report SPD error */
184 /* convert bits to multiples of 64MB */
186 cum += (1 << sz.side1);
188 pci_write_config8(ctrl->f0, DRB + (i*2), cum);
191 cum += (1 << sz.side2);
193 pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
196 pci_write_config8(ctrl->f0, DRB + (i*2), cum);
197 pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
200 /* set TOM top of memory 0xcc */
201 pci_write_config16(ctrl->f0, TOM, cum);
202 /* set TOLM top of low memory */
208 pci_write_config16(ctrl->f0, TOLM, cum);
213 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
218 for(i = 0; i < DIMM_SOCKETS; i++) {
221 device = ctrl->channel0[i];
223 byte = spd_read_byte(device, 2); /* Type */
224 if ((byte == 7) || (byte == 8)) {
225 dimm_mask |= (1 << i);
228 device = ctrl->channel1[i];
230 byte = spd_read_byte(device, 2);
231 if ((byte == 7) || (byte == 8)) {
232 dimm_mask |= (1 << (i + DIMM_SOCKETS));
240 static int spd_set_row_attributes(const struct mem_controller *ctrl,
250 for(cnt=0; cnt < 4; cnt++) {
251 if (!(dimm_mask & (1 << cnt))) {
255 value = spd_read_byte(ctrl->channel0[cnt], 3); /* rows */
256 if (value < 0) goto hw_err;
257 if ((value & 0xf) == 0) goto val_err;
260 value = spd_read_byte(ctrl->channel0[cnt], 4); /* columns */
261 if (value < 0) goto hw_err;
262 if ((value & 0xf) == 0) goto val_err;
265 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
266 if (value < 0) goto hw_err;
267 if ((value & 0xff) == 0) goto val_err;
268 reg += log2(value & 0xff);
270 /* Get the device width and convert it to a power of two */
271 value = spd_read_byte(ctrl->channel0[cnt], 13);
272 if (value < 0) goto hw_err;
273 value = log2(value & 0xff);
275 if(reg < 27) goto hw_err;
279 dra += reg << (cnt*8);
280 value = spd_read_byte(ctrl->channel0[cnt], 5);
282 dra += reg << ((cnt*8)+4);
286 pci_write_config32(ctrl->f0, DRA, dra);
290 die("Bad SPD value\n");
291 /* If an hw_error occurs report that I have no memory */
300 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
301 long dimm_mask, uint32_t drc)
312 static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
313 static const int latency_indicies[] = { 26, 23, 9 };
316 drt = pci_read_config32(ctrl->f0, DRT);
317 drt &= 3; /* save bits 1:0 */
319 for(first_dimm = 0; first_dimm < 4; first_dimm++) {
320 if (dimm_mask & (1 << first_dimm))
325 value = spd_read_byte(ctrl->channel0[first_dimm], 2);
327 drt |= (3<<5); /* back to bark write turn around & cycle add */
330 drt |= (3<<18); /* Trasmax */
332 for(cnt=0; cnt < 4; cnt++) {
333 if (!(dimm_mask & (1 << cnt))) {
336 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
337 /* Compute the lowest cas latency supported */
338 latency = log2(reg) -2;
340 /* Loop through and find a fast clock with a low latency */
341 for(index = 0; index < 3; index++, latency++) {
342 if ((latency < 2) || (latency > 4) ||
343 (!(reg & (1 << latency)))) {
346 value = spd_read_byte(ctrl->channel0[cnt],
347 latency_indicies[index]);
349 if(value <= cycle_time[drc&3]) {
350 if( latency > cas_latency) {
351 cas_latency = latency;
357 index = (cas_latency-2);
358 if((index)==0) cas_latency = 20;
359 else if((index)==1) cas_latency = 25;
360 else cas_latency = 30;
362 for(cnt=0;cnt<4;cnt++) {
363 if (!(dimm_mask & (1 << cnt))) {
366 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
367 if(((index>>8)&0x0ff)<reg) {
368 index &= ~(0x0ff << 8);
371 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
372 if(((index>>16)&0x0ff)<reg) {
373 index &= ~(0x0ff << 16);
376 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
377 if(((index2>>0)&0x0ff)<reg) {
378 index2 &= ~(0x0ff << 0);
381 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
382 if(((index2>>8)&0x0ff)<reg) {
383 index2 &= ~(0x0ff << 8);
386 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
387 if(((index2>>16)&0x0ff)<reg) {
388 index2 &= ~(0x0ff << 16);
394 value = cycle_time[drc&3];
395 if(value <= 0x50) { /* 200 MHz */
397 drt |= (2<<2); /* CAS latency 4 */
400 drt |= (1<<2); /* CAS latency 3 */
403 if((index&0x0ff00)<=0x03c00) {
404 drt |= (1<<8); /* Trp RAS Precharg */
406 drt |= (2<<8); /* Trp RAS Precharg */
409 /* Trcd RAS to CAS delay */
410 if((index2&0x0ff)<=0x03c) {
416 /* Tdal Write auto precharge recovery delay */
420 if((index2&0x0ff00)<=0x03700)
422 else if((index2&0xff00)<=0x03c00)
425 drt |= (2<<14); /* spd 41 */
427 drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */
430 if((index&0x0ff0000)<=0x0140000) {
432 } else if((index&0x0ff0000)<=0x0280000) {
434 } else if((index&0x0ff0000)<=0x03c0000) {
440 /* Trfc Auto refresh cycle time */
441 if((index2&0x0ff0000)<=0x04b0000) {
443 } else if((index2&0x0ff0000)<=0x0690000) {
448 /* Docs say use 55 for all 200Mhz */
451 else if(value <= 0x60) { /* 167 Mhz */
452 /* according to new documentation CAS latency is 00
453 * for bits 3:2 for all 167 Mhz
454 drt |= ((index&3)<<2); */ /* set CAS latency */
455 if((index&0x0ff00)<=0x03000) {
456 drt |= (1<<8); /* Trp RAS Precharg */
458 drt |= (2<<8); /* Trp RAS Precharg */
461 /* Trcd RAS to CAS delay */
462 if((index2&0x0ff)<=0x030) {
468 /* Tdal Write auto precharge recovery delay */
472 drt |= (2<<14); /* spd 41, but only one choice */
474 drt |= (2<<16); /* Twr not defined for DDR docs say 2 */
477 if((index&0x0ff0000)<=0x0180000) {
479 } else if((index&0x0ff0000)<=0x0300000) {
485 /* Trfc Auto refresh cycle time */
486 if((index2&0x0ff0000)<=0x0480000) {
488 } else if((index2&0x0ff0000)<=0x0780000) {
493 /* Docs state to use 99 for all 167 Mhz */
496 else if(value <= 0x75) { /* 133 Mhz */
497 drt |= ((index&3)<<2); /* set CAS latency */
498 if((index&0x0ff00)<=0x03c00) {
499 drt |= (1<<8); /* Trp RAS Precharg */
501 drt |= (2<<8); /* Trp RAS Precharg */
504 /* Trcd RAS to CAS delay */
505 if((index2&0x0ff)<=0x03c) {
511 /* Tdal Write auto precharge recovery delay */
515 drt |= (2<<14); /* spd 41, but only one choice */
517 drt |= (1<<16); /* Twr not defined for DDR docs say 1 */
520 if((index&0x0ff0000)<=0x01e0000) {
522 } else if((index&0x0ff0000)<=0x03c0000) {
528 /* Trfc Auto refresh cycle time */
529 if((index2&0x0ff0000)<=0x04b0000) {
531 } else if((index2&0x0ff0000)<=0x0780000) {
537 /* Based on CAS latency */
545 die("Invalid SPD 9 bus speed.\n");
549 pci_write_config32(ctrl->f0, DRT, drt);
554 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
562 unsigned char dram_type = 0xff;
563 unsigned char ecc = 0xff;
564 unsigned char rate = 62;
565 static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
566 static const unsigned char drc_rates[5] = {0,15,7,62,3};
567 static const unsigned char fsb_conversion[4] = {3,1,3,2};
570 drc = pci_read_config32(ctrl->f0, DRC);
571 for(cnt=0; cnt < 4; cnt++) {
572 if (!(dimm_mask & (1 << cnt))) {
575 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
576 reg = spd_read_byte(ctrl->channel0[cnt], 2); /* Type */
577 if (value == 2) { /* RAM is ECC capable */
583 die("ERROR - Mixed DDR & DDR2 RAM\n");
586 else if ( reg == 7 ) {
590 else if ( ecc > 1 ) {
591 die("ERROR - Mixed DDR & DDR2 RAM\n");
595 die("ERROR - RAM not DDR\n");
599 die("ERROR - Non ECC memory dimm\n");
602 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
603 value &= 0x0f; /* clip self refresh bit */
604 if (value > 5) goto hw_err;
605 if (rate > spd_rates[value])
606 rate = spd_rates[value];
608 value = spd_read_byte(ctrl->channel0[cnt], 9); /* cycle time */
609 if (value > 0x75) goto hw_err;
611 if (dram_type >= 2) {
612 if (reg == 8) { /*speed is good, is this ddr2?*/
614 } else { /* not ddr2 so use ddr333 */
619 else if (value <= 0x60) {
620 if (dram_type >= 1) dram_type = 1;
622 else dram_type = 0; /* ddr266 */
626 #if CONFIG_HAVE_OPTION_TABLE
627 if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
628 ecc = 0; /* ECC off in CMOS so disable it */
629 print_debug("ECC off\n");
633 print_debug("ECC on\n");
635 drc &= ~(3 << 20); /* clear the ecc bits */
636 drc |= (ecc << 20); /* or in the calculated ecc bits */
637 for ( cnt = 1; cnt < 5; cnt++)
638 if (drc_rates[cnt] == rate)
641 drc &= ~(7 << 8); /* clear the rate bits */
645 if (reg == 8) { /* independant clocks */
649 drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
650 drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
653 value = msr.lo >> 16;
655 drc &= ~(3 << 2); /* set the front side bus */
656 drc |= (fsb_conversion[value] << 2);
657 drc &= ~(3 << 0); /* set the dram type */
658 drc |= (dram_type << 0);
663 die("Bad SPD value\n");
664 /* If an hw_error occurs report that I have no memory */
671 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
675 /* Test if we can read the spd and if ram is ddr or ddr2 */
676 dimm_mask = spd_detect_dimms(ctrl);
677 if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
678 print_err("No memory for this cpu\n");
684 static void do_delay(void)
692 #define TIMEOUT_LOOPS 300000
694 #define DCALCSR 0x100
695 #define DCALADDR 0x104
696 #define DCALDATA 0x108
698 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
705 /* Set up northbridge values */
707 pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
708 /* Figure out which slots are Empty, Single, or Double sided */
709 for(i=0,t4=0,c2=0;i<8;i+=2) {
710 c1 = pci_read_config8(ctrl->f0, DRB+i);
711 if(c1 == c2) continue;
712 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
720 if( ((t4>>8)&0x0f) == 0 ) {
721 data32 = 0x00000010; /* EEES */
724 if ( ((t4>>16)&0x0f) == 0 ) {
725 data32 = 0x00003132; /* EESS */
728 if ( ((t4>>24)&0x0f) == 0 ) {
729 data32 = 0x00335566; /* ESSS */
732 data32 = 0x77bbddee; /* SSSS */
736 if( ((t4>>8)&0x0f) == 0 ) {
737 data32 = 0x00003132; /* EEED */
740 if ( ((t4>>8)&0x0f) == 2 ) {
741 data32 = 0xb373ecdc; /* EEDD */
744 if ( ((t4>>16)&0x0f) == 0 ) {
745 data32 = 0x00b3a898; /* EESD */
748 data32 = 0x777becdc; /* ESSD */
751 die("Error - First dimm slot empty\n");
754 print_debug("ODT Value = ");
755 print_debug_hex32(data32);
758 pci_write_config32(ctrl->f0, 0xb0, data32);
760 for(dimm=0;dimm<8;dimm+=1) {
762 write32(BAR+DCALADDR, 0x0b840001);
763 write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
765 for(i=0;i<1001;i++) {
766 data32 = read32(BAR+DCALCSR);
767 if(!(data32 & (1<<31)))
772 static void set_receive_enable(const struct mem_controller *ctrl)
775 unsigned int cnt,bit;
783 uint32_t data32_dram;
784 uint32_t dcal_data32_0;
785 uint32_t dcal_data32_1;
786 uint32_t dcal_data32_2;
787 uint32_t dcal_data32_3;
792 for(dimm=0;dimm<8;dimm+=1) {
795 write32(BAR+DCALDATA+(17*4), 0x04020000);
796 write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
798 for(i=0;i<1001;i++) {
799 data32 = read32(BAR+DCALCSR);
800 if(!(data32 & (1<<31)))
806 dcal_data32_0 = read32(BAR+DCALDATA + 0);
807 dcal_data32_1 = read32(BAR+DCALDATA + 4);
808 dcal_data32_2 = read32(BAR+DCALDATA + 8);
809 dcal_data32_3 = read32(BAR+DCALDATA + 12);
812 dcal_data32_0 = read32(BAR+DCALDATA + 16);
813 dcal_data32_1 = read32(BAR+DCALDATA + 20);
814 dcal_data32_2 = read32(BAR+DCALDATA + 24);
815 dcal_data32_3 = read32(BAR+DCALDATA + 28);
818 /* check if bank is installed */
819 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
821 /* Calculate the timing value */
822 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
823 work32l=dcal_data32_1,work32h=dcal_data32_3;
826 if(work32l & (1<<cnt))
829 work32l = dcal_data32_0;
830 work32h = dcal_data32_2;
836 if(!(work32l & (1<<cnt)))
839 work32l = dcal_data32_0;
840 work32h = dcal_data32_2;
848 data32 = ((bit%8) << 1);
849 if(work32h & (1<<cnt))
874 work32l = dcal_data32_0;
875 work32h = dcal_data32_2;
881 if(!(work32l & (1<<cnt)))
884 if(work32l & (1<<cnt))
887 data32 = (((cnt-1)%8)<<1);
888 if(work32h & (1<<(cnt-1))) {
891 /* test for frame edge cross overs */
892 if((edge == 1) && (data32 > 12) &&
893 (((recen+16)-data32) < 3)) {
897 if((edge == 2) && (data32 < 4) &&
898 ((recen - data32) > 12)) {
902 if(((recen+3) >= data32) && ((recen-3) <= data32))
913 recen <<= (dimm/2) * 8;
922 /* Check for Eratta problem */
923 for(i=cnt=bit=0;i<4;i++) {
924 if (((recena>>(i*8))&0x0f)>7) {
928 if((recena>>(i*8))&0x0f) {
937 if(((recena>>(i*8))&0x0f)>7) {
938 recena &= ~(0x0f<<(i*8));
939 recena |= (7<<(i*8));
945 if(((recena>>(i*8))&0x0f)<8) {
946 recena &= ~(0x0f<<(i*8));
947 recena |= (8<<(i*8));
952 for(i=cnt=bit=0;i<4;i++) {
953 if (((recenb>>(i*8))&0x0f)>7) {
957 if((recenb>>(i*8))&0x0f) {
966 if(((recenb>>(i*8))&0x0f)>7) {
967 recenb &= ~(0x0f<<(i*8));
968 recenb |= (7<<(i*8));
974 if(((recenb>>(i*8))&0x0f)<8) {
975 recenb &= ~(0x0f<<(i*8));
976 recenb |= (8<<(i*8));
982 // recena = 0x0000090a;
983 // recenb = 0x0000090a;
985 print_debug("Receive enable A = ");
986 print_debug_hex32(recena);
987 print_debug(", Receive enable B = ");
988 print_debug_hex32(recenb);
991 /* clear out the calibration area */
992 write32(BAR+DCALDATA+(16*4), 0x00000000);
993 write32(BAR+DCALDATA+(17*4), 0x00000000);
994 write32(BAR+DCALDATA+(18*4), 0x00000000);
995 write32(BAR+DCALDATA+(19*4), 0x00000000);
998 write32(BAR+DCALCSR, 0x0000000f);
1000 write32(BAR+0x150, recena);
1001 write32(BAR+0x154, recenb);
1005 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1016 volatile unsigned long *iptrv;
1021 static const struct {
1024 /* FSB 133 DIMM 266 */
1025 {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1026 /* FSB 133 DIMM 333 */
1027 {{ 0x00000000, 0x00000000, 0x00000000, 0x00000000}},
1028 /* FSB 133 DIMM 400 */
1029 {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
1030 /* FSB 167 DIMM 266 */
1031 {{ 0x00005432, 0x00001000, 0x00004325, 0x00000000}},
1032 /* FSB 167 DIMM 333 */
1033 {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1034 /* FSB 167 DIMM 400 */
1035 {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
1036 /* FSB 200 DIMM 266 */
1037 {{ 0x00000032, 0x00000010, 0x00000120, 0x00000000}},
1038 /* FSB 200 DIMM 333 */
1039 {{ 0x00065432, 0x00010000, 0x00054326, 0x00000000}},
1040 /* FSB 200 DIMM 400 */
1041 {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1044 static const uint32_t dqs_data[] = {
1045 0xffffffff, 0xffffffff, 0x000000ff,
1046 0xffffffff, 0xffffffff, 0x000000ff,
1047 0xffffffff, 0xffffffff, 0x000000ff,
1048 0xffffffff, 0xffffffff, 0x000000ff,
1049 0xffffffff, 0xffffffff, 0x000000ff,
1050 0xffffffff, 0xffffffff, 0x000000ff,
1051 0xffffffff, 0xffffffff, 0x000000ff,
1052 0xffffffff, 0xffffffff, 0x000000ff};
1054 mask = spd_detect_dimms(ctrl);
1055 print_debug("Starting SDRAM Enable\n");
1058 #ifdef DIMM_MAP_LOGICAL
1059 pci_write_config32(ctrl->f0, DRM,
1060 0x00210000 | DIMM_MAP_LOGICAL);
1062 pci_write_config32(ctrl->f0, DRM, 0x00211248);
1064 /* set dram type and Front Side Bus freq. */
1065 drc = spd_set_dram_controller_mode(ctrl, mask);
1067 die("Error calculating DRC\n");
1069 data32 = drc & ~(3 << 20); /* clear ECC mode */
1070 data32 = data32 & ~(7 << 8); /* clear refresh rates */
1071 data32 = data32 | (1 << 5); /* temp turn off of ODT */
1072 /* Set gearing, then dram controller mode */
1073 /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
1074 for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
1076 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1079 pci_write_config32(ctrl->f0, DRC, data32);
1081 /* turn the clocks on */
1083 pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1085 /* 0x9a DDRCSR Take subsystem out of idle */
1086 data16 = pci_read_config16(ctrl->f0, DDRCSR);
1087 data16 &= ~(7 << 12);
1088 data16 |= (3 << 12); /* use dual channel lock step */
1089 pci_write_config16(ctrl->f0, DDRCSR, data16);
1091 /* program row size DRB */
1092 spd_set_ram_size(ctrl, mask);
1094 /* program page size DRA */
1095 spd_set_row_attributes(ctrl, mask);
1097 /* program DRT timing values */
1098 cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1100 for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
1101 print_debug("DIMM ");
1102 print_debug_hex8(i);
1107 write32(BAR + 0x100, (0x03000000 | (i<<20)));
1109 write32(BAR+0x100, (0x83000000 | (i<<20)));
1111 data32 = read32(BAR+DCALCSR);
1112 while(data32 & 0x80000000)
1113 data32 = read32(BAR+DCALCSR);
1120 for(cs=0;cs<8;cs++) {
1121 write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
1122 data32 = read32(BAR+DCALCSR);
1123 while(data32 & 0x80000000)
1124 data32 = read32(BAR+DCALCSR);
1127 /* Precharg all banks */
1129 for(cs=0;cs<8;cs++) {
1130 if ((drc & 3) == 2) /* DDR2 */
1131 write32(BAR+DCALADDR, 0x04000000);
1133 write32(BAR+DCALADDR, 0x00000000);
1134 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1135 data32 = read32(BAR+DCALCSR);
1136 while(data32 & 0x80000000)
1137 data32 = read32(BAR+DCALCSR);
1140 /* EMRS dll's enabled */
1142 for(cs=0;cs<8;cs++) {
1143 if ((drc & 3) == 2) /* DDR2 */
1144 /* fixme hard code AL additive latency */
1145 write32(BAR+DCALADDR, 0x0b940001);
1147 write32(BAR+DCALADDR, 0x00000001);
1148 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1149 data32 = read32(BAR+DCALCSR);
1150 while(data32 & 0x80000000)
1151 data32 = read32(BAR+DCALCSR);
1153 /* MRS reset dll's */
1155 if ((drc & 3) == 2) { /* DDR2 */
1156 if(cas_latency == 30)
1157 mode_reg = 0x053a0000;
1159 mode_reg = 0x054a0000;
1162 if(cas_latency == 20)
1163 mode_reg = 0x012a0000;
1164 else /* CAS Latency 2.5 */
1165 mode_reg = 0x016a0000;
1167 for(cs=0;cs<8;cs++) {
1168 write32(BAR+DCALADDR, mode_reg);
1169 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1170 data32 = read32(BAR+DCALCSR);
1171 while(data32 & 0x80000000)
1172 data32 = read32(BAR+DCALCSR);
1175 /* Precharg all banks */
1179 for(cs=0;cs<8;cs++) {
1180 if ((drc & 3) == 2) /* DDR2 */
1181 write32(BAR+DCALADDR, 0x04000000);
1183 write32(BAR+DCALADDR, 0x00000000);
1184 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1185 data32 = read32(BAR+DCALCSR);
1186 while(data32 & 0x80000000)
1187 data32 = read32(BAR+DCALCSR);
1190 /* Do 2 refreshes */
1192 for(cs=0;cs<8;cs++) {
1193 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1194 data32 = read32(BAR+DCALCSR);
1195 while(data32 & 0x80000000)
1196 data32 = read32(BAR+DCALCSR);
1199 for(cs=0;cs<8;cs++) {
1200 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1201 data32 = read32(BAR+DCALCSR);
1202 while(data32 & 0x80000000)
1203 data32 = read32(BAR+DCALCSR);
1206 /* for good luck do 6 more */
1207 for(cs=0;cs<8;cs++) {
1208 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1211 for(cs=0;cs<8;cs++) {
1212 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1215 for(cs=0;cs<8;cs++) {
1216 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1219 for(cs=0;cs<8;cs++) {
1220 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1223 for(cs=0;cs<8;cs++) {
1224 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1227 for(cs=0;cs<8;cs++) {
1228 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1231 /* MRS reset dll's normal */
1233 for(cs=0;cs<8;cs++) {
1234 write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
1235 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1236 data32 = read32(BAR+DCALCSR);
1237 while(data32 & 0x80000000)
1238 data32 = read32(BAR+DCALCSR);
1241 /* Do only if DDR2 EMRS dll's enabled */
1242 if ((drc & 3) == 2) { /* DDR2 */
1244 for(cs=0;cs<8;cs++) {
1245 write32(BAR+DCALADDR, (0x0b940001));
1246 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1247 data32 = read32(BAR+DCALCSR);
1248 while(data32 & 0x80000000)
1249 data32 = read32(BAR+DCALCSR);
1255 write32(BAR+DCALCSR, 0x0000000f);
1257 /* DDR1 This is test code to copy some codes in the factory setup */
1259 write32(BAR, 0x00100000);
1261 if ((drc & 3) == 2) { /* DDR2 */
1262 /* enable on dimm termination */
1263 set_on_dimm_termination_enable(ctrl);
1266 /* receive enable calibration */
1267 set_receive_enable(ctrl);
1270 pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1271 for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
1272 write32(cnt, dqs_data[i]);
1274 pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1276 /* Enable refresh */
1278 data32 = drc & ~(3 << 20); /* clear ECC mode */
1279 pci_write_config32(ctrl->f0, DRC, data32);
1280 write32(BAR+DCALCSR, 0x0008000f);
1282 /* clear memory and init ECC */
1283 print_debug("Clearing memory\n");
1284 for(i=0;i<64;i+=4) {
1285 write32(BAR+DCALDATA+i, 0x00000000);
1288 for(cs=0;cs<8;cs++) {
1289 write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
1290 data32 = read32(BAR+DCALCSR);
1291 while(data32 & 0x80000000)
1292 data32 = read32(BAR+DCALCSR);
1295 /* Bring memory subsystem on line */
1296 data32 = pci_read_config32(ctrl->f0, 0x98);
1297 data32 |= (1 << 31);
1298 pci_write_config32(ctrl->f0, 0x98, data32);
1299 /* wait for completion */
1300 print_debug("Waiting for mem complete\n");
1302 data32 = pci_read_config32(ctrl->f0, 0x98);
1303 if( (data32 & (1<<31)) == 0)
1306 print_debug("Done\n");
1308 /* Set initialization complete */
1311 data32 = drc & ~(3 << 20); /* clear ECC mode */
1312 pci_write_config32(ctrl->f0, DRC, data32);
1314 /* Set the ecc mode */
1315 pci_write_config32(ctrl->f0, DRC, drc);
1317 /* Enable memory scrubbing */
1319 data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1321 data16 |= ((2 << 2) | (2 << 0));
1322 pci_write_config16(ctrl->f0, MCHSCRB, data16);
1324 /* The memory is now setup, use it */
1325 cache_lbmem(MTRR_TYPE_WRBACK);