src/northbridge/intel/e7520/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 #include <cpu/x86/mem.h>
  22 #include <cpu/x86/mtrr.h>
  23 #include <cpu/x86/cache.h>
  24 #include <stdlib.h>
  25 #include "raminit.h"
  26 #include "e7520.h"
  27
  28 #define BAR 0x40000000
  29
  30 static void sdram_set_registers(const struct mem_controller *ctrl)
  31 {
  32         static const unsigned int register_values[] = {
  33
  34                 /* CKDIS 0x8c disable clocks */
  35         PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
  36
  37                 /* 0x9c Device present and extended RAM control
  38                  * DEVPRES is very touchy, hard code the initialization
  39                  * of PCI-E ports here.
  40                  */
  41         PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
  42
  43                 /* 0xc8 Remap RAM base and limit off */
  44         PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
  45
  46                 /* ??? */
  47         PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
  48         PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
  49
  50                 /* 0x50 scrub */
  51         PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
  52
  53                 /* 0x58 0x5c PAM */
  54         PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
  55         PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
  56
  57                 /* 0xf4 */
  58         PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
  59
  60                 /* 0x14 */
  61         PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
  62         };
  63         int i;
  64         int max;
  65
  66         max = ARRAY_SIZE(register_values);
  67         for(i = 0; i < max; i += 3) {
  68                 device_t dev;
  69                 unsigned where;
  70                 unsigned long reg;
  71                 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
  72                 where = register_values[i] & 0xff;
  73                 reg = pci_read_config32(dev, where);
  74                 reg &= register_values[i+1];
  75                 reg |= register_values[i+2];
  76                 pci_write_config32(dev, where, reg);
  77         }
  78         print_spew("done.\r\n");
  79 }
  80
  81
  82
  83 struct dimm_size {
  84         unsigned long side1;
  85         unsigned long side2;
  86 };
  87
  88 static struct dimm_size spd_get_dimm_size(unsigned device)
  89 {
  90         /* Calculate the log base 2 size of a DIMM in bits */
  91         struct dimm_size sz;
  92         int value, low, ddr2;
  93         sz.side1 = 0;
  94         sz.side2 = 0;
  95
  96         /* test for ddr2 */
  97         ddr2=0;
  98         value = spd_read_byte(device, 2);       /* type */
  99         if (value < 0) goto hw_err;
 100         if (value == 8) ddr2 = 1;
 101
 102         /* Note it might be easier to use byte 31 here, it has the DIMM size as
 103          * a multiple of 4MB.  The way we do it now we can size both
 104          * sides of an assymetric dimm.
 105          */
 106         value = spd_read_byte(device, 3);       /* rows */
 107         if (value < 0) goto hw_err;
 108         if ((value & 0xf) == 0) goto val_err;
 109         sz.side1 += value & 0xf;
 110
 111         value = spd_read_byte(device, 4);       /* columns */
 112         if (value < 0) goto hw_err;
 113         if ((value & 0xf) == 0) goto val_err;
 114         sz.side1 += value & 0xf;
 115
 116         value = spd_read_byte(device, 17);      /* banks */
 117         if (value < 0) goto hw_err;
 118         if ((value & 0xff) == 0) goto val_err;
 119         sz.side1 += log2(value & 0xff);
 120
 121         /* Get the module data width and convert it to a power of two */
 122         value = spd_read_byte(device, 7);       /* (high byte) */
 123         if (value < 0) goto hw_err;
 124         value &= 0xff;
 125         value <<= 8;
 126
 127         low = spd_read_byte(device, 6); /* (low byte) */
 128         if (low < 0) goto hw_err;
 129         value = value | (low & 0xff);
 130         if ((value != 72) && (value != 64)) goto val_err;
 131         sz.side1 += log2(value);
 132
 133         /* side 2 */
 134         value = spd_read_byte(device, 5);       /* number of physical banks */
 135
 136         if (value < 0) goto hw_err;
 137         value &= 7;
 138         if(ddr2) value++;
 139         if (value == 1) goto out;
 140         if (value != 2) goto val_err;
 141
 142         /* Start with the symmetrical case */
 143         sz.side2 = sz.side1;
 144
 145         value = spd_read_byte(device, 3);       /* rows */
 146         if (value < 0) goto hw_err;
 147         if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
 148         sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
 149         sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
 150
 151         value = spd_read_byte(device, 4);       /* columns */
 152         if (value < 0) goto hw_err;
 153         if ((value & 0xff) == 0) goto val_err;
 154         sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
 155         sz.side2 += ((value >> 4) & 0x0f);      /* Add in columsn on side 2 */
 156         goto out;
 157
 158  val_err:
 159         die("Bad SPD value\r\n");
 160         /* If an hw_error occurs report that I have no memory */
 161 hw_err:
 162         sz.side1 = 0;
 163         sz.side2 = 0;
 164  out:
 165         return sz;
 166
 167 }
 168
 169 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 170 {
 171         int i;
 172         int cum;
 173
 174         for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 175                 struct dimm_size sz;
 176                 if (dimm_mask & (1 << i)) {
 177                         sz = spd_get_dimm_size(ctrl->channel0[i]);
 178                         if (sz.side1 < 29) {
 179                                 return -1; /* Report SPD error */
 180                         }
 181                         /* convert bits to multiples of 64MB */
 182                         sz.side1 -= 29;
 183                         cum += (1 << sz.side1);
 184                         /* DRB = 0x60 */
 185                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 186                         if( sz.side2 > 28) {
 187                                 sz.side2 -= 29;
 188                                 cum += (1 << sz.side2);
 189                         }
 190                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 191                 }
 192                 else {
 193                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 194                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 195                 }
 196         }
 197         /* set TOM top of memory 0xcc */
 198         pci_write_config16(ctrl->f0, TOM, cum);
 199         /* set TOLM top of low memory */
 200         if(cum > 0x18) {
 201                 cum = 0x18;
 202         }
 203         cum <<= 11;
 204         /* 0xc4 TOLM */
 205         pci_write_config16(ctrl->f0, TOLM, cum);
 206         return 0;
 207 }
 208
 209
 210 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 211 {
 212         unsigned dimm_mask;
 213         int i;
 214         dimm_mask = 0;
 215         for(i = 0; i < DIMM_SOCKETS; i++) {
 216                 int byte;
 217                 unsigned device;
 218                 device = ctrl->channel0[i];
 219                 if (device) {
 220                         byte = spd_read_byte(device, 2);  /* Type */
 221                         if ((byte == 7) || (byte == 8)) {
 222                                 dimm_mask |= (1 << i);
 223                         }
 224                 }
 225                 device = ctrl->channel1[i];
 226                 if (device) {
 227                         byte = spd_read_byte(device, 2);
 228                         if ((byte == 7) || (byte == 8)) {
 229                                 dimm_mask |= (1 << (i + DIMM_SOCKETS));
 230                         }
 231                 }
 232         }
 233         return dimm_mask;
 234 }
 235
 236
 237 static int spd_set_row_attributes(const struct mem_controller *ctrl,
 238                 long dimm_mask)
 239 {
 240
 241         int value;
 242         int reg;
 243         int dra;
 244         int cnt;
 245
 246         dra = 0;
 247         for(cnt=0; cnt < 4; cnt++) {
 248                 if (!(dimm_mask & (1 << cnt))) {
 249                         continue;
 250                 }
 251                 reg =0;
 252                 value = spd_read_byte(ctrl->channel0[cnt], 3);  /* rows */
 253                 if (value < 0) goto hw_err;
 254                 if ((value & 0xf) == 0) goto val_err;
 255                 reg += value & 0xf;
 256
 257                 value = spd_read_byte(ctrl->channel0[cnt], 4);  /* columns */
 258                 if (value < 0) goto hw_err;
 259                 if ((value & 0xf) == 0) goto val_err;
 260                 reg += value & 0xf;
 261
 262                 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
 263                 if (value < 0) goto hw_err;
 264                 if ((value & 0xff) == 0) goto val_err;
 265                 reg += log2(value & 0xff);
 266
 267                 /* Get the device width and convert it to a power of two */
 268                 value = spd_read_byte(ctrl->channel0[cnt], 13);
 269                 if (value < 0) goto hw_err;
 270                 value = log2(value & 0xff);
 271                 reg += value;
 272                 if(reg < 27) goto hw_err;
 273                 reg -= 27;
 274                 reg += (value << 2);
 275
 276                 dra += reg << (cnt*8);
 277                 value = spd_read_byte(ctrl->channel0[cnt], 5);
 278                 if (value & 2)
 279                         dra += reg << ((cnt*8)+4);
 280         }
 281
 282         /* 0x70 DRA */
 283         pci_write_config32(ctrl->f0, DRA, dra);
 284         goto out;
 285
 286  val_err:
 287         die("Bad SPD value\r\n");
 288         /* If an hw_error occurs report that I have no memory */
 289 hw_err:
 290         dra = 0;
 291  out:
 292         return dra;
 293
 294 }
 295
 296
 297 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 298                 long dimm_mask, uint32_t drc)
 299 {
 300         int value;
 301         int reg;
 302         uint32_t drt;
 303         int cnt;
 304         int first_dimm;
 305         int cas_latency=0;
 306         int latency;
 307         uint32_t index = 0;
 308         uint32_t index2 = 0;
 309         static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
 310         static const int latency_indicies[] = { 26, 23, 9 };
 311
 312         /* 0x78 DRT */
 313         drt = pci_read_config32(ctrl->f0, DRT);
 314         drt &= 3;  /* save bits 1:0 */
 315
 316         for(first_dimm = 0; first_dimm < 4; first_dimm++) {
 317                 if (dimm_mask & (1 << first_dimm))
 318                         break;
 319         }
 320
 321         /* get dimm type */
 322         value = spd_read_byte(ctrl->channel0[first_dimm], 2);
 323         if(value == 8) {
 324                 drt |= (3<<5); /* back to bark write turn around & cycle add */
 325         }
 326
 327         drt |= (3<<18);  /* Trasmax */
 328
 329         for(cnt=0; cnt < 4; cnt++) {
 330                 if (!(dimm_mask & (1 << cnt))) {
 331                         continue;
 332                 }
 333                 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 334                 /* Compute the lowest cas latency supported */
 335                 latency = log2(reg) -2;
 336
 337                 /* Loop through and find a fast clock with a low latency */
 338                 for(index = 0; index < 3; index++, latency++) {
 339                         if ((latency < 2) || (latency > 4) ||
 340                                 (!(reg & (1 << latency)))) {
 341                                 continue;
 342                         }
 343                         value = spd_read_byte(ctrl->channel0[cnt],
 344                                         latency_indicies[index]);
 345
 346                         if(value <= cycle_time[drc&3]) {
 347                                 if( latency > cas_latency) {
 348                                         cas_latency = latency;
 349                                 }
 350                                 break;
 351                         }
 352                 }
 353         }
 354         index = (cas_latency-2);
 355         if((index)==0) cas_latency = 20;
 356         else if((index)==1) cas_latency = 25;
 357         else cas_latency = 30;
 358
 359         for(cnt=0;cnt<4;cnt++) {
 360                 if (!(dimm_mask & (1 << cnt))) {
 361                         continue;
 362                 }
 363                 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
 364                 if(((index>>8)&0x0ff)<reg) {
 365                         index &= ~(0x0ff << 8);
 366                         index |= (reg << 8);
 367                 }
 368                 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
 369                 if(((index>>16)&0x0ff)<reg) {
 370                         index &= ~(0x0ff << 16);
 371                         index |= (reg<<16);
 372                 }
 373                 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
 374                 if(((index2>>0)&0x0ff)<reg) {
 375                         index2 &= ~(0x0ff << 0);
 376                         index2 |= (reg<<0);
 377                 }
 378                 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
 379                 if(((index2>>8)&0x0ff)<reg) {
 380                         index2 &= ~(0x0ff << 8);
 381                         index2 |= (reg<<8);
 382                 }
 383                 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
 384                 if(((index2>>16)&0x0ff)<reg) {
 385                         index2 &= ~(0x0ff << 16);
 386                         index2 |= (reg<<16);
 387                 }
 388         }
 389
 390         /* get dimm speed */
 391         value = cycle_time[drc&3];
 392         if(value <= 0x50) {  /* 200 MHz */
 393                 if((index&7) > 2) {
 394                         drt |= (2<<2);  /* CAS latency 4 */
 395                         cas_latency = 40;
 396                 } else {
 397                         drt |= (1<<2);  /* CAS latency 3 */
 398                         cas_latency = 30;
 399                 }
 400                 if((index&0x0ff00)<=0x03c00) {
 401                         drt |= (1<<8);  /* Trp RAS Precharg */
 402                 } else {
 403                         drt |= (2<<8);  /* Trp RAS Precharg */
 404                 }
 405
 406                 /* Trcd RAS to CAS delay */
 407                 if((index2&0x0ff)<=0x03c) {
 408                         drt |= (0<<10);
 409                 } else {
 410                         drt |= (1<<10);
 411                 }
 412
 413                 /* Tdal Write auto precharge recovery delay */
 414                 drt |= (1<<12);
 415
 416                 /* Trc TRS min */
 417                 if((index2&0x0ff00)<=0x03700)
 418                         drt |= (0<<14);
 419                 else if((index2&0xff00)<=0x03c00)
 420                         drt |= (1<<14);
 421                 else
 422                         drt |= (2<<14); /* spd 41 */
 423
 424                 drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 425
 426                 /* Trrd Row Delay */
 427                 if((index&0x0ff0000)<=0x0140000) {
 428                         drt |= (0<<20);
 429                 } else if((index&0x0ff0000)<=0x0280000) {
 430                         drt |= (1<<20);
 431                 } else if((index&0x0ff0000)<=0x03c0000) {
 432                         drt |= (2<<20);
 433                 } else {
 434                         drt |= (3<<20);
 435                 }
 436
 437                 /* Trfc Auto refresh cycle time */
 438                 if((index2&0x0ff0000)<=0x04b0000) {
 439                         drt |= (0<<22);
 440                 } else if((index2&0x0ff0000)<=0x0690000) {
 441                         drt |= (1<<22);
 442                 } else {
 443                         drt |= (2<<22);
 444                 }
 445                 /* Docs say use 55 for all 200Mhz */
 446                 drt |= (0x055<<24);
 447         }
 448         else if(value <= 0x60) { /* 167 Mhz */
 449                 /* according to new documentation CAS latency is 00
 450                  * for bits 3:2 for all 167 Mhz
 451                 drt |= ((index&3)<<2); */  /* set CAS latency */
 452                 if((index&0x0ff00)<=0x03000) {
 453                         drt |= (1<<8);  /* Trp RAS Precharg */
 454                 } else {
 455                         drt |= (2<<8);  /* Trp RAS Precharg */
 456                 }
 457
 458                 /* Trcd RAS to CAS delay */
 459                 if((index2&0x0ff)<=0x030) {
 460                         drt |= (0<<10);
 461                 } else {
 462                         drt |= (1<<10);
 463                 }
 464
 465                 /* Tdal Write auto precharge recovery delay */
 466                 drt |= (2<<12);
 467
 468                 /* Trc TRS min */
 469                 drt |= (2<<14); /* spd 41, but only one choice */
 470
 471                 drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 472
 473                 /* Trrd Row Delay */
 474                 if((index&0x0ff0000)<=0x0180000) {
 475                         drt |= (0<<20);
 476                 } else if((index&0x0ff0000)<=0x0300000) {
 477                         drt |= (1<<20);
 478                 } else {
 479                         drt |= (2<<20);
 480                 }
 481
 482                 /* Trfc Auto refresh cycle time */
 483                 if((index2&0x0ff0000)<=0x0480000) {
 484                         drt |= (0<<22);
 485                 } else if((index2&0x0ff0000)<=0x0780000) {
 486                         drt |= (2<<22);
 487                 } else {
 488                         drt |= (2<<22);
 489                 }
 490                 /* Docs state to use 99 for all 167 Mhz */
 491                 drt |= (0x099<<24);
 492         }
 493         else if(value <= 0x75) { /* 133 Mhz */
 494                 drt |= ((index&3)<<2);  /* set CAS latency */
 495                 if((index&0x0ff00)<=0x03c00) {
 496                         drt |= (1<<8);  /* Trp RAS Precharg */
 497                 } else {
 498                         drt |= (2<<8);  /* Trp RAS Precharg */
 499                 }
 500
 501                 /* Trcd RAS to CAS delay */
 502                 if((index2&0x0ff)<=0x03c) {
 503                         drt |= (0<<10);
 504                 } else {
 505                         drt |= (1<<10);
 506                 }
 507
 508                 /* Tdal Write auto precharge recovery delay */
 509                 drt |= (1<<12);
 510
 511                 /* Trc TRS min */
 512                 drt |= (2<<14); /* spd 41, but only one choice */
 513
 514                 drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 515
 516                 /* Trrd Row Delay */
 517                 if((index&0x0ff0000)<=0x01e0000) {
 518                         drt |= (0<<20);
 519                 } else if((index&0x0ff0000)<=0x03c0000) {
 520                         drt |= (1<<20);
 521                 } else {
 522                         drt |= (2<<20);
 523                 }
 524
 525                 /* Trfc Auto refresh cycle time */
 526                 if((index2&0x0ff0000)<=0x04b0000) {
 527                         drt |= (0<<22);
 528                 } else if((index2&0x0ff0000)<=0x0780000) {
 529                         drt |= (2<<22);
 530                 } else {
 531                         drt |= (2<<22);
 532                 }
 533
 534                 /* Based on CAS latency */
 535                 if(index&7)
 536                         drt |= (0x099<<24);
 537                 else
 538                         drt |= (0x055<<24);
 539
 540         }
 541         else {
 542                 die("Invalid SPD 9 bus speed.\r\n");
 543         }
 544
 545         /* 0x78 DRT */
 546         pci_write_config32(ctrl->f0, DRT, drt);
 547
 548         return(cas_latency);
 549 }
 550
 551 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 552                 long dimm_mask)
 553 {
 554         int value;
 555         int reg;
 556         int drc;
 557         int cnt;
 558         msr_t msr;
 559         unsigned char dram_type = 0xff;
 560         unsigned char ecc = 0xff;
 561         unsigned char rate = 62;
 562         static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
 563         static const unsigned char drc_rates[5] = {0,15,7,62,3};
 564         static const unsigned char fsb_conversion[4] = {3,1,3,2};
 565
 566         /* 0x7c DRC */
 567         drc = pci_read_config32(ctrl->f0, DRC);
 568         for(cnt=0; cnt < 4; cnt++) {
 569                 if (!(dimm_mask & (1 << cnt))) {
 570                         continue;
 571                 }
 572                 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
 573                 reg = spd_read_byte(ctrl->channel0[cnt], 2); /* Type */
 574                 if (value == 2) {    /* RAM is ECC capable */
 575                         if (reg == 8) {
 576                                 if ( ecc == 0xff ) {
 577                                         ecc = 2;
 578                                 }
 579                                 else if (ecc == 1) {
 580                                         die("ERROR - Mixed DDR & DDR2 RAM\r\n");
 581                                 }
 582                         }
 583                         else if ( reg == 7 ) {
 584                                 if ( ecc == 0xff) {
 585                                         ecc = 1;
 586                                 }
 587                                 else if ( ecc > 1 ) {
 588                                         die("ERROR - Mixed DDR & DDR2 RAM\r\n");
 589                                 }
 590                         }
 591                         else {
 592                                 die("ERROR - RAM not DDR\r\n");
 593                         }
 594                 }
 595                 else {
 596                         die("ERROR - Non ECC memory dimm\r\n");
 597                 }
 598
 599                 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
 600                 value &= 0x0f;    /* clip self refresh bit */
 601                 if (value > 5) goto hw_err;
 602                 if (rate > spd_rates[value])
 603                         rate = spd_rates[value];
 604
 605                 value = spd_read_byte(ctrl->channel0[cnt], 9);  /* cycle time */
 606                 if (value > 0x75) goto hw_err;
 607                 if (value <= 0x50) {
 608                         if (dram_type >= 2) {
 609                                 if (reg == 8) { /*speed is good, is this ddr2?*/
 610                                         dram_type = 2;
 611                                 } else { /* not ddr2 so use ddr333 */
 612                                         dram_type = 1;
 613                                 }
 614                         }
 615                 }
 616                 else if (value <= 0x60) {
 617                         if (dram_type >= 1)  dram_type = 1;
 618                 }
 619                 else dram_type = 0; /* ddr266 */
 620
 621         }
 622         ecc = 2;
 623         if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
 624                 ecc = 0;  /* ECC off in CMOS so disable it */
 625                 print_debug("ECC off\r\n");
 626         }
 627         else {
 628                 print_debug("ECC on\r\n");
 629         }
 630         drc &= ~(3 << 20); /* clear the ecc bits */
 631         drc |= (ecc << 20);  /* or in the calculated ecc bits */
 632         for ( cnt = 1; cnt < 5; cnt++)
 633                 if (drc_rates[cnt] == rate)
 634                         break;
 635         if (cnt < 5) {
 636                 drc &= ~(7 << 8);  /* clear the rate bits */
 637                 drc |= (cnt << 8);
 638         }
 639
 640         if (reg == 8) { /* independant clocks */
 641                 drc |= (1 << 4);
 642         }
 643
 644         drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
 645         drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
 646         /* front side bus */
 647         msr = rdmsr(0x2c);
 648         value = msr.lo >> 16;
 649         value &= 0x03;
 650         drc &= ~(3 << 2); /* set the front side bus */
 651         drc |= (fsb_conversion[value] << 2);
 652         drc &= ~(3 << 0); /* set the dram type */
 653         drc |= (dram_type << 0);
 654
 655         goto out;
 656
 657  val_err:
 658         die("Bad SPD value\r\n");
 659         /* If an hw_error occurs report that I have no memory */
 660 hw_err:
 661         drc = 0;
 662  out:
 663         return drc;
 664 }
 665
 666 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 667 {
 668         long dimm_mask;
 669
 670         /* Test if we can read the spd and if ram is ddr or ddr2 */
 671         dimm_mask = spd_detect_dimms(ctrl);
 672         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 673                 print_err("No memory for this cpu\r\n");
 674                 return;
 675         }
 676         return;
 677 }
 678
 679 static void do_delay(void)
 680 {
 681         int i;
 682         unsigned char b;
 683         for(i=0;i<16;i++)
 684                 b=inb(0x80);
 685 }
 686
 687 static void pll_setup(uint32_t drc)
 688 {
 689         unsigned pins;
 690         if(drc&3) { /* DDR 333 or DDR 400 */
 691                 if((drc&0x0c) == 0x0c) { /* FSB 200 */
 692                         pins = 2 | 1;
 693                 }
 694                 else if((drc&0x0c) == 0x08) {   /* FSB 167 */
 695                         pins = 0 | 1;
 696                 }
 697                 else if(drc&1){  /* FSB 133 DDR 333 */
 698                         pins = 2 | 1;
 699                 }
 700                 else { /* FSB 133 DDR 400 */
 701                         pins = 0 | 1;
 702                 }
 703         }
 704         else { /* DDR 266 */
 705                 if((drc&0x08) == 0x08) { /* FSB 200 or 167 */
 706                         pins = 0 | 0;
 707                 }
 708                 else { /* FSB 133 */
 709                         pins = 0 | 1;
 710                 }
 711         }
 712         mainboard_set_e7520_pll(pins);
 713         return;
 714 }
 715
 716 #define TIMEOUT_LOOPS 300000
 717
 718 #define DCALCSR  0x100
 719 #define DCALADDR 0x104
 720 #define DCALDATA 0x108
 721
 722 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 723 {
 724         unsigned char c1,c2;
 725         unsigned int dimm,i;
 726         unsigned int data32;
 727         unsigned int t4;
 728
 729         /* Set up northbridge values */
 730         /* ODT enable */
 731         pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
 732         /* Figure out which slots are Empty, Single, or Double sided */
 733         for(i=0,t4=0,c2=0;i<8;i+=2) {
 734                 c1 = pci_read_config8(ctrl->f0, DRB+i);
 735                 if(c1 == c2) continue;
 736                 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
 737                 if(c1 == c2)
 738                         t4 |= (1 << (i*4));
 739                 else
 740                         t4 |= (2 << (i*4));
 741         }
 742         for(i=0;i<1;i++) {
 743             if((t4&0x0f) == 1) {
 744                 if( ((t4>>8)&0x0f) == 0 ) {
 745                         data32 = 0x00000010; /* EEES */
 746                         break;
 747                 }
 748                 if ( ((t4>>16)&0x0f) == 0 ) {
 749                         data32 = 0x00003132; /* EESS */
 750                         break;
 751                 }
 752                 if ( ((t4>>24)&0x0f)  == 0 ) {
 753                         data32 = 0x00335566; /* ESSS */
 754                         break;
 755                 }
 756                 data32 = 0x77bbddee; /* SSSS */
 757                 break;
 758             }
 759             if((t4&0x0f) == 2) {
 760                 if( ((t4>>8)&0x0f) == 0 ) {
 761                         data32 = 0x00003132; /* EEED */
 762                         break;
 763                 }
 764                 if ( ((t4>>8)&0x0f) == 2 ) {
 765                         data32 = 0xb373ecdc; /* EEDD */
 766                         break;
 767                 }
 768                 if ( ((t4>>16)&0x0f) == 0 ) {
 769                         data32 = 0x00b3a898; /* EESD */
 770                         break;
 771                 }
 772                 data32 = 0x777becdc; /* ESSD */
 773                 break;
 774             }
 775             die("Error - First dimm slot empty\r\n");
 776         }
 777
 778         print_debug("ODT Value = ");
 779         print_debug_hex32(data32);
 780         print_debug("\r\n");
 781
 782         pci_write_config32(ctrl->f0, 0xb0, data32);
 783
 784         for(dimm=0;dimm<8;dimm+=1) {
 785
 786                 write32(BAR+DCALADDR, 0x0b840001);
 787                 write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
 788
 789                 for(i=0;i<1001;i++) {
 790                         data32 = read32(BAR+DCALCSR);
 791                         if(!(data32 & (1<<31)))
 792                                 break;
 793                 }
 794         }
 795 }
 796 static void set_receive_enable(const struct mem_controller *ctrl)
 797 {
 798         unsigned int i;
 799         unsigned int cnt;
 800         uint32_t recena=0;
 801         uint32_t recenb=0;
 802
 803         {
 804         unsigned int dimm;
 805         unsigned int edge;
 806         int32_t data32;
 807         uint32_t data32_dram;
 808         uint32_t dcal_data32_0;
 809         uint32_t dcal_data32_1;
 810         uint32_t dcal_data32_2;
 811         uint32_t dcal_data32_3;
 812         uint32_t work32l;
 813         uint32_t work32h;
 814         uint32_t data32r;
 815         int32_t recen;
 816         for(dimm=0;dimm<8;dimm+=1) {
 817
 818                 if(!(dimm&1)) {
 819                         write32(BAR+DCALDATA+(17*4), 0x04020000);
 820                         write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
 821
 822                         for(i=0;i<1001;i++) {
 823                                 data32 = read32(BAR+DCALCSR);
 824                                 if(!(data32 & (1<<31)))
 825                                         break;
 826                         }
 827                         if(i>=1000)
 828                                 continue;
 829
 830                         dcal_data32_0 = read32(BAR+DCALDATA + 0);
 831                         dcal_data32_1 = read32(BAR+DCALDATA + 4);
 832                         dcal_data32_2 = read32(BAR+DCALDATA + 8);
 833                         dcal_data32_3 = read32(BAR+DCALDATA + 12);
 834                 }
 835                 else {
 836                         dcal_data32_0 = read32(BAR+DCALDATA + 16);
 837                         dcal_data32_1 = read32(BAR+DCALDATA + 20);
 838                         dcal_data32_2 = read32(BAR+DCALDATA + 24);
 839                         dcal_data32_3 = read32(BAR+DCALDATA + 28);
 840                 }
 841
 842                 /* check if bank is installed */
 843                 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 844                         continue;
 845                 /* Calculate the timing value */
 846                 {
 847                 unsigned int bit;
 848                 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
 849                         work32l=dcal_data32_1,work32h=dcal_data32_3;
 850                                 (i<4) && bit; i++) {
 851                         for(;;bit--,cnt--) {
 852                                 if(work32l & (1<<cnt))
 853                                         break;
 854                                 if(!cnt) {
 855                                         work32l = dcal_data32_0;
 856                                         work32h = dcal_data32_2;
 857                                         cnt = 32;
 858                                 }
 859                                 if(!bit) break;
 860                         }
 861                         for(;;bit--,cnt--) {
 862                                 if(!(work32l & (1<<cnt)))
 863                                         break;
 864                                 if(!cnt) {
 865                                         work32l = dcal_data32_0;
 866                                         work32h = dcal_data32_2;
 867                                         cnt = 32;
 868                                 }
 869                                 if(!bit) break;
 870                         }
 871                         if(!bit) {
 872                                 break;
 873                         }
 874                         data32 = ((bit%8) << 1);
 875                         if(work32h & (1<<cnt))
 876                                 data32 += 1;
 877                         if(data32 < 4) {
 878                                 if(!edge) {
 879                                         edge = 1;
 880                                 }
 881                                 else {
 882                                         if(edge != 1) {
 883                                                 data32 = 0x0f;
 884                                         }
 885                                 }
 886                         }
 887                         if(data32 > 12) {
 888                                 if(!edge) {
 889                                         edge = 2;
 890                                 }
 891                                 else {
 892                                         if(edge != 2) {
 893                                                 data32 = 0x00;
 894                                         }
 895                                 }
 896                         }
 897                         data32r += data32;
 898                 }
 899                 }
 900                 work32l = dcal_data32_0;
 901                 work32h = dcal_data32_2;
 902                 recen = data32r;
 903                 recen += 3;
 904                 recen = recen>>2;
 905                 for(cnt=5;cnt<24;) {
 906                         for(;;cnt++)
 907                                 if(!(work32l & (1<<cnt)))
 908                                         break;
 909                         for(;;cnt++) {
 910                                 if(work32l & (1<<cnt))
 911                                         break;
 912                         }
 913                         data32 = (((cnt-1)%8)<<1);
 914                         if(work32h & (1<<(cnt-1))) {
 915                                 data32++;
 916                         }
 917                         /* test for frame edge cross overs */
 918                         if((edge == 1) && (data32 > 12) &&
 919                             (((recen+16)-data32) < 3)) {
 920                                 data32 = 0;
 921                                 cnt += 2;
 922                         }
 923                         if((edge == 2) && (data32 < 4) &&
 924                             ((recen - data32) > 12))  {
 925                                 data32 = 0x0f;
 926                                 cnt -= 2;
 927                         }
 928                         if(((recen+3) >= data32) && ((recen-3) <= data32))
 929                                 break;
 930                 }
 931                 cnt--;
 932                 cnt /= 8;
 933                 cnt--;
 934                 if(recen&1)
 935                         recen+=2;
 936                 recen >>= 1;
 937                 recen += (cnt*8);
 938                 recen+=2;      /* this is not in the spec, but matches
 939                                  the factory output, and has less failure */
 940                 recen <<= (dimm/2) * 8;
 941                 if(!(dimm&1)) {
 942                         recena |= recen;
 943                 }
 944                 else {
 945                         recenb |= recen;
 946                 }
 947         }
 948         }
 949         /* Check for Eratta problem */
 950         for(i=cnt=0;i<32;i+=8) {
 951                 if (((recena>>i)&0x0f)>7) {
 952                         cnt+= 0x101;
 953                 }
 954                 else {
 955                         if((recena>>i)&0x0f) {
 956                                 cnt++;
 957                         }
 958                 }
 959         }
 960         if(cnt&0x0f00) {
 961                 cnt = (cnt&0x0f) - (cnt>>16);
 962                 if(cnt>1) {
 963                         for(i=0;i<32;i+=8) {
 964                                 if(((recena>>i)&0x0f)>7) {
 965                                         recena &= ~(0x0f<<i);
 966                                         recena |= (7<<i);
 967                                 }
 968                         }
 969                 }
 970                 else {
 971                         for(i=0;i<32;i+=8) {
 972                                 if(((recena>>i)&0x0f)<8) {
 973                                         recena &= ~(0x0f<<i);
 974                                         recena |= (8<<i);
 975                                 }
 976                         }
 977                 }
 978         }
 979         for(i=cnt=0;i<32;i+=8) {
 980                 if (((recenb>>i)&0x0f)>7) {
 981                         cnt+= 0x101;
 982                 }
 983                 else {
 984                         if((recenb>>i)&0x0f) {
 985                                 cnt++;
 986                         }
 987                 }
 988         }
 989         if(cnt & 0x0f00) {
 990                 cnt = (cnt&0x0f) - (cnt>>16);
 991                 if(cnt>1) {
 992                         for(i=0;i<32;i+=8) {
 993                                 if(((recenb>>i)&0x0f)>7) {
 994                                         recenb &= ~(0x0f<<i);
 995                                         recenb |= (7<<i);
 996                                 }
 997                         }
 998                 }
 999                 else {
1000                         for(i=0;i<32;i+=8) {
1001                                 if(((recenb>>8)&0x0f)<8) {
1002                                         recenb &= ~(0x0f<<i);
1003                                         recenb |= (8<<i);
1004                                 }
1005                         }
1006                 }
1007         }
1008
1009         print_debug("Receive enable A = ");
1010         print_debug_hex32(recena);
1011         print_debug(",  Receive enable B = ");
1012         print_debug_hex32(recenb);
1013         print_debug("\r\n");
1014
1015         /* clear out the calibration area */
1016         write32(BAR+DCALDATA+(16*4), 0x00000000);
1017         write32(BAR+DCALDATA+(17*4), 0x00000000);
1018         write32(BAR+DCALDATA+(18*4), 0x00000000);
1019         write32(BAR+DCALDATA+(19*4), 0x00000000);
1020
1021         /* No command */
1022         write32(BAR+DCALCSR, 0x0000000f);
1023
1024         write32(BAR+0x150, recena);
1025         write32(BAR+0x154, recenb);
1026 }
1027
1028
1029 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1030 {
1031         int i;
1032         int cs;
1033         int cnt;
1034         int cas_latency;
1035         long mask;
1036         uint32_t drc;
1037         uint32_t data32;
1038         uint32_t mode_reg;
1039         uint32_t *iptr;
1040         volatile unsigned long *iptrv;
1041         msr_t msr;
1042         uint32_t scratch;
1043         uint8_t byte;
1044         uint16_t data16;
1045         static const struct {
1046                 uint32_t clkgr[4];
1047         } gearing [] = {
1048                 /* FSB 133 DIMM 266 */
1049         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1050                 /* FSB 133 DIMM 333 */
1051         {{ 0x00000000, 0x00000000, 0x00000000, 0x00000000}},
1052                 /* FSB 133 DIMM 400 */
1053         {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
1054                 /* FSB 167 DIMM 266 */
1055         {{ 0x00005432, 0x00001000, 0x00004325, 0x00000000}},
1056                 /* FSB 167 DIMM 333 */
1057         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1058                 /* FSB 167 DIMM 400 */
1059         {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
1060                 /* FSB 200 DIMM 266 */
1061         {{ 0x00000032, 0x00000010, 0x00000120, 0x00000000}},
1062                 /* FSB 200 DIMM 333 */
1063         {{ 0x00065432, 0x00010000, 0x00154320, 0x00000000}},
1064                 /* FSB 200 DIMM 400 */
1065         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1066         };
1067
1068         static const uint32_t dqs_data[] = {
1069                 0xffffffff, 0xffffffff, 0x000000ff,
1070                 0xffffffff, 0xffffffff, 0x000000ff,
1071                 0xffffffff, 0xffffffff, 0x000000ff,
1072                 0xffffffff, 0xffffffff, 0x000000ff,
1073                 0xffffffff, 0xffffffff, 0x000000ff,
1074                 0xffffffff, 0xffffffff, 0x000000ff,
1075                 0xffffffff, 0xffffffff, 0x000000ff,
1076                 0xffffffff, 0xffffffff, 0x000000ff};
1077
1078         mask = spd_detect_dimms(ctrl);
1079         print_debug("Starting SDRAM Enable\r\n");
1080
1081         /* 0x80 */
1082 #ifdef DIMM_MAP_LOGICAL
1083         pci_write_config32(ctrl->f0, DRM,
1084                 0x00210000 | DIMM_MAP_LOGICAL);
1085 #else
1086         pci_write_config32(ctrl->f0, DRM, 0x00211248);
1087 #endif
1088         /* set dram type and Front Side Bus freq. */
1089         drc = spd_set_dram_controller_mode(ctrl, mask);
1090         if( drc == 0) {
1091                 die("Error calculating DRC\r\n");
1092         }
1093         pll_setup(drc);
1094         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1095         data32 = data32 & ~(7 << 8);  /* clear refresh rates */
1096         data32 = data32 | (1 << 5);  /* temp turn off of ODT */
1097         /* Set gearing, then dram controller mode */
1098         /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
1099         for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
1100                         cnt<4;cnt++) {
1101                 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1102         }
1103         /* 0x7c DRC */
1104         pci_write_config32(ctrl->f0, DRC, data32);
1105
1106                 /* turn the clocks on */
1107         /* 0x8c CKDIS */
1108         pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1109
1110                 /* 0x9a DDRCSR Take subsystem out of idle */
1111         data16 = pci_read_config16(ctrl->f0, DDRCSR);
1112         data16 &= ~(7 << 12);
1113         data16 |= (3 << 12);   /* use dual channel lock step */
1114         pci_write_config16(ctrl->f0, DDRCSR, data16);
1115
1116                 /* program row size DRB */
1117         spd_set_ram_size(ctrl, mask);
1118
1119                 /* program page size DRA */
1120         spd_set_row_attributes(ctrl, mask);
1121
1122                 /* program DRT timing values */
1123         cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1124
1125         for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
1126                 print_debug("DIMM ");
1127                 print_debug_hex8(i);
1128                 print_debug("\r\n");
1129                 /* Apply NOP */
1130                 do_delay();
1131
1132                 write32(BAR + 0x100, (0x03000000 | (i<<20)));
1133
1134                 write32(BAR+0x100, (0x83000000 | (i<<20)));
1135
1136                 data32 = read32(BAR+DCALCSR);
1137                 while(data32 & 0x80000000)
1138                         data32 = read32(BAR+DCALCSR);
1139
1140         }
1141
1142         /* Apply NOP */
1143         do_delay();
1144
1145         for(cs=0;cs<8;cs++) {
1146                 write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
1147                 data32 = read32(BAR+DCALCSR);
1148                 while(data32 & 0x80000000)
1149                         data32 = read32(BAR+DCALCSR);
1150         }
1151
1152         /* Precharg all banks */
1153         do_delay();
1154         for(cs=0;cs<8;cs++) {
1155                 if ((drc & 3) == 2) /* DDR2  */
1156                         write32(BAR+DCALADDR, 0x04000000);
1157                 else   /* DDR1  */
1158                         write32(BAR+DCALADDR, 0x00000000);
1159                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1160                 data32 = read32(BAR+DCALCSR);
1161                 while(data32 & 0x80000000)
1162                         data32 = read32(BAR+DCALCSR);
1163         }
1164
1165         /* EMRS dll's enabled */
1166         do_delay();
1167         for(cs=0;cs<8;cs++) {
1168                 if ((drc & 3) == 2) /* DDR2  */
1169                         /* fixme hard code AL additive latency */
1170                         write32(BAR+DCALADDR, 0x0b940001);
1171                 else   /* DDR1  */
1172                         write32(BAR+DCALADDR, 0x00000001);
1173                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1174                 data32 = read32(BAR+DCALCSR);
1175                 while(data32 & 0x80000000)
1176                         data32 = read32(BAR+DCALCSR);
1177         }
1178         /* MRS reset dll's */
1179         do_delay();
1180         if ((drc & 3) == 2) {  /* DDR2  */
1181                 if(cas_latency == 30)
1182                         mode_reg = 0x053a0000;
1183                 else
1184                         mode_reg = 0x054a0000;
1185         }
1186         else {  /* DDR1  */
1187                 if(cas_latency == 20)
1188                         mode_reg = 0x012a0000;
1189                 else  /*  CAS Latency 2.5 */
1190                         mode_reg = 0x016a0000;
1191         }
1192         for(cs=0;cs<8;cs++) {
1193                 write32(BAR+DCALADDR, mode_reg);
1194                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1195                 data32 = read32(BAR+DCALCSR);
1196                 while(data32 & 0x80000000)
1197                         data32 = read32(BAR+DCALCSR);
1198         }
1199
1200         /* Precharg all banks */
1201         do_delay();
1202         do_delay();
1203         do_delay();
1204         for(cs=0;cs<8;cs++) {
1205                 if ((drc & 3) == 2) /* DDR2  */
1206                         write32(BAR+DCALADDR, 0x04000000);
1207                 else   /* DDR1  */
1208                         write32(BAR+DCALADDR, 0x00000000);
1209                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1210                 data32 = read32(BAR+DCALCSR);
1211                 while(data32 & 0x80000000)
1212                         data32 = read32(BAR+DCALCSR);
1213         }
1214
1215         /* Do 2 refreshes */
1216         do_delay();
1217         for(cs=0;cs<8;cs++) {
1218                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1219                 data32 = read32(BAR+DCALCSR);
1220                 while(data32 & 0x80000000)
1221                         data32 = read32(BAR+DCALCSR);
1222         }
1223         do_delay();
1224         for(cs=0;cs<8;cs++) {
1225                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1226                 data32 = read32(BAR+DCALCSR);
1227                 while(data32 & 0x80000000)
1228                         data32 = read32(BAR+DCALCSR);
1229         }
1230         do_delay();
1231         /* for good luck do 6 more */
1232         for(cs=0;cs<8;cs++) {
1233                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1234         }
1235         do_delay();
1236         for(cs=0;cs<8;cs++) {
1237                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1238         }
1239         do_delay();
1240         for(cs=0;cs<8;cs++) {
1241                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1242         }
1243         do_delay();
1244         for(cs=0;cs<8;cs++) {
1245                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1246         }
1247         do_delay();
1248         for(cs=0;cs<8;cs++) {
1249                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1250         }
1251         do_delay();
1252         for(cs=0;cs<8;cs++) {
1253                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1254         }
1255         do_delay();
1256         /* MRS reset dll's normal */
1257         do_delay();
1258         for(cs=0;cs<8;cs++) {
1259                 write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
1260                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1261                 data32 = read32(BAR+DCALCSR);
1262                 while(data32 & 0x80000000)
1263                         data32 = read32(BAR+DCALCSR);
1264         }
1265
1266         /* Do only if DDR2  EMRS dll's enabled */
1267         if ((drc & 3) == 2) { /* DDR2  */
1268                 do_delay();
1269                 for(cs=0;cs<8;cs++) {
1270                         write32(BAR+DCALADDR, (0x0b940001));
1271                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1272                         data32 = read32(BAR+DCALCSR);
1273                         while(data32 & 0x80000000)
1274                                 data32 = read32(BAR+DCALCSR);
1275                 }
1276         }
1277
1278         do_delay();
1279         /* No command */
1280         write32(BAR+DCALCSR, 0x0000000f);
1281
1282         /* DDR1 This is test code to copy some codes in the factory setup */
1283
1284         write32(BAR, 0x00100000);
1285
1286         if ((drc & 3) == 2) { /* DDR2  */
1287         /* enable on dimm termination */
1288                 set_on_dimm_termination_enable(ctrl);
1289         }
1290         else { /* ddr */
1291                 pci_write_config32(ctrl->f0, 0x88, 0xa0000000 );
1292         }
1293
1294         /* receive enable calibration */
1295         set_receive_enable(ctrl);
1296
1297         /* DQS */
1298         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1299         for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
1300                 write32(cnt, dqs_data[i]);
1301         }
1302         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1303
1304         /* Enable refresh */
1305         /* 0x7c DRC */
1306         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1307         pci_write_config32(ctrl->f0, DRC, data32);
1308         write32(BAR+DCALCSR, 0x0008000f);
1309
1310         /* clear memory and init ECC */
1311         print_debug("Clearing memory\r\n");
1312         for(i=0;i<64;i+=4) {
1313                 write32(BAR+DCALDATA+i, 0x00000000);
1314         }
1315
1316         for(cs=0;cs<8;cs++) {
1317                 write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
1318                 data32 = read32(BAR+DCALCSR);
1319                 while(data32 & 0x80000000)
1320                         data32 = read32(BAR+DCALCSR);
1321         }
1322
1323         /* Bring memory subsystem on line */
1324         data32 = pci_read_config32(ctrl->f0, 0x98);
1325         data32 |= (1 << 31);
1326         pci_write_config32(ctrl->f0, 0x98, data32);
1327         /* wait for completion */
1328         print_debug("Waiting for mem complete\r\n");
1329         while(1) {
1330                 data32 = pci_read_config32(ctrl->f0, 0x98);
1331                 if( (data32 & (1<<31)) == 0)
1332                         break;
1333         }
1334         print_debug("Done\r\n");
1335
1336         /* Set initialization complete */
1337         /* 0x7c DRC */
1338         drc |= (1 << 29);
1339         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1340         pci_write_config32(ctrl->f0, DRC, data32);
1341
1342         /* Set the ecc mode */
1343         pci_write_config32(ctrl->f0, DRC, drc);
1344
1345         /* Enable memory scrubbing */
1346         /* 0x52 MCHSCRB */
1347         data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1348         data16 &= ~0x0f;
1349         data16 |= ((2 << 2) | (2 << 0));
1350         pci_write_config16(ctrl->f0, MCHSCRB, data16);
1351
1352         /* The memory is now setup, use it */
1353         cache_lbmem(MTRR_TYPE_WRBACK);
1354 }