{
int i;
- int entries_num = sizeof(rsdt->entry)/sizeof(rsdt->entry[0]);
+ int entries_num = ARRAY_SIZE(rsdt->entry);
for (i=0; i<entries_num; i++) {
if(rsdt->entry[i]==0) {
{ LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
- for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(strings); i++) {
struct lb_string *rec;
size_t len;
rec = (struct lb_string *)lb_new_record(header);
{
const char *name;
name = "<invalid cpu vendor>";
- if ((vendor < (sizeof(x86_vendor_name)/sizeof(x86_vendor_name[0]))) &&
+ if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
(x86_vendor_name[vendor] != 0))
{
name = x86_vendor_name[vendor];
}
}
cpu->vendor = X86_VENDOR_UNKNOWN;
- for(i = 0; i < sizeof(x86_vendors)/sizeof(x86_vendors[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
cpu->vendor = x86_vendors[i].vendor;
break;
gdb_stub_registers[CS] = info->cs;
gdb_stub_registers[PS] = info->eflags;
signo = GDB_UNKNOWN;
- if (info->vector < sizeof(exception_to_signal)/sizeof(exception_to_signal[0])) {
+ if (info->vector < ARRAY_SIZE(exception_to_signal)) {
signo = exception_to_signal[info->vector];
}
l[0] = 0x03;
l[4] = 1;
#endif /* i786 */
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
{ LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
- for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(strings); i++) {
struct lb_string *rec;
size_t len;
rec = (struct lb_string *)lb_new_record(header);
printk_debug("setup_remote_node: %02x", node);
/* copy the default resource map from node 0 */
- for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
u32 value;
u16 reg;
reg = pci_reg[i];
revision = mctGetLogicalCPUID(0xFF);
platform = get_platform_type();
- for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
if ((fam10_msr_default[i].revision & revision) &&
(fam10_msr_default[i].platform & platform)) {
msr = rdmsr(fam10_msr_default[i].msr);
AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */
- for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
if ((fam10_pci_default[i].revision & revision) &&
(fam10_pci_default[i].platform & platform)) {
val = pci_read_config32(NODE_PCI(node,
}
}
- for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
if ((fam10_htphy_default[i].revision & revision) &&
(fam10_htphy_default[i].platform & platform)) {
/* HT Phy settings either apply to both sublinks or have
// int i;
int idx;
#if 0
- for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
unsigned char rambits;
int i, idx;
- for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
aty_st_le32(0xEC, 0x00000000, info);
aty_st_le32(0xFC, 0x00000000, info);
- for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
+ for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
}
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
type = chip_id & CFG_CHIP_TYPE;
rev = (chip_id & CFG_CHIP_REV)>>24;
- for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++)
+ for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
if (type == aty_chips[j].chip_type &&
(rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
chipname = aty_chips[j].name;
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 0
/* Check the first 1M */
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
+#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
get_bus_conf_done = 1;
- hc_possible_num = sizeof(pci1234) / sizeof(pci1234[0]);
+ hc_possible_num = ARRAY_SIZE(pci1234);
get_sblk_pci1234();
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
+#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
return; /* do it only once */
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values) / sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
m = sysconf.mb;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <cpu/amd/amdfam10_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
m->bus_type[i] = 0;
}
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#endif
enable_smbus();
#if 0
- dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ dump_spd_registers(ARRAY_SIZE(cpu), cpu);
#endif
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 0
dump_pci_devices();
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
int i;
if (device == DIMM0){
- for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
+ for (i=0; i < (ARRAY_SIZE(spd_table)); i++){
if (spd_table[i].address == address){
return spd_table[i].data;
}
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
/*
* Global variables for MB layouts and these will be shared by irqtable,
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
/* dump_spd_registers(&memctrl[0]); */
/* sdram_initialize() runs out of registers. */
- /* sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); */
+ /* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */
sdram_set_registers(memctrl);
sdram_set_spd_registers(memctrl);
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
// dump_ipmi_registers();
mainboard_set_e7520_leds();
// memreset_setup();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
#endif
#endif
#include <arch/hlt.h>
//#include "option_table.h"
+#include <stdlib.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
memreset_setup();
- sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}
#if 0
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#endif
};
int i;
- for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/io.h>
+#include <stdlib.h>
static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)
{
{ 0x13, 0x77}
};
-#define ARRAYSIZE(x) sizeof x/sizeof *x
-
/*
* Called from superio.c
*/
void init_ec(uint16_t base)
{
int i;
- for (i=0; i<ARRAYSIZE(sequence); i++) {
+ for (i=0; i<ARRAY_SIZE(sequence); i++) {
write_index(base, sequence[i].index, sequence[i].value);
}
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#endif
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 0
dump_pci_devices();
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#endif
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 0
dump_pci_devices();
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
power_down_reset_check();
// dump_ipmi_registers();
mainboard_set_e7520_leds();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
ich5_watchdog_on();
#if 0
dump_pci_devices();
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
// dump_smbus_registers();
// memreset_setup(); No-op for this chipset
- sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}
// NOTE: ROMCC dies with an internal compiler error
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
m = sysconf.mb;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#endif
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 0
dump_pci_devices();
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#endif
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 1
dump_pci_devices();
#endif
};
int i;
- for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
console_init();
report_bist_failure(bist);
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
/* Global variables for MB layouts and these will be shared by irqtable,
* mptable and acpi_tables.
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
- sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
// busnum is default.
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
- int max = sizeof(register_values) / sizeof(register_values[0]);
+ int max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
m = sysconf.mb;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t));
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
dump_spd_registers(&cpu[0]);
#endif
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 0
dump_pci_devices();
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t));
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
get_bus_conf_done = 1;
- hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
+ hc_possible_num = ARRAY_SIZE(pci1234);
get_sblk_pci1234();
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
}
#endif
disable_watchdogs();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 1
dump_pci_device(PCI_DEV(0, 0x00, 0));
// dump_bar14(PCI_DEV(0, 0x00, 0));
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
// dump_ipmi_registers();
// mainboard_set_e7520_leds();
// memreset_setup();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
// dump_ipmi_registers();
// mainboard_set_e7520_leds();
// memreset_setup();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
// dump_ipmi_registers();
// mainboard_set_e7520_leds();
// memreset_setup();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
// dump_ipmi_registers();
mainboard_set_e7520_leds();
// memreset_setup();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 1
dump_pci_devices();
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
// dump_ipmi_registers();
mainboard_set_e7520_leds();
// memreset_setup();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
report_bist_failure(bist);
enable_smbus();
/* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
/* ram_check(0, 640 * 1024); */
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#endif
memreset_setup();
- sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
+ sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}
#if 0
else {
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#endif
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t));
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <cpu/amd/amdfam10_sysconf.h>
+#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t));
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
}
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
enable_smbus();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#endif
};
int i;
- for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
/*
this is way more generic than we need.
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
*/
sdram_set_registers((const struct mem_controller *) 0);
sdram_set_spd_registers((const struct mem_controller *) 0);
#endif
};
int i;
- for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
};
u32 max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
+#include <stdlib.h>
#include "arch/romcc_io.h"
#include "amdk8.h"
print_spew("setup_remote_node: ");
/* copy the default resource map from node 0 */
- for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
+ for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
uint32_t value;
uint8_t reg;
reg = pci_reg[i];
};
#endif
- setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0]));
+ setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1));
setup_temp_row(0,2);
verify_connection(7);
3,0,1,1,
};
#endif
- setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0]));
+ setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
/* ready to enable RT for Node 3 */
rename_temp_node(3);
2,1,0,1,
};
#endif
- setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0]));
+ setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
#if 0
/*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
#endif
};
- setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0]));
+ setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte,byte+2);
#endif
};
- setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0]));
+ setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2));
rename_temp_node(4);
enable_routing(4);
#endif
};
- setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0]));
+ setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));
/* ready to enable RT for 5 */
rename_temp_node(5);
#endif
};
- setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0]));
+ setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
#if 0
/* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
#endif
};
- setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0]));
+ setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
for(byte=0; byte<6; byte+=2) {
setup_temp_row(byte,byte+2);
#endif
};
- setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0]));
+ setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2));
#if CROSS_BAR_47_56
//init 5, 6 here
#endif
};
- setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0]));
+ setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
#if CROSS_BAR_47_56
/* for 47, 56, 57, 75, 46, 64 we need to substract another link to
7, 3, 6,
};
- opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0]));
+ opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
static const u8 conn8_5[] = {
2, 7, 0,
3, 6, 1,
};
- opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0]));
+ opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
#endif
1,3,
2,3,
};
- needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
+ needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
}
#endif
4, 5,
#endif
};
- needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
+ needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
}
#endif
5, 7,
6, 7,
};
- needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
+ needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
}
#endif
#include <cpu/x86/mem.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
+#include <stdlib.h>
#include "raminit.h"
#include "amdk8.h"
print_spew("setting up CPU");
print_spew_hex8(ctrl->node_id);
print_spew(" northbridge registers\r\n");
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
}
device0 = ctrl->channel0[i];
device1 = ctrl->channel1[i];
- for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
+ for(j = 0; j < ARRAY_SIZE(addresses); j++) {
unsigned addr;
addr = addresses[j];
value0 = spd_read_byte(device0, addr);
#include <cpu/x86/mtrr.h>
#include <cpu/x86/tsc.h>
+#include <stdlib.h>
#include "raminit.h"
#include "amdk8_f.h"
#include "spd_ddr2.h"
print_spew("setting up CPU");
print_spew_hex8(ctrl->node_id);
print_spew(" northbridge registers\r\n");
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
for (i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
}
device0 = ctrl->channel0[i];
device1 = ctrl->channel1[i];
- for (j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
+ for (j = 0; j < ARRAY_SIZE(addresses); j++) {
unsigned addr;
addr = addresses[j];
value0 = spd_read_byte(device0, addr);
#include <string.h>
#include <setjmp.h>
#include <device/pci_def.h>
+#include <stdlib.h>
#include "amdk8.h"
jmp_buf end_buf;
};
console_init();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
{ FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */
};
-#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
uint32_t FlashPort[] = {
MDD_LBAR_FLSH0,
#include <assert.h>
#include <spd.h>
#include <sdram_mode.h>
+#include <stdlib.h>
#include "e7501.h"
// Uncomment this to enable run-time checking of DIMM parameters
static void ram_set_d0f0_regs(const struct mem_controller *ctrl)
{
int i;
- int num_values = sizeof(constant_register_values)/sizeof(constant_register_values[0]);
+ int num_values = ARRAY_SIZE(constant_register_values);
ASSERT((num_values % 3) == 0); // Bad table?
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <stdlib.h>
#include "raminit.h"
#include "e7520.h"
int i;
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
#include <string.h>
#include <setjmp.h>
#include <device/pci_def.h>
+#include <stdlib.h>
#include "e7520.h"
jmp_buf end_buf;
};
console_init();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <stdlib.h>
#include "raminit.h"
#include "e7525.h"
int i;
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
#include <string.h>
#include <setjmp.h>
#include <device/pci_def.h>
+#include <stdlib.h>
#include "e7525.h"
jmp_buf end_buf;
};
console_init();
memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ sdram_initialize(ARRAY_SIZE(cpu), cpu);
}
#endif
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <stdlib.h>
#include "raminit.h"
#include "i3100.h"
int i;
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
for(i = 0; i < max; i += 3) {
device_t dev;
u32 where;
#include <spd.h>
#include <sdram_mode.h>
#include <delay.h>
+#include <stdlib.h>
#include "i440bx.h"
/*-----------------------------------------------------------------------------
PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
DUMPNORTH();
- max = sizeof(register_values) / sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
/* Set registers as specified in the register_values[] array. */
for (i = 0; i < max; i += 3) {
#endif
int i;
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
for(i = 0; i < max; i += 3) {
uint32_t reg;
#if DEBUG_RAM_CONFIG >=2
unsigned char rambits;
int i, idx;
- for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
unsigned char rambits;
int i, idx;
- for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "amd8111.h"
#define NMI_OFF 0
ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid);
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
#include <cpu/x86/msr.h>
#include <cpu/amd/vr.h>
#include <cpu/amd/geode_post_code.h>
+#include <stdlib.h>
#include "chip.h"
#include "cs5536.h"
{FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */
};
-#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
uint32_t FlashPort[] = {
MDD_LBAR_FLSH0,
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "sb600.h"
#include "sb600_smbus.c"
l = (unsigned long *)ioapic_base;
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
#endif
};
- setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]));
+ setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));
}
#endif
};
- setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]));
+ setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));
}
- setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0]));
+ setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf));
setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf,
- sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+ ARRAY_SIZE(ctrl_devport_conf),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_b,
- sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
+ ARRAY_SIZE(ctrl_devport_conf_b),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
}
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf_clear,
- sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+ ARRAY_SIZE(ctrl_devport_conf_clear),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_clear_b,
- sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
+ ARRAY_SIZE(ctrl_devport_conf_clear_b),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
for(j=0; j<ck804_num; j++) {
if(busn[j] == 0) {
- setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
+ setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master),
PCI_DEV(busn[0],0,0), io_base[0]);
continue;
}
- setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
+ setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),
PCI_DEV(busn[j],0,0), io_base[j]);
}
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "ck804.h"
#define CK804_CHIP_REV 2
l = (unsigned long *) ioapic_base;
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
int j;
for(j = 0; j < mcp55_num; j++ ) {
setup_resource_map_offset(ctrl_devport_conf,
- sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+ ARRAY_SIZE(ctrl_devport_conf),
PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
}
}
int j;
for(j = 0; j < mcp55_num; j++ ) {
setup_resource_map_offset(ctrl_devport_conf_clear,
- sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+ ARRAY_SIZE(ctrl_devport_conf_clear),
PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
}
for(j=0; j<mcp55_num; j++) {
mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
- setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
+ setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
for(i=0; i<3; i++) { // three SATA
- setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
+ setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1),
PCI_DEV(busn[j], devn[j], i), io_base[j]);
}
if(busn[j] == 0) {
- setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
+ setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
if( (busn[j] == 0) && (mcp55_num>1) ) {
- setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
+ setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
- setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
+ setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "mcp55.h"
#define NMI_OFF 0
l = (unsigned long *) ioapic_base;
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "sis966.h"
#include <pc80/keyboard.h>
l = (unsigned long *) ioapic_base;
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
{
int i;
- for (i = 0; i < sizeof(fsys_table)/sizeof(fsys_table[0]); i++) {
+ for (i = 0; i < ARRAY_SIZE(fsys_table); i++) {
if (fsys_table[i].mount_func()) {
fsys = &fsys_table[i];
printk_info("Mounted %s\n", fsys->name);
#include <device/device.h>
#include <device/pnp.h>
#include <uart8250.h>
+#include <stdlib.h>
#include "chip.h"
#include "it8661f.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8661f_ops = {
#include <device/pnp.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "it8671f.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8671f_ops = {
#include <device/pnp.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "it8673f.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8673f_ops = {
#include <device/device.h>
#include <device/pnp.h>
#include <uart8250.h>
+#include <stdlib.h>
#include "chip.h"
#include "it8705f.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8705f_ops = {
#include <uart8250.h>
#include <pc80/keyboard.h>
#include <arch/io.h>
+#include <stdlib.h>
#include "chip.h"
#include "it8712f.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8712f_ops = {
#include <uart8250.h>
#include <pc80/keyboard.h>
#include <arch/io.h>
+#include <stdlib.h>
#include "chip.h"
#include "it8716f.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8716f_ops = {
#include <device/pnp.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "it8718f.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8718f_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc8374.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc8374_ops = {
#include <device/pnp.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc87309.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87309_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc87351.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87351_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc87360.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87360_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc87366.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87366_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc87417.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87417_ops = {
#include <console/console.h>
#include <string.h>
#include <bitops.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc87427.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87427_ops = {
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc97307.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc97307_ops = {
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
+#include <stdlib.h>
#include "chip.h"
#include "pc97317.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc97317_ops = {
#include <device/pnp.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "fdc37m60x.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_fdc37m60x_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "lpc47b272.h"
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
+ ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
}
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "lpc47b397.h"
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_lpc47b397_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "lpc47m10x.h"
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
+ ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
}
#include <bitops.h>
#include <uart8250.h>
#include <assert.h>
+#include <stdlib.h>
#include "chip.h"
#include "lpc47n217.h"
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
+ ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
}
#include <device/device.h>
#include <device/pnp.h>
#include <uart8250.h>
+#include <stdlib.h>
#include "vt1211.h"
#include "chip.h"
printk_debug("vt1211 enabling PNP devices.\n");
pnp_enable_devices(dev,
&ops,
- sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]),
+ ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
}
#include <uart8250.h>
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
+#include <stdlib.h>
#include "chip.h"
#include "w83627ehg.h"
0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */
};
- for(i = 0; i < sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i += 3) {
+ for(i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
reg = hwm_reg_values[i];
value = pnp_read_index(base, reg);
value &= 0xff & (~(hwm_reg_values[i + 1]));
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_winbond_w83627ehg_ops = {
#include <uart8250.h>
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
+#include <stdlib.h>
#include "chip.h"
#include "w83627hf.h"
};
- for(i = 0; i< sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i+=3 ) {
+ for(i = 0; i< ARRAY_SIZE(hwm_reg_values); i+=3 ) {
reg = hwm_reg_values[i];
value = pnp_read_index(base, reg);
value &= 0xff & hwm_reg_values[i+1];
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_winbond_w83627hf_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "w83627thf.h"
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_winbond_w83627thf_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "w83977f.h"
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_winbond_w83977f_ops = {
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <stdlib.h>
#include "chip.h"
#include "w83977tf.h"
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_winbond_w83977tf_ops = {
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