src/northbridge/ibm/cpc710/cpc710_pci.c

   1 #include <stdint.h>
   2 #include <arch/io.h>
   3 #include <arch/pciconf.h>
   4 #include <delay.h>
   5 #include "cpc710.h"
   6 #include "cpc710_pci.h"
   7
   8 extern void setCPC710(uint32_t, uint32_t);
   9
  10 void
  11 setCPC710_PCI32(uint32_t addr, uint32_t data)
  12 {
  13         out_be32((unsigned *)(CPC710_PCI32_CONFIG + addr), data);
  14 }
  15
  16 #if 0
  17 void
  18 setCPC710_PCI64(uint32_t addr, uint32_t data)
  19 {
  20         out_be32((unsigned *)(CPC710_PCI64_CONFIG + addr), data);
  21 }
  22 #endif
  23
  24 void
  25 cpc710_pci_init(void)
  26 {
  27         /* Enable PCI32 */
  28         setCPC710(CPC710_CPC0_PCICNFR, 0x80000002); /* activate PCI32 config */
  29         setCPC710(CPC710_CPC0_PCIBAR,  CPC710_PCI32_CONFIG); /* PCI32 base address */
  30         setCPC710(CPC710_CPC0_PCIENB,  0x80000000); /* enable addr space */
  31         setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
  32
  33         /* Reset PCI Status register */
  34         pci_ppc_write_config16(0, 0, 0x06, 0xffff);
  35
  36         /* Configure bus number */
  37         pci_ppc_write_config16(0, 0, 0x40, 0);
  38
  39         /* Set PCI configuration registers */
  40         setCPC710_PCI32(CPC710_PCIL0_PCIDG,  0x40000000);
  41         setCPC710_PCI32(CPC710_PCIL0_PIBAR,  0x00000000);
  42         setCPC710_PCI32(CPC710_PCIL0_PMBAR,  0x00000000);
  43         setCPC710_PCI32(CPC710_PCIL0_PR,     0xa000c000);
  44         setCPC710_PCI32(CPC710_PCIL0_ACR,    0xfc000000);
  45         setCPC710_PCI32(CPC710_PCIL0_MSIZE,  CPC710_PCI32_MEM_SIZE);
  46         setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE);
  47         setCPC710_PCI32(CPC710_PCIL0_SMBAR,  CPC710_PCI32_MEM_BASE);
  48         setCPC710_PCI32(CPC710_PCIL0_SIBAR,  CPC710_PCI32CONFIG_IO_BASE);
  49         setCPC710_PCI32(CPC710_PCIL0_CTLRW,  0x00000000);
  50         setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080);
  51         setCPC710_PCI32(CPC710_PCIL0_BARPS,  0x00000000);
  52         setCPC710_PCI32(CPC710_PCIL0_PSBAR,  0x00000080);
  53         setCPC710_PCI32(CPC710_PCIL0_BPMDLK, 0x00000000);
  54         setCPC710_PCI32(CPC710_PCIL0_TPMDLK, 0x00000000);
  55         setCPC710_PCI32(CPC710_PCIL0_BIODLK, 0x00000000);
  56         setCPC710_PCI32(CPC710_PCIL0_TIODLK, 0x00000000);
  57
  58         /* Enable address space */
  59         pci_ppc_write_config16(0, 0, 0x04, 0xfda7);
  60
  61         setCPC710_PCI32(CPC710_PCIL0_CRR,    0xfc000000);
  62
  63         /*
  64          * wait for PCI to reset
  65          */
  66         udelay(250);
  67
  68 #if 0
  69         /* Enable PCI64 */
  70         setCPC710(CPC710_CPC0_PCICNFR, 0x80000003); /* activate PCI64 config */
  71         setCPC710(CPC710_CPC0_PCIBAR,  CPC710_PCI64_CONFIG); /* PCI64 base address */
  72         setCPC710(CPC710_CPC0_PCIENB,  0x80000000); /* enable addr space */
  73         setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
  74
  75         /* Reset PCI Status register */
  76         setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x06000080);
  77         setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0xffff);
  78
  79         /* Reset G_INT[A-D] bits in INT_RESET */
  80         setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x68000080);
  81         setCPC710_PCI64(CPC710_PCIL0_CFGDATA, 0x0f000000);
  82
  83         /* Configure bus number BUSNO=1, SUBNO=1 */
  84         setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x40000080);
  85         setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0x0101);
  86
  87         /* Set PCI configuration registers */
  88         setCPC710_PCI64(CPC710_PCIL0_PSEA,   0x00000000);
  89         setCPC710_PCI64(CPC710_PCIL0_PCIDG,  0xc0000000);
  90         setCPC710_PCI64(CPC710_PCIL0_PIBAR,  0x00000000);
  91         setCPC710_PCI64(CPC710_PCIL0_PMBAR,  0x00000000);
  92         setCPC710_PCI64(CPC710_PCIL0_PR,     0x80008000);
  93         setCPC710_PCI64(CPC710_PCIL0_ACR,    0xff000000);
  94         setCPC710_PCI64(CPC710_PCIL0_MSIZE,  CPC710_PCI64_MEM_SIZE);
  95         setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE);
  96         setCPC710_PCI64(CPC710_PCIL0_SMBAR,  CPC710_PCI64_MEM_BASE);
  97         setCPC710_PCI64(CPC710_PCIL0_SIBAR,  CPC710_PCI64CONFIG_IO_BASE);
  98         setCPC710_PCI64(CPC710_PCIL0_CTLRW,  0x02000000);
  99         setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080);
 100
 101         /* Config PSBAR for PCI64 */
 102         setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x10000080);
 103         setCPC710_PCI64(CPC710_PCIL0_CFGDATA, 0x00000080);
 104
 105         setCPC710_PCI64(CPC710_PCIL0_BARPS,   0x00000000);
 106         setCPC710_PCI64(CPC710_PCIL0_INTSET,  0x00000000);
 107
 108         /* Enable address space */
 109         setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x04000180);
 110         setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0xfda7);
 111
 112         setCPC710_PCI64(CPC710_PCIL0_CRR,    0xfc000000);
 113
 114         /*
 115          * wait for PCI to reset
 116          */
 117         udelay(250);
 118 #endif
 119 }