src/northbridge/amd/amdk8/misc_control.c

   1 /* Turn off machine check triggers when reading
   2  * pci space where there are no devices.
   3  * This is necessary when scaning the bus for
   4  * devices which is done by the kernel
   5  *
   6  * written in 2003 by Eric Biederman
   7  *
   8  *  - Athlon64 workarounds by Stefan Reinauer
   9  *  - "reset once" logic by Yinghai Lu
  10  */
  11
  12 #include <console/console.h>
  13 #include <device/device.h>
  14 #include <device/pci.h>
  15 #include <device/pci_ids.h>
  16 #include <device/pci_ops.h>
  17 #include <part/hard_reset.h>
  18 #include <pc80/mc146818rtc.h>
  19 #include <bitops.h>
  20 #include <cpu/amd/model_fxx_rev.h>
  21
  22 #include "amdk8.h"
  23
  24 /**
  25  * @brief Read resources for AGP aperture
  26  *
  27  * @param
  28  *
  29  * There is only one AGP aperture resource needed. The resoruce is added to
  30  * the northbridge of BSP.
  31  *
  32  * The same trick can be used to augment legacy VGA resources which can
  33  * be detect by generic pci reousrce allocator for VGA devices.
  34  * BAD: it is more tricky than I think, the resource allocation code is
  35  * implemented in a way to NOT DOING legacy VGA resource allcation on
  36  * purpose :-(.
  37  */
  38 static void mcf3_read_resources(device_t dev)
  39 {
  40         struct resource *resource;
  41         unsigned char iommu;
  42         /* Read the generic PCI resources */
  43         pci_dev_read_resources(dev);
  44
  45         /* If we are not the first processor don't allocate the gart apeture */
  46         if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
  47                 return;
  48         }
  49
  50         iommu = 1;
  51         get_option(&iommu, "iommu");
  52
  53         if (iommu) {
  54                 /* Add a Gart apeture resource */
  55                 resource = new_resource(dev, 0x94);
  56                 resource->size = iommu?AGP_APERTURE_SIZE:1;
  57                 resource->align = log2(resource->size);
  58                 resource->gran  = log2(resource->size);
  59                 resource->limit = 0xffffffff; /* 4G */
  60                 resource->flags = IORESOURCE_MEM;
  61         }
  62 }
  63
  64 static void set_agp_aperture(device_t dev)
  65 {
  66         struct resource *resource;
  67
  68         resource = probe_resource(dev, 0x94);
  69         if (resource) {
  70                 device_t pdev;
  71                 uint32_t gart_base, gart_acr;
  72
  73                 /* Remember this resource has been stored */
  74                 resource->flags |= IORESOURCE_STORED;
  75
  76                 /* Find the size of the GART aperture */
  77                 gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
  78
  79                 /* Get the base address */
  80                 gart_base = ((resource->base) >> 25) & 0x00007fff;
  81
  82                 /* Update the other northbriges */
  83                 pdev = 0;
  84                 while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
  85                         /* Store the GART size but don't enable it */
  86                         pci_write_config32(pdev, 0x90, gart_acr);
  87
  88                         /* Store the GART base address */
  89                         pci_write_config32(pdev, 0x94, gart_base);
  90
  91                         /* Don't set the GART Table base address */
  92                         pci_write_config32(pdev, 0x98, 0);
  93
  94                         /* Report the resource has been stored... */
  95                         report_resource_stored(pdev, resource, " <gart>");
  96                 }
  97         }
  98 }
  99
 100 static void mcf3_set_resources(device_t dev)
 101 {
 102         /* Set the gart apeture */
 103         set_agp_aperture(dev);
 104
 105         /* Set the generic PCI resources */
 106         pci_dev_set_resources(dev);
 107 }
 108
 109 static void misc_control_init(struct device *dev)
 110 {
 111         uint32_t cmd, cmd_ref;
 112         int needs_reset;
 113         struct device *f0_dev, *f2_dev;
 114
 115         printk_debug("NB: Function 3 Misc Control.. ");
 116         needs_reset = 0;
 117
 118         /* Disable Machine checks from Invalid Locations.
 119          * This is needed for PC backwards compatibility.
 120          */
 121         cmd = pci_read_config32(dev, 0x44);
 122         cmd |= (1<<6) | (1<<25);
 123         pci_write_config32(dev, 0x44, cmd );
 124 #if K8_REV_F_SUPPORT == 0
 125         if (is_cpu_pre_c0()) {
 126
 127                 /* Errata 58
 128                  * Disable CPU low power states C2, C1 and throttling
 129                  */
 130                 cmd = pci_read_config32(dev, 0x80);
 131                 cmd &= ~(1<<0);
 132                 pci_write_config32(dev, 0x80, cmd );
 133                 cmd = pci_read_config32(dev, 0x84);
 134                 cmd &= ~(1<<24);
 135                 cmd &= ~(1<<8);
 136                 pci_write_config32(dev, 0x84, cmd );
 137
 138                 /* Errata 66
 139                  * Limit the number of downstream posted requests to 1
 140                  */
 141                 cmd = pci_read_config32(dev, 0x70);
 142                 if ((cmd & (3 << 0)) != 2) {
 143                         cmd &= ~(3<<0);
 144                         cmd |= (2<<0);
 145                         pci_write_config32(dev, 0x70, cmd );
 146                         needs_reset = 1;
 147                 }
 148                 cmd = pci_read_config32(dev, 0x7c);
 149                 if ((cmd & (3 << 4)) != 0) {
 150                         cmd &= ~(3<<4);
 151                         cmd |= (0<<4);
 152                         pci_write_config32(dev, 0x7c, cmd );
 153                         needs_reset = 1;
 154                 }
 155                 /* Clock Power/Timing Low */
 156                 cmd = pci_read_config32(dev, 0xd4);
 157                 if (cmd != 0x000D0001) {
 158                         cmd = 0x000D0001;
 159                         pci_write_config32(dev, 0xd4, cmd);
 160                         needs_reset = 1; /* Needed? */
 161                 }
 162         }
 163         else if(is_cpu_pre_d0()) {
 164                 uint32_t dcl;
 165                 f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
 166                 /* Errata 98
 167                  * Set Clk Ramp Hystersis to 7
 168                  * Clock Power/Timing Low
 169                  */
 170                 cmd_ref = 0x04e20707; /* Registered */
 171                 dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
 172                 if (dcl & DCL_UnBuffDimm) {
 173                         cmd_ref = 0x000D0701; /* Unbuffered */
 174                 }
 175                 cmd = pci_read_config32(dev, 0xd4);
 176                 if(cmd != cmd_ref) {
 177                         pci_write_config32(dev, 0xd4, cmd_ref );
 178                         needs_reset = 1; /* Needed? */
 179                 }
 180         }
 181 #endif
 182         /* Optimize the Link read pointers */
 183         f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
 184         if (f0_dev) {
 185                 int link;
 186                 cmd_ref = cmd = pci_read_config32(dev, 0xdc);
 187                 for(link = 0; link < 3; link++) {
 188                         uint32_t link_type;
 189                         unsigned reg;
 190                         /* This works on an Athlon64 because unimplemented links return 0 */
 191                         reg = 0x98 + (link * 0x20);
 192                         link_type = pci_read_config32(f0_dev, reg);
 193                         /* Only handle coherent link here please */
 194                         if ((link_type & (LinkConnected|InitComplete|NonCoherent))
 195                                 == (LinkConnected|InitComplete))
 196                         {
 197                                 cmd &= ~(0xff << (link *8));
 198                                 /* FIXME this assumes the device on the other side is an AMD device */
 199                                 cmd |= 0x25 << (link *8);
 200                         }
 201                 }
 202                 if (cmd != cmd_ref) {
 203                         pci_write_config32(dev, 0xdc, cmd);
 204                         needs_reset = 1;
 205                 }
 206         }
 207         else {
 208                 printk_err("Missing f0 device!\n");
 209         }
 210         if (needs_reset) {
 211                 printk_debug("resetting cpu\n");
 212                 hard_reset();
 213         }
 214         printk_debug("done.\n");
 215 }
 216
 217
 218 static struct device_operations mcf3_ops  = {
 219         .read_resources   = mcf3_read_resources,
 220         .set_resources    = mcf3_set_resources,
 221         .enable_resources = pci_dev_enable_resources,
 222         .init             = misc_control_init,
 223         .scan_bus         = 0,
 224         .ops_pci          = 0,
 225 };
 226
 227 static const struct pci_driver mcf3_driver __pci_driver = {
 228         .ops    = &mcf3_ops,
 229         .vendor = PCI_VENDOR_ID_AMD,
 230         .device = 0x1103,
 231 };