#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"
uses AGP_APERTURE_SIZE
uses HAVE_ACPI_TABLES
uses HAVE_HIGH_TABLES
+uses K8_REV_F_SUPPORT
default AGP_APERTURE_SIZE=0x4000000
default HAVE_HIGH_TABLES=1
driver northbridge.o
driver misc_control.o
+if K8_REV_F_SUPPORT
+
+makerule raminit_test
+ depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"
+ depends "$(TOP)/src/northbridge/amd/amdk8/raminit_f.c"
+ action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
+end
+
+else
+
makerule raminit_test
depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"
depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c"
action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
end
+end
+
+
if HAVE_ACPI_TABLES
object amdk8_acpi.o
end
#if K8_REV_F_SUPPORT == 1
#include "amdk8_f.h"
-
#else
-/* Definitions of various K8 registers */
-/* Function 0 */
-#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
-#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
-#define HTTC_MED_PRI_BYP_CNT_MASK 3
-#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
-#define HTTC_HI_PRI_BYP_CNT_MASK 3
-
-
-/* Function 1 */
-#define PCI_IO_BASE0 0xc0
-#define PCI_IO_BASE1 0xc8
-#define PCI_IO_BASE2 0xd0
-#define PCI_IO_BASE3 0xd8
-#define PCI_IO_BASE_VGA_EN (1 << 4)
-#define PCI_IO_BASE_NO_ISA (1 << 5)
-
-
-/* Function 2 */
-#define DRAM_CSBASE 0x40
-#define DRAM_CSMASK 0x60
-#define DRAM_BANK_ADDR_MAP 0x80
-
-#define DRAM_TIMING_LOW 0x88
-#define DTL_TCL_SHIFT 0
-#define DTL_TCL_MASK 0x7
-#define DTL_CL_2 1
-#define DTL_CL_3 2
-#define DTL_CL_2_5 5
-#define DTL_TRC_SHIFT 4
-#define DTL_TRC_MASK 0xf
-#define DTL_TRC_BASE 7
-#define DTL_TRC_MIN 7
-#define DTL_TRC_MAX 22
-#define DTL_TRFC_SHIFT 8
-#define DTL_TRFC_MASK 0xf
-#define DTL_TRFC_BASE 9
-#define DTL_TRFC_MIN 9
-#define DTL_TRFC_MAX 24
-#define DTL_TRCD_SHIFT 12
-#define DTL_TRCD_MASK 0x7
-#define DTL_TRCD_BASE 0
-#define DTL_TRCD_MIN 2
-#define DTL_TRCD_MAX 6
-#define DTL_TRRD_SHIFT 16
-#define DTL_TRRD_MASK 0x7
-#define DTL_TRRD_BASE 0
-#define DTL_TRRD_MIN 2
-#define DTL_TRRD_MAX 4
-#define DTL_TRAS_SHIFT 20
-#define DTL_TRAS_MASK 0xf
-#define DTL_TRAS_BASE 0
-#define DTL_TRAS_MIN 5
-#define DTL_TRAS_MAX 15
-#define DTL_TRP_SHIFT 24
-#define DTL_TRP_MASK 0x7
-#define DTL_TRP_BASE 0
-#define DTL_TRP_MIN 2
-#define DTL_TRP_MAX 6
-#define DTL_TWR_SHIFT 28
-#define DTL_TWR_MASK 0x1
-#define DTL_TWR_BASE 2
-#define DTL_TWR_MIN 2
-#define DTL_TWR_MAX 3
-
-#define DRAM_TIMING_HIGH 0x8c
-#define DTH_TWTR_SHIFT 0
-#define DTH_TWTR_MASK 0x1
-#define DTH_TWTR_BASE 1
-#define DTH_TWTR_MIN 1
-#define DTH_TWTR_MAX 2
-#define DTH_TRWT_SHIFT 4
-#define DTH_TRWT_MASK 0x7
-#define DTH_TRWT_BASE 1
-#define DTH_TRWT_MIN 1
-#define DTH_TRWT_MAX 6
-#define DTH_TREF_SHIFT 8
-#define DTH_TREF_MASK 0x1f
-#define DTH_TREF_100MHZ_4K 0x00
-#define DTH_TREF_133MHZ_4K 0x01
-#define DTH_TREF_166MHZ_4K 0x02
-#define DTH_TREF_200MHZ_4K 0x03
-#define DTH_TREF_100MHZ_8K 0x08
-#define DTH_TREF_133MHZ_8K 0x09
-#define DTH_TREF_166MHZ_8K 0x0A
-#define DTH_TREF_200MHZ_8K 0x0B
-#define DTH_TWCL_SHIFT 20
-#define DTH_TWCL_MASK 0x7
-#define DTH_TWCL_BASE 1
-#define DTH_TWCL_MIN 1
-#define DTH_TWCL_MAX 2
-
-#define DRAM_CONFIG_LOW 0x90
-#define DCL_DLL_Disable (1<<0)
-#define DCL_D_DRV (1<<1)
-#define DCL_QFC_EN (1<<2)
-#define DCL_DisDqsHys (1<<3)
-#define DCL_Burst2Opt (1<<5)
-#define DCL_DramInit (1<<8)
-#define DCL_DualDIMMen (1<<9)
-#define DCL_DramEnable (1<<10)
-#define DCL_MemClrStatus (1<<11)
-#define DCL_ESR (1<<12)
-#define DCL_SRS (1<<13)
-#define DCL_128BitEn (1<<16)
-#define DCL_DimmEccEn (1<<17)
-#define DCL_UnBufDimm (1<<18)
-#define DCL_32ByteEn (1<<19)
-#define DCL_x4DIMM_SHIFT 20
-#define DCL_DisInRcvrs (1<<24)
-#define DCL_BypMax_SHIFT 25
-#define DCL_En2T (1<<28)
-#define DCL_UpperCSMap (1<<29)
-
-#define DRAM_CONFIG_HIGH 0x94
-#define DCH_ASYNC_LAT_SHIFT 0
-#define DCH_ASYNC_LAT_MASK 0xf
-#define DCH_ASYNC_LAT_BASE 0
-#define DCH_ASYNC_LAT_MIN 0
-#define DCH_ASYNC_LAT_MAX 15
-#define DCH_RDPREAMBLE_SHIFT 8
-#define DCH_RDPREAMBLE_MASK 0xf
-#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
-#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
-#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
-#define DCH_IDLE_LIMIT_SHIFT 16
-#define DCH_IDLE_LIMIT_MASK 0x7
-#define DCH_IDLE_LIMIT_0 0
-#define DCH_IDLE_LIMIT_4 1
-#define DCH_IDLE_LIMIT_8 2
-#define DCH_IDLE_LIMIT_16 3
-#define DCH_IDLE_LIMIT_32 4
-#define DCH_IDLE_LIMIT_64 5
-#define DCH_IDLE_LIMIT_128 6
-#define DCH_IDLE_LIMIT_256 7
-#define DCH_DYN_IDLE_CTR_EN (1 << 19)
-#define DCH_MEMCLK_SHIFT 20
-#define DCH_MEMCLK_MASK 0x7
-#define DCH_MEMCLK_100MHZ 0
-#define DCH_MEMCLK_133MHZ 2
-#define DCH_MEMCLK_166MHZ 5
-#define DCH_MEMCLK_200MHZ 7
-#define DCH_MEMCLK_VALID (1 << 25)
-#define DCH_MEMCLK_EN0 (1 << 26)
-#define DCH_MEMCLK_EN1 (1 << 27)
-#define DCH_MEMCLK_EN2 (1 << 28)
-#define DCH_MEMCLK_EN3 (1 << 29)
-
-/* Function 3 */
-#define MCA_NB_CONFIG 0x44
-#define MNC_ECC_EN (1 << 22)
-#define MNC_CHIPKILL_EN (1 << 23)
-#define SCRUB_CONTROL 0x58
-#define SCRUB_NONE 0
-#define SCRUB_40ns 1
-#define SCRUB_80ns 2
-#define SCRUB_160ns 3
-#define SCRUB_320ns 4
-#define SCRUB_640ns 5
-#define SCRUB_1_28us 6
-#define SCRUB_2_56us 7
-#define SCRUB_5_12us 8
-#define SCRUB_10_2us 9
-#define SCRUB_20_5us 10
-#define SCRUB_41_0us 11
-#define SCRUB_81_9us 12
-#define SCRUB_163_8us 13
-#define SCRUB_327_7us 14
-#define SCRUB_655_4us 15
-#define SCRUB_1_31ms 16
-#define SCRUB_2_62ms 17
-#define SCRUB_5_24ms 18
-#define SCRUB_10_49ms 19
-#define SCRUB_20_97ms 20
-#define SCRUB_42ms 21
-#define SCRUB_84ms 22
-#define SC_DRAM_SCRUB_RATE_SHFIT 0
-#define SC_DRAM_SCRUB_RATE_MASK 0x1f
-#define SC_L2_SCRUB_RATE_SHIFT 8
-#define SC_L2_SCRUB_RATE_MASK 0x1f
-#define SC_L1D_SCRUB_RATE_SHIFT 16
-#define SC_L1D_SCRUB_RATE_MASK 0x1f
-#define SCRUB_ADDR_LOW 0x5C
-#define SCRUB_ADDR_HIGH 0x60
-#define NORTHBRIDGE_CAP 0xE8
-#define NBCAP_128Bit (1 << 0)
-#define NBCAP_MP (1 << 1)
-#define NBCAP_BIG_MP (1 << 2)
-#define NBCAP_ECC (1 << 3)
-#define NBCAP_CHIPKILL_ECC (1 << 4)
-#define NBCAP_MEMCLK_SHIFT 5
-#define NBCAP_MEMCLK_MASK 3
-#define NBCAP_MEMCLK_100MHZ 3
-#define NBCAP_MEMCLK_133MHZ 2
-#define NBCAP_MEMCLK_166MHZ 1
-#define NBCAP_MEMCLK_200MHZ 0
-#define NBCAP_MEMCTRL (1 << 8)
-
-
-#define LinkConnected (1 << 0)
-#define InitComplete (1 << 1)
-#define NonCoherent (1 << 2)
-#define ConnectionPending (1 << 4)
-
-#include "raminit.h"
-//struct definitions
-
-struct link_pair_st {
- device_t udev;
- uint32_t upos;
- uint32_t uoffs;
- device_t dev;
- uint32_t pos;
- uint32_t offs;
-
-} __attribute__((packed));
-
-struct sys_info {
- uint8_t ctrl_present[NODE_NUMS];
- struct mem_controller ctrl[NODE_NUMS];
-
- uint32_t nodes;
- struct link_pair_st link_pair[16];// enough? only in_conherent
- uint32_t link_pair_num;
- uint32_t ht_c_num;
- uint32_t sbdn;
- uint32_t sblk;
- uint32_t sbbusn;
-} __attribute__((packed));
-
+ #include "amdk8_pre_f.h"
#endif
#endif /* AMDK8_H */
#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
-
#include "raminit.h"
//struct definitions
--- /dev/null
+#ifndef AMDK8_PRE_F_H
+
+#define AMDK8_PRE_F_H
+
+/* Definitions of various K8 registers */
+/* Function 0 */
+#define HT_TRANSACTION_CONTROL 0x68
+#define HTTC_DIS_RD_B_P (1 << 0)
+#define HTTC_DIS_RD_DW_P (1 << 1)
+#define HTTC_DIS_WR_B_P (1 << 2)
+#define HTTC_DIS_WR_DW_P (1 << 3)
+#define HTTC_DIS_MTS (1 << 4)
+#define HTTC_CPU1_EN (1 << 5)
+#define HTTC_CPU_REQ_PASS_PW (1 << 6)
+#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
+#define HTTC_DIS_P_MEM_C (1 << 8)
+#define HTTC_DIS_RMT_MEM_C (1 << 9)
+#define HTTC_DIS_FILL_P (1 << 10)
+#define HTTC_RSP_PASS_PW (1 << 11)
+#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
+#define HTTC_BUF_REL_PRI_SHIFT 13
+#define HTTC_BUF_REL_PRI_MASK 3
+#define HTTC_BUF_REL_PRI_64 0
+#define HTTC_BUF_REL_PRI_16 1
+#define HTTC_BUF_REL_PRI_8 2
+#define HTTC_BUF_REL_PRI_2 3
+#define HTTC_LIMIT_CLDT_CFG (1 << 15)
+#define HTTC_LINT_EN (1 << 16)
+#define HTTC_APIC_EXT_BRD_CST (1 << 17)
+#define HTTC_APIC_EXT_ID (1 << 18)
+#define HTTC_APIC_EXT_SPUR (1 << 19)
+#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
+#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define HTTC_DS_NP_REQ_LIMIT_MASK 3
+#define HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define HTTC_DS_NP_REQ_LIMIT_1 1
+#define HTTC_DS_NP_REQ_LIMIT_4 2
+#define HTTC_DS_NP_REQ_LIMIT_8 3
+#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
+#define HTTC_MED_PRI_BYP_CNT_MASK 3
+#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
+#define HTTC_HI_PRI_BYP_CNT_MASK 3
+
+
+/* Function 1 */
+#define PCI_IO_BASE0 0xc0
+#define PCI_IO_BASE1 0xc8
+#define PCI_IO_BASE2 0xd0
+#define PCI_IO_BASE3 0xd8
+#define PCI_IO_BASE_VGA_EN (1 << 4)
+#define PCI_IO_BASE_NO_ISA (1 << 5)
+
+
+/* Function 2 */
+#define DRAM_CSBASE 0x40
+#define DRAM_CSMASK 0x60
+#define DRAM_BANK_ADDR_MAP 0x80
+
+#define DRAM_TIMING_LOW 0x88
+#define DTL_TCL_SHIFT 0
+#define DTL_TCL_MASK 0x7
+#define DTL_CL_2 1
+#define DTL_CL_3 2
+#define DTL_CL_2_5 5
+#define DTL_TRC_SHIFT 4
+#define DTL_TRC_MASK 0xf
+#define DTL_TRC_BASE 7
+#define DTL_TRC_MIN 7
+#define DTL_TRC_MAX 22
+#define DTL_TRFC_SHIFT 8
+#define DTL_TRFC_MASK 0xf
+#define DTL_TRFC_BASE 9
+#define DTL_TRFC_MIN 9
+#define DTL_TRFC_MAX 24
+#define DTL_TRCD_SHIFT 12
+#define DTL_TRCD_MASK 0x7
+#define DTL_TRCD_BASE 0
+#define DTL_TRCD_MIN 2
+#define DTL_TRCD_MAX 6
+#define DTL_TRRD_SHIFT 16
+#define DTL_TRRD_MASK 0x7
+#define DTL_TRRD_BASE 0
+#define DTL_TRRD_MIN 2
+#define DTL_TRRD_MAX 4
+#define DTL_TRAS_SHIFT 20
+#define DTL_TRAS_MASK 0xf
+#define DTL_TRAS_BASE 0
+#define DTL_TRAS_MIN 5
+#define DTL_TRAS_MAX 15
+#define DTL_TRP_SHIFT 24
+#define DTL_TRP_MASK 0x7
+#define DTL_TRP_BASE 0
+#define DTL_TRP_MIN 2
+#define DTL_TRP_MAX 6
+#define DTL_TWR_SHIFT 28
+#define DTL_TWR_MASK 0x1
+#define DTL_TWR_BASE 2
+#define DTL_TWR_MIN 2
+#define DTL_TWR_MAX 3
+
+#define DRAM_TIMING_HIGH 0x8c
+#define DTH_TWTR_SHIFT 0
+#define DTH_TWTR_MASK 0x1
+#define DTH_TWTR_BASE 1
+#define DTH_TWTR_MIN 1
+#define DTH_TWTR_MAX 2
+#define DTH_TRWT_SHIFT 4
+#define DTH_TRWT_MASK 0x7
+#define DTH_TRWT_BASE 1
+#define DTH_TRWT_MIN 1
+#define DTH_TRWT_MAX 6
+#define DTH_TREF_SHIFT 8
+#define DTH_TREF_MASK 0x1f
+#define DTH_TREF_100MHZ_4K 0x00
+#define DTH_TREF_133MHZ_4K 0x01
+#define DTH_TREF_166MHZ_4K 0x02
+#define DTH_TREF_200MHZ_4K 0x03
+#define DTH_TREF_100MHZ_8K 0x08
+#define DTH_TREF_133MHZ_8K 0x09
+#define DTH_TREF_166MHZ_8K 0x0A
+#define DTH_TREF_200MHZ_8K 0x0B
+#define DTH_TWCL_SHIFT 20
+#define DTH_TWCL_MASK 0x7
+#define DTH_TWCL_BASE 1
+#define DTH_TWCL_MIN 1
+#define DTH_TWCL_MAX 2
+
+#define DRAM_CONFIG_LOW 0x90
+#define DCL_DLL_Disable (1<<0)
+#define DCL_D_DRV (1<<1)
+#define DCL_QFC_EN (1<<2)
+#define DCL_DisDqsHys (1<<3)
+#define DCL_Burst2Opt (1<<5)
+#define DCL_DramInit (1<<8)
+#define DCL_DualDIMMen (1<<9)
+#define DCL_DramEnable (1<<10)
+#define DCL_MemClrStatus (1<<11)
+#define DCL_ESR (1<<12)
+#define DCL_SRS (1<<13)
+#define DCL_128BitEn (1<<16)
+#define DCL_DimmEccEn (1<<17)
+#define DCL_UnBuffDimm (1<<18)
+#define DCL_32ByteEn (1<<19)
+#define DCL_x4DIMM_SHIFT 20
+#define DCL_DisInRcvrs (1<<24)
+#define DCL_BypMax_SHIFT 25
+#define DCL_En2T (1<<28)
+#define DCL_UpperCSMap (1<<29)
+
+#define DRAM_CONFIG_HIGH 0x94
+#define DCH_ASYNC_LAT_SHIFT 0
+#define DCH_ASYNC_LAT_MASK 0xf
+#define DCH_ASYNC_LAT_BASE 0
+#define DCH_ASYNC_LAT_MIN 0
+#define DCH_ASYNC_LAT_MAX 15
+#define DCH_RDPREAMBLE_SHIFT 8
+#define DCH_RDPREAMBLE_MASK 0xf
+#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
+#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
+#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
+#define DCH_IDLE_LIMIT_SHIFT 16
+#define DCH_IDLE_LIMIT_MASK 0x7
+#define DCH_IDLE_LIMIT_0 0
+#define DCH_IDLE_LIMIT_4 1
+#define DCH_IDLE_LIMIT_8 2
+#define DCH_IDLE_LIMIT_16 3
+#define DCH_IDLE_LIMIT_32 4
+#define DCH_IDLE_LIMIT_64 5
+#define DCH_IDLE_LIMIT_128 6
+#define DCH_IDLE_LIMIT_256 7
+#define DCH_DYN_IDLE_CTR_EN (1 << 19)
+#define DCH_MEMCLK_SHIFT 20
+#define DCH_MEMCLK_MASK 0x7
+#define DCH_MEMCLK_100MHZ 0
+#define DCH_MEMCLK_133MHZ 2
+#define DCH_MEMCLK_166MHZ 5
+#define DCH_MEMCLK_200MHZ 7
+#define DCH_MEMCLK_VALID (1 << 25)
+#define DCH_MEMCLK_EN0 (1 << 26)
+#define DCH_MEMCLK_EN1 (1 << 27)
+#define DCH_MEMCLK_EN2 (1 << 28)
+#define DCH_MEMCLK_EN3 (1 << 29)
+
+/* Function 3 */
+#define MCA_NB_CONFIG 0x44
+#define MNC_ECC_EN (1 << 22)
+#define MNC_CHIPKILL_EN (1 << 23)
+#define SCRUB_CONTROL 0x58
+#define SCRUB_NONE 0
+#define SCRUB_40ns 1
+#define SCRUB_80ns 2
+#define SCRUB_160ns 3
+#define SCRUB_320ns 4
+#define SCRUB_640ns 5
+#define SCRUB_1_28us 6
+#define SCRUB_2_56us 7
+#define SCRUB_5_12us 8
+#define SCRUB_10_2us 9
+#define SCRUB_20_5us 10
+#define SCRUB_41_0us 11
+#define SCRUB_81_9us 12
+#define SCRUB_163_8us 13
+#define SCRUB_327_7us 14
+#define SCRUB_655_4us 15
+#define SCRUB_1_31ms 16
+#define SCRUB_2_62ms 17
+#define SCRUB_5_24ms 18
+#define SCRUB_10_49ms 19
+#define SCRUB_20_97ms 20
+#define SCRUB_42ms 21
+#define SCRUB_84ms 22
+#define SC_DRAM_SCRUB_RATE_SHFIT 0
+#define SC_DRAM_SCRUB_RATE_MASK 0x1f
+#define SC_L2_SCRUB_RATE_SHIFT 8
+#define SC_L2_SCRUB_RATE_MASK 0x1f
+#define SC_L1D_SCRUB_RATE_SHIFT 16
+#define SC_L1D_SCRUB_RATE_MASK 0x1f
+#define SCRUB_ADDR_LOW 0x5C
+#define SCRUB_ADDR_HIGH 0x60
+#define NORTHBRIDGE_CAP 0xE8
+#define NBCAP_128Bit (1 << 0)
+#define NBCAP_MP (1 << 1)
+#define NBCAP_BIG_MP (1 << 2)
+#define NBCAP_ECC (1 << 3)
+#define NBCAP_CHIPKILL_ECC (1 << 4)
+#define NBCAP_MEMCLK_SHIFT 5
+#define NBCAP_MEMCLK_MASK 3
+#define NBCAP_MEMCLK_100MHZ 3
+#define NBCAP_MEMCLK_133MHZ 2
+#define NBCAP_MEMCLK_166MHZ 1
+#define NBCAP_MEMCLK_200MHZ 0
+#define NBCAP_MEMCTRL (1 << 8)
+
+
+#define LinkConnected (1 << 0)
+#define InitComplete (1 << 1)
+#define NonCoherent (1 << 2)
+#define ConnectionPending (1 << 4)
+
+#include "raminit.h"
+//struct definitions
+
+struct link_pair_st {
+ device_t udev;
+ uint32_t upos;
+ uint32_t uoffs;
+ device_t dev;
+ uint32_t pos;
+ uint32_t offs;
+
+} __attribute__((packed));
+
+struct sys_info {
+ uint8_t ctrl_present[NODE_NUMS];
+ struct mem_controller ctrl[NODE_NUMS];
+
+ uint32_t nodes;
+ struct link_pair_st link_pair[16];// enough? only in_conherent
+ uint32_t link_pair_num;
+ uint32_t ht_c_num;
+ uint32_t sbdn;
+ uint32_t sblk;
+ uint32_t sbbusn;
+} __attribute__((packed));
+
+#endif /* AMDK8_PRE_F_H */
*/
cmd_ref = 0x04e20707; /* Registered */
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
- if (dcl & DCL_UnBufDimm) {
+ if (dcl & DCL_UnBuffDimm) {
cmd_ref = 0x000D0701; /* Unbuffered */
}
cmd = pci_read_config32(dev, 0xd4);
2004.12 yhlu add D0 support
2005.02 yhlu add E0 memory hole support
*/
-#if K8_REV_F_SUPPORT == 1
- #include "raminit_f.c"
-#else
#include <cpu/x86/mem.h>
#include <cpu/x86/cache.h>
static void hard_reset(void);
#endif
-#if 1
static void setup_resource_map(const unsigned int *register_values, int max)
{
int i;
-// print_debug("setting up resource map....");
-#if 0
- print_debug("\r\n");
-#endif
- for(i = 0; i < max; i += 3) {
+// printk_debug("setting up resource map....");
+ for (i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
-#if 0
- #if CONFIG_USE_PRINTK_IN_CAR
- prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
- #else
- print_debug_hex32(register_values[i]);
- print_debug(" <-");
- print_debug_hex32(register_values[i+2]);
- print_debug("\r\n");
- #endif
-#endif
dev = register_values[i] & ~0xfff;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
-#if 0
- reg = pci_read_config32(register_values[i]);
- reg &= register_values[i+1];
- reg |= register_values[i+2] & ~register_values[i+1];
- pci_write_config32(register_values[i], reg);
-#endif
}
-// print_debug("done.\r\n");
+// printk_debug("done.\n");
}
-#endif
static int controller_present(const struct mem_controller *ctrl)
{
{
static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
+ /* Careful set limit registers before base registers which
+ contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
int i;
int max;
-#if 1
if (!controller_present(ctrl)) {
-// print_debug("No memory controller present\r\n");
+// printk_debug("No memory controller present\n");
return;
}
-#endif
- print_spew("setting up CPU");
- print_spew_hex8(ctrl->node_id);
- print_spew(" northbridge registers\r\n");
+ printk_spew("setting up CPU%02x northbridge registers\n", ctrl->node_id);
max = ARRAY_SIZE(register_values);
- for(i = 0; i < max; i += 3) {
+ for (i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
-#if 0
- #if CONFIG_USE_PRINTK_IN_CAR
- prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
- #else
- print_spew_hex32(register_values[i]);
- print_spew(" <-");
- print_spew_hex32(register_values[i+2]);
- print_spew("\r\n");
- #endif
-#endif
dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
-#if 0
-
- reg = pci_read_config32(register_values[i]);
- reg &= register_values[i+1];
- reg |= register_values[i+2];
- pci_write_config32(register_values[i], reg);
-#endif
}
- print_spew("done.\r\n");
+ printk_spew("done.\n");
}
-
static void hw_enable_ecc(const struct mem_controller *ctrl)
{
uint32_t dcl, nbcap;
*/
uint32_t dcl;
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
- return !(dcl & DCL_UnBufDimm);
+ return !(dcl & DCL_UnBuffDimm);
}
struct dimm_size {
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
#if QRANK_DIMM_SUPPORT == 1
- if(sz.rank == 4) {
+ if (sz.rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
}
dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
dch |= DCH_MEMCLK_EN0 << index;
#if QRANK_DIMM_SUPPORT == 1
- if(sz.rank == 4) {
+ if (sz.rank == 4) {
dch |= DCH_MEMCLK_EN0 << (index + 2);
}
#endif
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
#if QRANK_DIMM_SUPPORT == 1
- if(sz.rank == 4) {
+ if (sz.rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
#endif
/* Make certain side1 of the dimm is at least 32MB */
if (sz.side1 >= (25 +3)) {
- if(is_cpu_pre_d0()) {
+ if (is_cpu_pre_d0()) {
map |= (sz.side1 - (25 + 3)) << (index *4);
#if QRANK_DIMM_SUPPORT == 1
- if(sz.rank == 4) {
+ if (sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
}
#endif
else {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
#if QRANK_DIMM_SUPPORT == 1
- if(sz.rank == 4) {
+ if (sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
}
#endif
{
int i;
- for(i = 0; i < DIMM_SOCKETS; i++) {
+ for (i = 0; i < DIMM_SOCKETS; i++) {
struct dimm_size sz;
if (!(dimm_mask & (1 << i))) {
continue;
limit_reg = 0x44 + index;
base_reg = 0x40 + index;
- for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
+ for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
pci_write_config32(device, limit_reg, limit);
pci_write_config32(device, base_reg, base);
}
}
/* Report the amount of memory. */
- print_spew("RAM: 0x");
- print_spew_hex32(tom_k);
- print_spew(" KB\r\n");
+ printk_spew("RAM: 0x%08x kB\n", tom_k);
/* Now set top of memory */
msr_t msr;
- if(tom_k > (4*1024*1024)) {
+ if (tom_k > (4*1024*1024)) {
msr.lo = (tom_k & 0x003fffff) << 10;
msr.hi = (tom_k & 0xffc00000) >> 22;
wrmsr(TOP_MEM2, msr);
*/
if (tom_k >= 0x003f0000) {
#if HW_MEM_HOLE_SIZEK != 0
- if(hole_startk != 0) {
+ if (hole_startk != 0) {
tom_k = hole_startk;
} else
#endif
chip_selects = 0;
common_size = 0;
common_cs_mode = 0;
- for(index = 0; index < 8; index++) {
+ for (index = 0; index < 8; index++) {
unsigned size;
unsigned cs_mode;
uint32_t value;
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
cs_mode =( value >> ((index>>1)*4)) & 0xf;
- if(cs_mode == 0 ) continue;
- if(common_cs_mode == 0) {
+ if (cs_mode == 0 ) continue;
+ if (common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
- /* The size differed fail */
- if(common_cs_mode != cs_mode) {
+ /* The cs_mode differed fail */
+ if (common_cs_mode != cs_mode) {
return 0;
}
}
}
/* Find the bits of csbase that we need to interleave on */
- if(is_cpu_pre_d0()){
+ if (is_cpu_pre_d0()){
csbase_inc = 1 << csbase_low_shift[common_cs_mode];
- if(is_dual_channel(ctrl)) {
+ if (is_dual_channel(ctrl)) {
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-// print_debug("8 4GB chip selects cannot be interleaved\r\n");
+// printk_debug("8 4GB chip selects cannot be interleaved\n");
return 0;
}
csbase_inc <<=1;
}
else {
csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
- if(is_dual_channel(ctrl)) {
- if( (bits==3) && (common_cs_mode > 8)) {
-// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
+ if (is_dual_channel(ctrl)) {
+ if ( (bits==3) && (common_cs_mode > 8)) {
+// printk_debug("8 cs_mode>8 chip selects cannot be interleaved\n");
return 0;
}
csbase_inc <<=1;
csbase = 0 | 1;
csmask = (((common_size << bits) - 1) << 21);
csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc);
- for(index = 0; index < 8; index++) {
+ for (index = 0; index < 8; index++) {
uint32_t value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
csbase += csbase_inc;
}
- print_spew("Interleaved\r\n");
+ printk_spew("Interleaved\n");
/* Return the memory size in K */
return common_size << (15 + bits);
/* Remember which registers we have used in the high 8 bits of tom */
tom = 0;
- for(;;) {
- /* Find the largest remaining canidate */
- unsigned index, canidate;
+ for (;;) {
+ /* Find the largest remaining candidate */
+ unsigned index, candidate;
uint32_t csbase, csmask;
unsigned size;
csbase = 0;
- canidate = 0;
- for(index = 0; index < 8; index++) {
+ candidate = 0;
+ for (index = 0; index < 8; index++) {
uint32_t value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
if (tom & (1 << (index + 24))) {
continue;
}
- /* I have a new canidate */
+ /* I have a new candidate */
csbase = value;
- canidate = index;
+ candidate = index;
}
- /* See if I have found a new canidate */
+
+ /* See if I have found a new candidate */
if (csbase == 0) {
break;
}
size = csbase >> 21;
/* Remember I have used this register */
- tom |= (1 << (canidate + 24));
+ tom |= (1 << (candidate + 24));
/* Recompute the cs base register value */
csbase = (tom << 21) | 1;
csmask |= 0xfe00; /* For now don't optimize */
/* Write the new base register */
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
+ pci_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
/* Write the new mask register */
- pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
+ pci_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
}
/* Return the memory size in K */
unsigned end_k;
/* Find the last memory address used */
end_k = 0;
- for(node_id = 0; node_id < max_node_id; node_id++) {
+ for (node_id = 0; node_id < max_node_id; node_id++) {
uint32_t limit, base;
unsigned index;
index = node_id << 3;
read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
tom_k = interleave_chip_selects(ctrl);
} else {
- print_debug("Interleaving disabled\r\n");
+ printk_debug("Interleaving disabled\n");
tom_k = 0;
}
+
if (!tom_k) {
tom_k = order_chip_selects(ctrl);
}
+
/* Compute the memory base address */
base_k = memory_end_k(ctrl, ctrl->node_id);
tom_k += base_k;
static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
{
- print_debug("disabling dimm");
- print_debug_hex8(index);
- print_debug("\r\n");
+ printk_debug("disabling dimm %02x\n", index);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
dimm_mask &= ~(1 << index);
return dimm_mask;
}
-static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask)
+static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
+ long dimm_mask)
{
int i;
int registered;
uint32_t dcl;
unbuffered = 0;
registered = 0;
- for(i = 0; (i < DIMM_SOCKETS); i++) {
+ for (i = 0; (i < DIMM_SOCKETS); i++) {
int value;
if (!(dimm_mask & (1 << i))) {
continue;
if (value < 0) {
return -1;
}
+
/* Registered dimm ? */
if (value & (1 << 1)) {
registered = 1;
}
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
- dcl &= ~DCL_UnBufDimm;
+ dcl &= ~DCL_UnBuffDimm;
if (unbuffered) {
if ((has_dualch) && (!is_cpu_pre_d0())) {
- dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
+ dcl |= DCL_UnBuffDimm; /* set DCL_DualDIMMen too? */
/* set DCL_En2T if you have non-equal DDR mem types! */
dcl |= DCL_UpperCSMap;
}
} else {
- dcl |= DCL_UnBufDimm;
+ dcl |= DCL_UnBuffDimm;
}
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-#if 0
+
if (is_registered(ctrl)) {
- print_debug("Registered\r\n");
+ printk_spew("Registered\n");
} else {
- print_debug("Unbuffered\r\n");
+ printk_spew("Unbuffered\n");
}
-#endif
+
return dimm_mask;
}
unsigned dimm_mask;
int i;
dimm_mask = 0;
- for(i = 0; i < DIMM_SOCKETS; i++) {
+ for (i = 0; i < DIMM_SOCKETS; i++) {
int byte;
unsigned device;
device = ctrl->channel0[i];
if (!(nbcap & NBCAP_128Bit)) {
goto single_channel;
}
- for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+ for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
unsigned device0, device1;
int value0, value1;
int j;
}
device0 = ctrl->channel0[i];
device1 = ctrl->channel1[i];
- for(j = 0; j < ARRAY_SIZE(addresses); j++) {
+ for (j = 0; j < ARRAY_SIZE(addresses); j++) {
unsigned addr;
addr = addresses[j];
value0 = spd_read_byte(device0, addr);
}
}
}
- print_spew("Enabling dual channel memory\r\n");
+ printk_spew("Enabling dual channel memory\n");
uint32_t dcl;
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_32ByteEn;
{
static const struct mem_param speed[] = {
{
- .name = "100Mhz\r\n",
+ .name = "100Mhz",
.cycle_time = 0xa0,
.divisor = (10 <<1),
.tRC = 0x46,
.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
},
{
- .name = "133Mhz\r\n",
+ .name = "133Mhz",
.cycle_time = 0x75,
.divisor = (7<<1)+1,
.tRC = 0x41,
.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
},
{
- .name = "166Mhz\r\n",
+ .name = "166Mhz",
.cycle_time = 0x60,
.divisor = (6<<1),
.tRC = 0x3C,
.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
},
{
- .name = "200Mhz\r\n",
+ .name = "200Mhz",
.cycle_time = 0x50,
.divisor = (5<<1),
.tRC = 0x37,
},
};
const struct mem_param *param;
- for(param = &speed[0]; param->cycle_time ; param++) {
+ for (param = &speed[0]; param->cycle_time ; param++) {
if (min_cycle_time > (param+1)->cycle_time) {
break;
}
if (!param->cycle_time) {
die("min_cycle_time to low");
}
- print_spew(param->name);
-#ifdef DRAM_MIN_CYCLE_TIME
- print_debug(param->name);
-#endif
+ printk_spew("%s\n", param->name);
return param;
}
/* Compute the least latency with the fastest clock supported
* by both the memory controller and the dimms.
*/
- for(i = 0; i < DIMM_SOCKETS; i++) {
+ for (i = 0; i < DIMM_SOCKETS; i++) {
int new_cycle_time, new_latency;
int index;
int latencies;
latency = log2(latencies) -2;
/* Loop through and find a fast clock with a low latency */
- for(index = 0; index < 3; index++, latency++) {
+ for (index = 0; index < 3; index++, latency++) {
int spd_value;
if ((latency < 2) || (latency > 4) ||
(!(latencies & (1 << latency)))) {
* any that cannot support the selected memclk and cas latency.
*/
- for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+ for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
int latencies;
int latency;
int index;
if (!(dimm_mask & (1 << i))) {
continue;
}
+
latencies = spd_read_byte(ctrl->channel0[i], 18);
if (latencies < 0) goto hw_error;
if (latencies == 0) {
latency = log2(latencies) -2;
/* Walk through searching for the selected latency */
- for(index = 0; index < 3; index++, latency++) {
+ for (index = 0; index < 3; index++, latency++) {
if (!(latencies & (1 << latency))) {
continue;
}
#if 0
//down speed for full load 4 rank support
#if QRANK_DIMM_SUPPORT
- if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
+ if (dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
int ranks = 4;
- for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+ for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
int val;
if (!(dimm_mask & (1 << i))) {
continue;
}
val = spd_read_byte(ctrl->channel0[i], 5);
- if(val!=ranks) {
+ if (val!=ranks) {
ranks = val;
break;
}
}
- if(ranks==4) {
- if(min_cycle_time <= 0x50 ) {
+ if (ranks==4) {
+ if (min_cycle_time <= 0x50 ) {
min_cycle_time = 0x60;
}
}
value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
#if 0
/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/
- if(!is_cpu_pre_e0()) {
- if(min_cycle_time==0x50) {
+ if (!is_cpu_pre_e0()) {
+ if (min_cycle_time==0x50) {
value |= 1<<31;
}
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
+
/* Update DRAM Timing Low with our selected cas latency */
value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
dimm = 1<<(DCL_x4DIMM_SHIFT+i);
#if QRANK_DIMM_SUPPORT == 1
- if(rank==4) {
+ if (rank==4) {
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
}
#endif
int dimms;
unsigned index;
dimms = 0;
- for(index = 0; index < 8; index += 2) {
+ for (index = 0; index < 8; index += 2) {
uint32_t csbase;
csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2)));
if (csbase & 1) {
clocks = param->dtl_trwt[lat][mtype];
if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
- die("Unknown Trwt\r\n");
+ die("Unknown Trwt\n");
}
dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
slots = 0;
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++) {
if (ctrl->channel0[i]) {
slots += 1;
}
int i;
init_Tref(ctrl, param);
- for(i = 0; i < DIMM_SOCKETS; i++) {
+ for (i = 0; i < DIMM_SOCKETS; i++) {
int rc;
if (!(dimm_mask & (1 << i))) {
continue;
long dimm_mask;
#if 1
if (!controller_present(ctrl)) {
-// print_debug("No memory controller present\r\n");
+// printk_debug("No memory controller present\n");
return;
}
#endif
activate_spd_rom(ctrl);
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_debug("No memory for this cpu\r\n");
+ printk_debug("No memory for this cpu\n");
return;
}
dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
return;
hw_spd_err:
/* Unrecoverable error reading SPD data */
- print_err("SPD error - reset\r\n");
+ print_err("SPD error - reset\n");
hard_reset();
return;
}
carry_over = (4*1024*1024) - hole_startk;
- for(ii=controllers - 1;ii>i;ii--) {
+ for (ii=controllers - 1;ii>i;ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
- for(j = 0; j < controllers; j++) {
+ for (j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
}
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
- for(j = 0; j < controllers; j++) {
+ for (j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
}
dev = ctrl[i].f1;
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
- if(basek == hole_startk) {
+ if (basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
- for(j = 0; j < controllers; j++) {
+ for (j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
}
}
* we need to decrease it.
*/
uint32_t basek_pri;
- for(i=0; i<controllers; i++) {
+ for (i=0; i<controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
continue;
}
base_k = (base & 0xffff0000) >> 2;
- if(base_k == hole_startk) {
+ if (base_k == hole_startk) {
/* decrease memory hole startk to make sure it is
* in the middle of the previous node
*/
#endif
/* Find node number that needs the memory hole configured */
- for(i=0; i<controllers; i++) {
+ for (i=0; i<controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
/* Error if I don't have memory */
if (memory_end_k(ctrl, controllers) == 0) {
- die("No memory\r\n");
+ die("No memory\n");
}
/* Before enabling memory start the memory clocks */
- for(i = 0; i < controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t dch;
if (!controller_present(ctrl + i))
continue;
}
}
+ /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
/* And if necessary toggle the the reset on the dimms by hand */
memreset(controllers, ctrl);
- /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
-
- for(i = 0; i < controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t dcl, dch;
if (!controller_present(ctrl + i))
continue;
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
if (dcl & DCL_DimmEccEn) {
uint32_t mnc;
- print_spew("ECC enabled\r\n");
+ printk_spew("ECC enabled\n");
mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
mnc |= MNC_ECC_EN;
if (dcl & DCL_128BitEn) {
dcl &= ~DCL_QFC_EN;
dcl |= DCL_DramInit;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
-
}
- for(i = 0; i < controllers; i++) {
+
+ for (i = 0; i < controllers; i++) {
uint32_t dcl, dch;
if (!controller_present(ctrl + i))
continue;
continue;
}
- print_debug("Initializing memory: ");
-
+ printk_debug("Initializing memory: ");
int loops = 0;
do {
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
- loops += 1;
+ loops++;
if ((loops & 1023) == 0) {
- print_debug(".");
+ printk_debug(".");
}
} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
if (loops >= TIMEOUT_LOOPS) {
- print_debug(" failed\r\n");
+ printk_debug(" failed\n");
continue;
}
} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
}
- print_debug(" done\r\n");
+ printk_debug(" done\n");
}
#if HW_MEM_HOLE_SIZEK != 0
// init hw mem hole here
/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
- if(!is_cpu_pre_e0())
+ if (!is_cpu_pre_e0())
set_hw_mem_hole(controllers, ctrl);
#endif
5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
*/
-#if USE_DCACHE_RAM == 0
- /* Make certain the first 1M of memory is intialized */
- print_debug("Clearing initial memory region: ");
-
- /* Use write combine caching while we setup the first 1M */
- cache_lbmem(MTRR_TYPE_WRCOMB);
-
- /* clear memory 1meg */
- clear_memory((void *)0, CONFIG_LB_MEM_TOPK << 10);
-
- /* The first 1M is now setup, use it */
- cache_lbmem(MTRR_TYPE_WRBACK);
-
- print_debug(" done\r\n");
-#endif
}
-#if USE_DCACHE_RAM == 1
static void set_sysinfo_in_ram(unsigned val)
{
}
-static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
+static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
+ const uint16_t *spd_addr)
{
int i;
int j;
struct mem_controller *ctrl;
- for(i=0;i<controllers; i++) {
+ for (i=0;i<controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
- if(spd_addr == (void *)0) continue;
+ if (spd_addr == (void *)0) continue;
- for(j=0;j<DIMM_SOCKETS;j++) {
+ for (j=0;j<DIMM_SOCKETS;j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
}
}
-#endif
-
-#endif
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
-
printk_spew("done.\n");
}
-
static int is_dual_channel(const struct mem_controller *ctrl)
{
uint32_t dcl;
return dcl & DCL_Width128;
}
-
static int is_opteron(const struct mem_controller *ctrl)
{
/* Test to see if I am an Opteron.
return !!(nbcap & NBCAP_128Bit);
}
-
static int is_registered(const struct mem_controller *ctrl)
{
/* Test to see if we are dealing with registered SDRAM.
static void set_dimm_size(const struct mem_controller *ctrl,
- struct dimm_size *sz, unsigned index, struct mem_info *meminfo)
+ struct dimm_size *sz, unsigned index,
+ struct mem_info *meminfo)
{
uint32_t base0, base1;
return -1; /* Report SPD error */
}
set_dimm_size(ctrl, sz, i, meminfo);
- set_dimm_cs_map (ctrl, sz, i, meminfo);
+ set_dimm_cs_map(ctrl, sz, i, meminfo);
}
return meminfo->dimm_mask;
}
-
static void route_dram_accesses(const struct mem_controller *ctrl,
- unsigned long base_k, unsigned long limit_k)
+ unsigned long base_k, unsigned long limit_k)
{
/* Route the addresses to the controller node */
unsigned node_id;
}
}
-
static void set_top_mem(unsigned tom_k, unsigned hole_startk)
{
/* Error if I don't have memory */
/* Report the amount of memory. */
printk_debug("RAM: 0x%08x kB\n", tom_k);
+ /* Now set top of memory */
msr_t msr;
if (tom_k > (4*1024*1024)) {
- /* Now set top of memory */
msr.lo = (tom_k & 0x003fffff) << 10;
msr.hi = (tom_k & 0xffc00000) >> 22;
wrmsr(TOP_MEM2, msr);
csbase_inc <<=1;
}
-
/* Compute the initial values for csbase and csbask.
* In csbase just set the enable bit and the base to zero.
* In csmask set the mask bits for the size and page level interleave.
/* Return the memory size in K */
return common_size << ((27-10) + bits);
}
+
static unsigned long order_chip_selects(const struct mem_controller *ctrl)
{
unsigned long tom;
return end_k;
}
-
static void order_dimms(const struct mem_controller *ctrl,
struct mem_info *meminfo)
{
printk_debug("Interleaving disabled\n");
tom_k = 0;
}
-
+
if (!tom_k) {
tom_k = order_chip_selects(ctrl);
}
-
+
/* Compute the memory base address */
base_k = memory_end_k(ctrl, ctrl->node_id);
tom_k += base_k;
set_top_mem(tom_k, 0);
}
-
static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
struct mem_info *meminfo)
{
return meminfo->dimm_mask;
}
-
static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
struct mem_info *meminfo)
{
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-#if 1
if (meminfo->is_registered) {
- printk_debug("Registered\n");
+ printk_spew("Registered\n");
} else {
- printk_debug("Unbuffered\n");
+ printk_spew("Unbuffered\n");
}
-#endif
return meminfo->dimm_mask;
}
-
static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
{
unsigned dimm_mask;
if (!param->cycle_time) {
die("min_cycle_time to low");
}
- printk_debug("%s\n", param->name);
+ printk_spew("%s\n", param->name);
return param;
}
return 1;
}
-
static int update_dimm_Trcd(const struct mem_controller *ctrl,
const struct mem_param *param, int i, long dimm_mask)
{
if (clocks < DTL_TRAS_MIN) {
clocks = DTL_TRAS_MIN;
}
-
if (clocks > DTL_TRAS_MAX) {
return 0;
}
-
dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
if (old_clocks >= clocks) { // someone did it?
return 1;
}
-
dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
-
static void set_4RankRDimm(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
#endif
}
-
static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
struct mem_info *meminfo)
{
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
-
static void set_ecc(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
}
-
static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
{
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
}
-
static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
{
set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
}
-
static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
{
static const uint8_t faw_1k[] = {8, 10, 13, 14};
}
set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
-
}
-
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
{
uint32_t dch;
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
-
static void set_SlowAccessMode(const struct mem_controller *ctrl)
{
uint32_t dch;
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
-
/*
DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
DRAM_ADDR_TIMING_CTRL 04, 0x24
#endif
}
-
static void set_idle_cycle_limit(const struct mem_controller *ctrl,
const struct mem_param *param)
{
pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
}
-
static void set_RdWrQByp(const struct mem_controller *ctrl,
const struct mem_param *param)
{
set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
}
-
static long spd_set_dram_timing(const struct mem_controller *ctrl,
const struct mem_param *param,
struct mem_info *meminfo)
/* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
memreset(controllers, ctrl);
-#if 0
- printk_debug("prepare to InitDram:");
- for (i=0; i<10; i++) {
- printk_debug("%08x", i);
- print_debug("\b\b\b\b\b\b\b\b");
- }
- printk_debug("\n");
-#endif
/* lets override the rest of the routine */
if (suspend) {
}
-
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
- const uint16_t *spd_addr)
+ const uint16_t *spd_addr)
{
int i;
int j;
projects / coreboot.git / commitdiff