src/northbridge/amd/amdfam10/raminit_amdmct.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 static  void print_raminit(const char *strval, u32 val)
  22 {
  23         printk_debug("%s%08x\n", strval, val);
  24 }
  25
  26 static  void print_tx(const char *strval, u32 val)
  27 {
  28 #if CONFIG_DEBUG_RAM_SETUP
  29         print_raminit(strval, val);
  30 #endif
  31 }
  32
  33 static  void print_t(const char *strval)
  34 {
  35 #if CONFIG_DEBUG_RAM_SETUP
  36         print_debug(strval);
  37 #endif
  38 }
  39 #include "amdfam10.h"
  40 #include "../amdmct/wrappers/mcti.h"
  41 #include "../amdmct/amddefs.h"
  42 #include "../amdmct/mct/mct_d.h"
  43 #include "../amdmct/mct/mct_d_gcc.h"
  44
  45 #include "../amdmct/wrappers/mcti_d.c"
  46 #include "../amdmct/mct/mct_d.c"
  47
  48
  49 #include "../amdmct/mct/mctmtr_d.c"
  50 #include "../amdmct/mct/mctcsi_d.c"
  51 #include "../amdmct/mct/mctecc_d.c"
  52 #include "../amdmct/mct/mctpro_d.c"
  53 #include "../amdmct/mct/mctdqs_d.c"
  54 #include "../amdmct/mct/mctsrc.c"
  55 #include "../amdmct/mct/mctsrc1p.c"
  56 #include "../amdmct/mct/mcttmrl.c"
  57 #include "../amdmct/mct/mcthdi.c"
  58 #include "../amdmct/mct/mctndi_d.c"
  59 #include "../amdmct/mct/mctchi_d.c"
  60
  61 #if CONFIG_CPU_SOCKET_TYPE == 0x10
  62 //L1
  63 #include "../amdmct/mct/mctardk3.c"
  64 #elif CONFIG_CPU_SOCKET_TYPE == 0x11
  65 //AM2
  66 #include "../amdmct/mct/mctardk4.c"
  67 //#elif SYSTEM_TYPE == MOBILE
  68 //s1g1
  69 //#include "../amdmct/mct/mctardk5.c"
  70 #endif
  71
  72 #include "../amdmct/mct/mct_fd.c"
  73
  74 int mctRead_SPD(u32 smaddr, u32 reg)
  75 {
  76         return spd_read_byte(smaddr, reg);
  77 }
  78
  79
  80 void mctSMBhub_Init(u32 node)
  81 {
  82         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  83         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
  84         activate_spd_rom(ctrl);
  85 }
  86
  87
  88 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
  89 {
  90         int j;
  91         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  92         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
  93
  94         for(j=0;j<DIMM_SOCKETS;j++) {
  95                 pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff;
  96                 pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff;
  97         }
  98
  99 }
 100
 101
 102 u32 mctGetLogicalCPUID(u32 Node)
 103 {
 104         /* FIXME: Move this to a more generic place. Maybe to the CPU code */
 105         /* Converts the CPUID to a logical ID MASK that is used to check
 106          CPU version support versions */
 107         u32 dev;
 108         u32 val, valx;
 109         u32 family, model, stepping;
 110         u32 ret;
 111
 112         if (Node == 0xFF) { /* current node */
 113                 val = cpuid_eax(0x80000001);
 114         } else {
 115                 dev = PA_NBMISC(Node);
 116                 val = Get_NB32(dev, 0xfc);
 117         }
 118
 119         family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
 120         model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
 121         stepping = val & 0x0f;
 122
 123         valx = (family << 12) | (model << 4) | (stepping);
 124
 125         switch (valx) {
 126         case 0x10000:
 127                 ret = AMD_DR_A0A;
 128                 break;
 129         case 0x10001:
 130                 ret = AMD_DR_A1B;
 131                 break;
 132         case 0x10002:
 133                 ret = AMD_DR_A2;
 134                 break;
 135         case 0x10020:
 136                 ret = AMD_DR_B0;
 137                 break;
 138         case 0x10021:
 139                 ret = AMD_DR_B1;
 140                 break;
 141         case 0x10022:
 142                 ret = AMD_DR_B2;
 143                 break;
 144         case 0x10023:
 145                 ret = AMD_DR_B3;
 146                 break;
 147         case 0x10042:
 148                 ret = AMD_RB_C2;
 149                 break;
 150         case 0x10062:
 151                 ret = AMD_DA_C2;
 152                 break;
 153         case 0x10080:
 154                 ret = AMD_HY_D0;
 155                 break;
 156         default:
 157                 /* FIXME: mabe we should die() here. */
 158                 print_err("FIXME! CPU Version unknown or not supported! \n");
 159                 ret = 0;
 160         }
 161
 162         return ret;
 163 }
 164
 165
 166 void raminit_amdmct(struct sys_info *sysinfo)
 167 {
 168         struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
 169         struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
 170
 171         print_debug("raminit_amdmct begin:\n");
 172
 173         mctAutoInitMCT_D(pMCTstat, pDCTstatA);
 174
 175         print_debug("raminit_amdmct end:\n");
 176 }