The following patch implements Opteron Fam 10 rev D (aka Istanbul)

support for coreboot.  I have not updated MAX_CPUS for all fam10
mainboards, but it might make sense to multiply those by 1.5.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
I assume the line
pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
should be put outside the loop.

Everything seems to be fine. I don't have Istanbul to test. I have
read every changes and they all look good.

Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 65290089f1c76c1c2bd4be2c720561b50878e025..b1b245a2d804598687edbb8b586a9479addaf88e 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -315,44 +315,44 @@ static const struct {
        u32 mask;
 } fam10_htphy_default[] = {
 
-       /* Errata 344 - Fam10 C2
+       /* Errata 344 - Fam10 C2/D0
         * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
-       { 0x60, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x60, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x61, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x62, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x63, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x64, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x65, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x66, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x67, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x68, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       { 0x70, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x71, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x72, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x73, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x74, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x75, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x76, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x77, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x78, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
        /* Errata 354 - Fam10 C2
@@ -395,20 +395,20 @@ static const struct {
        { 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       /* Errata 327 - Fam10 C2
+       /* Errata 327 - Fam10 C2/D0
         * BIOS should set the Link Phy Impedance Register[RttCtl]
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
         * Link Phy Impedance Register[RttIndex]
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
-       { 0xC0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
-       { 0xD0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
 
-       { 0x520A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
-       { 0x530A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
        { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,

diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 0b54d44459186f08e602cd16e56a8c3fc9dad97c..daf3eceaa4e0a92bb74e0f3b1b53ed0696f5c328 100644 (file)
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -146,6 +146,7 @@ static struct cpu_device_id cpu_table[] = {
        { X86_VENDOR_AMD, 0x100F42 },           /* RB-C2 */ 
        { X86_VENDOR_AMD, 0x100F52 },           /* BL-C2 */ 
        { X86_VENDOR_AMD, 0x100F62 },           /* DA-C2 */ 
+       { X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */ 
        { 0, 0 },
 };
 static struct cpu_driver model_10xxx __cpu_driver = {

diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index ac629817235e76a6eac808c9840ee7563a8318d3..7d621c5375062653a7d7b3b4473a9bd4ddedb752 100644 (file)
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -29,7 +29,11 @@ static u32 get_core_num_in_bsp(u32 nodeid)
        u32 dword;
        dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
        dword >>= 12;
-       dword &= 3;
+       /* Bit 15 is CmpCap[2] since Revision D. */
+       if ((cpuid_ecx(0x80000008) & 0xff) > 3)
+           dword = ((dword & 8) >> 1) | (dword & 3);
+       else
+           dword &= 3;
        return dword;
 }
 
@@ -53,7 +57,7 @@ static void set_apicid_cpuid_lo(void) { }
 
 static void real_start_other_core(u32 nodeid, u32 cores)
 {
-       u32 dword;
+       u32 dword, i;
 
        printk_debug("Start other core - nodeid: %02x  cores: %02x\n", nodeid, cores);
 
@@ -69,9 +73,8 @@ static void real_start_other_core(u32 nodeid, u32 cores)
 
        if(cores > 1) {
                dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
-               dword |= (1 << 0);      // core2
-               if(cores > 2) {         // core3
-                       dword |= (1 << 1);
+               for (i = 0; i < cores - 1; i++) {
+                       dword |= 1 << i;
                }
                pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
        }

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index e7ac7efc11c800dce0cda147829180507cd59f57..86f3e5224fd7e85448b84bf2dcd4aed9818cc3e9 100644 (file)
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1364,6 +1364,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
                if (dev && dev->enabled) {
                        j = pci_read_config32(dev, 0xe8);
                        cores_found = (j >> 12) & 3; // dev is func 3
+                       if (siblings > 3)
+                               cores_found |= (j >> 13) & 4;
                        printk_debug("  %s siblings=%d\n", dev_path(dev), cores_found);
                }
 

diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index c9f0c27b0b2b750e9d9fdbbb2274a1f44e9baa59..21f1e188e5189b0596baa409efc48e48d6ae25e3 100644 (file)
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -150,6 +150,9 @@ u32 mctGetLogicalCPUID(u32 Node)
        case 0x10062:
                ret = AMD_DA_C2;
                break;
+       case 0x10080:
+               ret = AMD_HY_D0;
+               break;
        default:
                /* FIXME: mabe we should die() here. */
                print_err("FIXME! CPU Version unknown or not supported! \n");

diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 004e4cf50d3d8f5dada8130a7dc674800d51c871..1b75888b123c6af7c95ce9321cafcef59ff48f1b 100644 (file)
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -42,6 +42,7 @@
 #define        AMD_DR_B3       0x00800000      /* Barcelona B3 */
 #define        AMD_RB_C2       0x01000000      /* Shanghai C2 */
 #define        AMD_DA_C2       0x02000000      /* XXXX C2 */
+#define        AMD_HY_D0       0x04000000      /* Istanbul D0 */
 
 /*
  * Groups - Create as many as you wish, from the above public values
@@ -59,7 +60,7 @@
 #define        AMD_DR_LT_B3    (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
 #define        AMD_DR_GT_B0    (AMD_DR_ALL & ~(AMD_DR_B0))
 #define        AMD_DR_ALL      (AMD_DR_Bx)
-#define        AMD_FAM10_ALL   (AMD_DR_ALL | AMD_RB_C2)
+#define        AMD_FAM10_ALL   (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0)
 #define        AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
 
 /*