2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
32 #include <cpu/x86/lapic.h>
34 #if CONFIG_LOGICAL_CPUS==1
35 #include <cpu/amd/multicore.h>
36 #include <pc80/mc146818rtc.h>
40 #include "root_complex/chip.h"
41 #include "northbridge.h"
45 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
46 #include <cpu/amd/model_10xxx_rev.h>
49 #include <cpu/amd/amdfam10_sysconf.h>
50 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800
52 #elif CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
56 struct amdfam10_sysconf_t sysconf;
58 #define FX_DEVS NODE_NUMS
59 static device_t __f0_dev[FX_DEVS];
60 static device_t __f1_dev[FX_DEVS];
61 static device_t __f2_dev[FX_DEVS];
62 static device_t __f4_dev[FX_DEVS];
63 static unsigned fx_devs=0;
65 device_t get_node_pci(u32 nodeid, u32 fn)
69 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
71 return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
75 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
79 static void get_fx_devs(void)
82 for(i = 0; i < FX_DEVS; i++) {
83 __f0_dev[i] = get_node_pci(i, 0);
84 __f1_dev[i] = get_node_pci(i, 1);
85 __f2_dev[i] = get_node_pci(i, 2);
86 __f4_dev[i] = get_node_pci(i, 4);
87 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
90 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
91 die("Cannot find 0:0x18.[0|1]\n");
95 static u32 f1_read_config32(unsigned reg)
99 return pci_read_config32(__f1_dev[0], reg);
102 static void f1_write_config32(unsigned reg, u32 value)
107 for(i = 0; i < fx_devs; i++) {
110 if (dev && dev->enabled) {
111 pci_write_config32(dev, reg, value);
116 static u32 amdfam10_nodeid(device_t dev)
120 busn = dev->bus->secondary;
121 if(busn != CONFIG_CBB) {
122 return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
124 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
128 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
134 static void set_vga_enable_reg(u32 nodeid, u32 linkn)
138 val = 1 | (nodeid<<4) | (linkn<<12);
139 /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
141 f1_write_config32(0xf4, val);
145 static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink,
146 u32 max, u32 offset_unitid)
148 // I want to put sb chain in bus 0 can I?
150 printk(BIOS_INFO, "%s: starting...\n", __func__);
155 u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
158 u32 is_sublink1 = (link_num>3);
162 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
167 #if CONFIG_HT3_SUPPORT==1
171 regpos = 0x170 + 4 * (link_num&3); // it is only on sublink0
172 reg = pci_read_config32(dev, regpos);
173 if(reg & 1) return max; // already ganged no sblink1
174 devx = get_node_pci(nodeid, 4);
180 link->cap = 0x80 + ((link_num&3) *0x20);
182 link_type = pci_read_config32(devx, link->cap + 0x18);
183 printk(BIOS_INFO, "%s: link_type: 0x%08x\n", __func__, link_type);
184 } while(link_type & ConnectionPending);
185 if (!(link_type & LinkConnected)) {
189 link_type = pci_read_config32(devx, link->cap + 0x18);
190 printk(BIOS_INFO, "%s: link_type: 0x%08x\n", __func__, link_type);
191 } while(!(link_type & InitComplete));
192 if (!(link_type & NonCoherent)) {
195 /* See if there is an available configuration space mapping
196 * register in function 1.
198 printk(BIOS_INFO, "%s: before get_ht_c_index\n", __func__);
199 ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf);
200 printk(BIOS_INFO, "%s: after get_ht_c_index\n", __func__);
202 #if CONFIG_EXT_CONF_SUPPORT == 0
203 if(ht_c_index>=4) return max;
206 /* Set up the primary, secondary and subordinate bus numbers.
207 * We have no idea how many busses are behind this bridge yet,
208 * so we set the subordinate bus number to 0xff for the moment.
210 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
211 // first chain will on bus 0
212 if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here
215 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
216 // second chain will be on 0x40, third 0x80, forth 0xc0
217 // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0
218 // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config.
220 min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same
222 max = min_bus | (segn<<8);
232 max_bus = 0xfc | (segn<<8);
234 link->secondary = min_bus;
235 link->subordinate = max_bus;
237 /* Read the existing primary/secondary/subordinate bus
238 * number configuration.
240 busses = pci_read_config32(devx, link->cap + 0x14);
242 /* Configure the bus numbers for this bridge: the configuration
243 * transactions will not be propagates by the bridge if it is
244 * not correctly configured
246 busses &= 0xffff00ff;
247 busses |= ((u32)(link->secondary) << 8);
248 pci_write_config32(devx, link->cap + 0x14, busses);
251 /* set the config map space */
253 printk(BIOS_INFO, "%s: before set_config_map_reg\n", __func__);
254 set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
255 printk(BIOS_INFO, "%s: after set_config_map_reg\n", __func__);
257 /* Now we can scan all of the subordinate busses i.e. the
258 * chain on the hypertranport link
261 ht_unitid_base[i] = 0x20;
264 //if ext conf is enabled, only need use 0x1f
266 max_devfn = (0x17<<3) | 7;
268 max_devfn = (0x1f<<3) | 7;
270 printk(BIOS_INFO, "%s: before hypertransport_scan_chain\n", __func__);
272 max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid);
273 printk(BIOS_INFO, "%s: after hypertransport_scan_chain\n", __func__);
275 /* We know the number of busses behind this bridge. Set the
276 * subordinate bus number to it's real value
278 if(ht_c_index>3) { // clear the extend reg
279 printk(BIOS_INFO, "%s: before clear_config_map_reg\n", __func__);
280 clear_config_map_reg(nodeid, link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes);
281 printk(BIOS_INFO, "%s: after clear_config_map_reg\n", __func__);
284 link->subordinate = max;
285 printk(BIOS_INFO, "%s: before set_config_map_reg\n", __func__);
286 set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
287 printk(BIOS_INFO, "%s: after set_config_map_reg\n", __func__);
291 // use ht_unitid_base to update hcdn_reg
294 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
297 sysconf.hcdn_reg[ht_c_index] = temp;
300 printk(BIOS_INFO, "%s: before store_ht_c_conf_bus\n", __func__);
301 store_ht_c_conf_bus(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, &sysconf);
302 printk(BIOS_INFO, "%s: after store_ht_c_conf_bus\n", __func__);
303 printk(BIOS_INFO, "%s: done.\n", __func__);
307 static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
311 unsigned sblink = sysconf.sblk;
312 unsigned offset_unitid = 0;
314 printk(BIOS_INFO, "%s: starting...\n", __func__);
316 nodeid = amdfam10_nodeid(dev);
318 // Put sb chain in bus 0
319 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
321 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
324 for (link = dev->link_list; link; link = link->next) {
325 printk(BIOS_INFO, "%s: link: %p\n", __func__, link);
326 if (link->link_num == sblink)
327 max = amdfam10_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
332 #if CONFIG_PCI_BUS_SEGN_BITS
333 max = check_segn(dev, max, sysconf.nodes, &sysconf);
336 for(link = dev->link_list; link; link = link->next) {
337 printk(BIOS_INFO, "%s: link2: %p\n", __func__, link);
338 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
339 if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done
342 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
343 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
344 if((nodeid == 0) && (sblink == link->link_num))
349 max = amdfam10_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid);
351 printk(BIOS_INFO, "%s: done.\n", __func__);
356 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
359 struct resource *res;
360 unsigned nodeid, link = 0;
363 for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
365 dev = __f0_dev[nodeid];
368 for(link = 0; !res && (link < 8); link++) {
369 res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
375 if ( (goal_link == (link - 1)) &&
376 (goal_nodeid == (nodeid - 1)) &&
384 static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link)
386 struct resource *resource;
390 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
392 result = reg_useable(reg, dev, nodeid, link);
394 /* I have been allocated this one */
397 else if (result > 1) {
398 /* I have a free register pair */
403 reg = free_reg; // if no free, the free_reg still be 0
408 //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
409 u32 index = get_io_addr_index(nodeid, link);
410 reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
413 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
418 static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link)
420 struct resource *resource;
424 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
426 result = reg_useable(reg, dev, nodeid, link);
428 /* I have been allocated this one */
431 else if (result > 1) {
432 /* I have a free register pair */
442 //because of Extend conf space, we will never run out of reg,
443 // but we need one index to differ them. so same node and
444 // same link can have multi range
445 u32 index = get_mmio_addr_index(nodeid, link);
446 reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
449 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
454 static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
456 struct resource *resource;
458 /* Initialize the io space constraints on the current bus */
459 resource = amdfam10_find_iopair(dev, nodeid, link);
462 #if CONFIG_EXT_CONF_SUPPORT == 1
463 if((resource->index & 0x1fff) == 0x1110) { // ext
468 align = log2(HT_IO_HOST_ALIGN);
471 resource->align = align;
472 resource->gran = align;
473 resource->limit = 0xffffUL;
474 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
477 /* Initialize the prefetchable memory constraints on the current bus */
478 resource = amdfam10_find_mempair(dev, nodeid, link);
482 resource->align = log2(HT_MEM_HOST_ALIGN);
483 resource->gran = log2(HT_MEM_HOST_ALIGN);
484 resource->limit = 0xffffffffffULL;
485 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
486 resource->flags |= IORESOURCE_BRIDGE;
488 #if CONFIG_EXT_CONF_SUPPORT == 1
489 if((resource->index & 0x1fff) == 0x1110) { // ext
490 normalize_resource(resource);
496 /* Initialize the memory constraints on the current bus */
497 resource = amdfam10_find_mempair(dev, nodeid, link);
501 resource->align = log2(HT_MEM_HOST_ALIGN);
502 resource->gran = log2(HT_MEM_HOST_ALIGN);
503 resource->limit = 0xffffffffffULL;
504 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
505 #if CONFIG_EXT_CONF_SUPPORT == 1
506 if((resource->index & 0x1fff) == 0x1110) { // ext
507 normalize_resource(resource);
513 static void amdfam10_read_resources(device_t dev)
517 nodeid = amdfam10_nodeid(dev);
518 for(link = dev->link_list; link; link = link->next) {
519 if (link->children) {
520 amdfam10_link_read_bases(dev, nodeid, link->link_num);
525 static void amdfam10_set_resource(device_t dev, struct resource *resource,
528 resource_t rbase, rend;
529 unsigned reg, link_num;
532 /* Make certain the resource has actually been set */
533 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
537 /* If I have already stored this resource don't worry about it */
538 if (resource->flags & IORESOURCE_STORED) {
542 /* Only handle PCI memory and IO resources */
543 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
546 /* Ensure I am actually looking at a resource of function 1 */
547 if ((resource->index & 0xffff) < 0x1000) {
550 /* Get the base address */
551 rbase = resource->base;
553 /* Get the limit (rounded up) */
554 rend = resource_end(resource);
556 /* Get the register and link */
557 reg = resource->index & 0xfff; // 4k
558 link_num = IOINDEX_LINK(resource->index);
560 if (resource->flags & IORESOURCE_IO) {
562 set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
563 store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8);
565 else if (resource->flags & IORESOURCE_MEM) {
566 set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
567 store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);
569 resource->flags |= IORESOURCE_STORED;
570 sprintf(buf, " <node %x link %x>",
572 report_resource_stored(dev, resource, buf);
576 * I tried to reuse the resource allocation code in amdfam10_set_resource()
577 * but it is too difficult to deal with the resource allocation magic.
580 static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
584 /* find out which link the VGA card is connected,
585 * we only deal with the 'first' vga card */
586 for (link = dev->link_list; link; link = link->next) {
587 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
588 #if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
589 extern device_t vga_pri; // the primary vga device, defined in device.c
590 printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
591 link->secondary,link->subordinate);
592 /* We need to make sure the vga_pri is under the link */
593 if((vga_pri->bus->secondary >= link->secondary ) &&
594 (vga_pri->bus->secondary <= link->subordinate )
601 /* no VGA card installed */
605 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
606 set_vga_enable_reg(nodeid, link->link_num);
609 static void amdfam10_set_resources(device_t dev)
613 struct resource *res;
615 /* Find the nodeid */
616 nodeid = amdfam10_nodeid(dev);
618 amdfam10_create_vga_resource(dev, nodeid);
620 /* Set each resource we have found */
621 for(res = dev->resource_list; res; res = res->next) {
622 amdfam10_set_resource(dev, res, nodeid);
625 for(bus = dev->link_list; bus; bus = bus->next) {
627 assign_resources(bus);
632 static void mcf0_control_init(struct device *dev)
636 static struct device_operations northbridge_operations = {
637 .read_resources = amdfam10_read_resources,
638 .set_resources = amdfam10_set_resources,
639 .enable_resources = pci_dev_enable_resources,
640 .init = mcf0_control_init,
641 .scan_bus = amdfam10_scan_chains,
647 static const struct pci_driver mcf0_driver __pci_driver = {
648 .ops = &northbridge_operations,
649 .vendor = PCI_VENDOR_ID_AMD,
653 struct chip_operations northbridge_amd_amdfam10_ops = {
654 CHIP_NAME("AMD FAM10 Northbridge")
658 static void amdfam10_domain_read_resources(device_t dev)
662 /* Find the already assigned resource pairs */
664 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
666 base = f1_read_config32(reg);
667 limit = f1_read_config32(reg + 0x04);
668 /* Is this register allocated? */
669 if ((base & 3) != 0) {
670 unsigned nodeid, reg_link;
672 if(reg<0xc0) { // mmio
673 nodeid = (limit & 0xf) + (base&0x30);
675 nodeid = (limit & 0xf) + ((base>>4)&0x30);
677 reg_link = (limit >> 4) & 7;
678 reg_dev = __f0_dev[nodeid];
680 /* Reserve the resource */
681 struct resource *res;
682 res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
689 /* FIXME: do we need to check extend conf space?
690 I don't believe that much preset value */
692 #if CONFIG_PCI_64BIT_PREF_MEM == 0
693 pci_domain_read_resources(dev);
696 struct resource *resource;
697 for(link=dev->link_list; link; link = link->next) {
698 /* Initialize the system wide io space constraints */
699 resource = new_resource(dev, 0|(link->link_num<<2));
700 resource->base = 0x400;
701 resource->limit = 0xffffUL;
702 resource->flags = IORESOURCE_IO;
704 /* Initialize the system wide prefetchable memory resources constraints */
705 resource = new_resource(dev, 1|(link->link_num<<2));
706 resource->limit = 0xfcffffffffULL;
707 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
709 /* Initialize the system wide memory resources constraints */
710 resource = new_resource(dev, 2|(link->link_num<<2));
711 resource->limit = 0xfcffffffffULL;
712 resource->flags = IORESOURCE_MEM;
715 #if CONFIG_MMCONF_SUPPORT
716 struct resource *res = new_resource(dev, 0xc0010058);
717 res->base = CONFIG_MMCONF_BASE_ADDRESS;
718 res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
719 res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
720 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
724 static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
726 struct resource *min;
728 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
729 if (min && tolm > min->base) {
735 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
737 struct hw_mem_hole_info {
738 unsigned hole_startk;
742 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
744 struct hw_mem_hole_info mem_hole;
747 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
748 mem_hole.node_id = -1;
750 for (i = 0; i < sysconf.nodes; i++) {
751 struct dram_base_mask_t d;
753 d = get_dram_base_mask(i);
754 if(!(d.mask & 1)) continue; // no memory on this node
756 hole = pci_read_config32(__f1_dev[i], 0xf0);
757 if(hole & 1) { // we find the hole
758 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
759 mem_hole.node_id = i; // record the node No with hole
760 break; // only one hole
764 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
765 if(mem_hole.node_id==-1) {
766 resource_t limitk_pri = 0;
767 for(i=0; i<sysconf.nodes; i++) {
768 struct dram_base_mask_t d;
769 resource_t base_k, limit_k;
770 d = get_dram_base_mask(i);
771 if(!(d.base & 1)) continue;
773 base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
774 if(base_k > 4 *1024 * 1024) break; // don't need to go to check
775 if(limitk_pri != base_k) { // we find the hole
776 mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
777 mem_hole.node_id = i;
778 break; //only one hole
781 limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
782 limitk_pri = limit_k;
788 // WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
789 // Does it make sense not to?
790 #if CONFIG_AMDMCT == 0
791 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
795 struct dram_base_mask_t d;
802 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
803 struct mem_info *meminfo;
804 meminfo = &sysinfox->meminfo[node_id];
806 one_DCT = get_one_DCT(meminfo);
808 // 1. find which node has hole
809 // 2. change limit in that node.
810 // 3. change base and limit in later node
811 // 4. clear that node f0
813 // if there is not mem hole enabled, we need to change it's base instead
815 hole_sizek = (4*1024*1024) - hole_startk;
817 for(i=NODE_NUMS-1;i>node_id;i--) {
819 d = get_dram_base_mask(i);
821 if(!(d.mask & 1)) continue;
823 d.base -= (hole_sizek>>9);
824 d.mask -= (hole_sizek>>9);
825 set_dram_base_mask(i, d, sysconf.nodes);
827 if(get_DctSelHiEn(i) & 1) {
828 sel_m = get_DctSelBaseAddr(i);
829 sel_m -= hole_startk>>10;
830 set_DctSelBaseAddr(i, sel_m);
834 d = get_dram_base_mask(node_id);
835 dev = __f1_dev[node_id];
836 sel_hi_en = get_DctSelHiEn(node_id);
839 sel_m = get_DctSelBaseAddr(node_id);
841 hoist = pci_read_config32(dev, 0xf0);
843 pci_write_config32(dev, 0xf0, 0);
844 d.mask -= (hole_sizek>>9);
845 set_dram_base_mask(node_id, d, sysconf.nodes);
846 if(one_DCT || (sel_m >= (hole_startk>>10))) {
848 sel_m -= hole_startk>>10;
849 set_DctSelBaseAddr(node_id, sel_m);
853 set_DctSelBaseOffset(node_id, 0);
856 d.base -= (hole_sizek>>9);
857 d.mask -= (hole_sizek>>9);
858 set_dram_base_mask(node_id, d, sysconf.nodes);
861 sel_m -= hole_startk>>10;
862 set_DctSelBaseAddr(node_id, sel_m);
871 #if CONFIG_WRITE_HIGH_TABLES==1
875 #if CONFIG_GFXUMA == 1
876 extern uint64_t uma_memory_base, uma_memory_size;
878 static void add_uma_resource(struct device *dev, int index)
880 struct resource *resource;
882 printk(BIOS_DEBUG, "Adding UMA memory area\n");
883 resource = new_resource(dev, index);
884 resource->base = (resource_t) uma_memory_base;
885 resource->size = (resource_t) uma_memory_size;
886 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
887 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
891 static void amdfam10_domain_set_resources(device_t dev)
893 #if CONFIG_PCI_64BIT_PREF_MEM == 1
894 struct resource *io, *mem1, *mem2;
895 struct resource *res;
897 unsigned long mmio_basek;
901 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
902 struct hw_mem_hole_info mem_hole;
903 u32 reset_memhole = 1;
906 #if CONFIG_PCI_64BIT_PREF_MEM == 1
908 for(link = dev->link_list; link; link = link->next) {
909 /* Now reallocate the pci resources memory with the
910 * highest addresses I can manage.
912 mem1 = find_resource(dev, 1|(link->link_num<<2));
913 mem2 = find_resource(dev, 2|(link->link_num<<2));
915 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
916 mem1->base, mem1->limit, mem1->size, mem1->align);
917 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
918 mem2->base, mem2->limit, mem2->size, mem2->align);
920 /* See if both resources have roughly the same limits */
921 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
922 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
924 /* If so place the one with the most stringent alignment first
926 if (mem2->align > mem1->align) {
927 struct resource *tmp;
932 /* Now place the memory as high up as it will go */
933 mem2->base = resource_max(mem2);
934 mem1->limit = mem2->base - 1;
935 mem1->base = resource_max(mem1);
938 /* Place the resources as high up as they will go */
939 mem2->base = resource_max(mem2);
940 mem1->base = resource_max(mem1);
943 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
944 mem1->base, mem1->limit, mem1->size, mem1->align);
945 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
946 mem2->base, mem2->limit, mem2->size, mem2->align);
949 for(res = &dev->resource_list; res; res = res->next)
951 res->flags |= IORESOURCE_ASSIGNED;
952 res->flags |= IORESOURCE_STORED;
953 report_resource_stored(dev, res, "");
957 pci_tolm = 0xffffffffUL;
958 for(link = dev->link_list; link; link = link->next) {
959 pci_tolm = my_find_pci_tolm(link, pci_tolm);
962 // FIXME handle interleaved nodes. If you fix this here, please fix
964 mmio_basek = pci_tolm >> 10;
965 /* Round mmio_basek to something the processor can support */
966 mmio_basek &= ~((1 << 6) -1);
968 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
969 // MMIO hole. If you fix this here, please fix amdk8, too.
970 /* Round the mmio hole to 64M */
971 mmio_basek &= ~((64*1024) - 1);
973 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
974 /* if the hw mem hole is already set in raminit stage, here we will compare
975 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
976 * use hole_basek as mmio_basek and we don't need to reset hole.
977 * otherwise We reset the hole to the mmio_basek
980 mem_hole = get_hw_mem_hole_info();
982 // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
983 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
984 mmio_basek = mem_hole.hole_startk;
988 #if CONFIG_AMDMCT == 0
989 //mmio_basek = 3*1024*1024; // for debug to meet boundary
992 if(mem_hole.node_id!=-1) {
993 /* We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not
994 make hole_startk to some basek too!
995 We need to reset our Mem Hole, because We want more big HOLE
997 Before that We need to disable mem hole at first, becase
998 memhole could already be set on i+1 instead
1000 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
1003 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
1004 // We need to double check if the mmio_basek is valid for hole
1005 // setting, if it is equal to basek, we need to decrease it some
1006 resource_t basek_pri;
1007 for (i = 0; i < sysconf.nodes; i++) {
1008 struct dram_base_mask_t d;
1010 d = get_dram_base_mask(i);
1012 if(!(d.mask &1)) continue;
1014 basek = ((resource_t)(d.base & 0x1fffff00)) << 9;
1015 if(mmio_basek == (u32)basek) {
1016 mmio_basek -= (uin32_t)(basek - basek_pri); // increase mem hole size to make sure it is on middle of pri node
1029 for(i = 0; i < sysconf.nodes; i++) {
1030 struct dram_base_mask_t d;
1031 resource_t basek, limitk, sizek; // 4 1T
1032 d = get_dram_base_mask(i);
1034 if(!(d.mask & 1)) continue;
1035 basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
1036 limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ;
1037 sizek = limitk - basek;
1039 /* see if we need a hole from 0xa0000 to 0xbffff */
1040 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1041 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1043 basek = (8*64)+(16*16);
1044 sizek = limitk - ((8*64)+(16*16));
1048 // printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
1050 /* split the region to accomodate pci memory space */
1051 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1052 if (basek <= mmio_basek) {
1054 pre_sizek = mmio_basek - basek;
1056 ram_resource(dev, (idx | i), basek, pre_sizek);
1059 #if CONFIG_WRITE_HIGH_TABLES==1
1060 if (high_tables_base==0) {
1061 /* Leave some space for ACPI, PIRQ and MP tables */
1062 #if CONFIG_GFXUMA == 1
1063 high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
1065 high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
1067 high_tables_size = HIGH_MEMORY_SIZE;
1068 printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
1069 HIGH_MEMORY_SIZE / 1024, high_tables_base);
1073 #if CONFIG_AMDMCT == 0
1074 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1076 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
1077 struct mem_info *meminfo;
1078 meminfo = &sysinfox->meminfo[i];
1079 sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes);
1086 if ((basek + sizek) <= 4*1024*1024) {
1090 basek = 4*1024*1024;
1091 sizek -= (4*1024*1024 - mmio_basek);
1095 #if CONFIG_GFXUMA == 1
1096 /* Deduct uma memory before reporting because
1097 * this is what the mtrr code expects */
1098 sizek -= uma_memory_size / 1024;
1100 ram_resource(dev, (idx | i), basek, sizek);
1102 #if CONFIG_WRITE_HIGH_TABLES==1
1103 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
1104 i, mmio_basek, basek, limitk);
1105 if (high_tables_base==0) {
1106 /* Leave some space for ACPI, PIRQ and MP tables */
1107 #if CONFIG_GFXUMA == 1
1108 high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
1110 high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
1112 high_tables_size = HIGH_MEMORY_SIZE;
1117 #if CONFIG_GFXUMA == 1
1118 add_uma_resource(dev, 7);
1121 for(link = dev->link_list; link; link = link->next) {
1122 if (link->children) {
1123 assign_resources(link);
1128 static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
1133 /* Unmap all of the HT chains */
1134 for(reg = 0xe0; reg <= 0xec; reg += 4) {
1135 f1_write_config32(reg, 0);
1137 #if CONFIG_EXT_CONF_SUPPORT == 1
1139 for(i = 0; i< sysconf.nodes; i++) {
1141 for(index = 0; index < 64; index++) {
1142 pci_write_config32(__f1_dev[i], 0x110, index | (6<<28));
1143 pci_write_config32(__f1_dev[i], 0x114, 0);
1150 for(link = dev->link_list; link; link = link->next) {
1151 max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max);
1154 /* Tune the hypertransport transaction for best performance.
1155 * Including enabling relaxed ordering if it is safe.
1158 for(i = 0; i < fx_devs; i++) {
1160 f0_dev = __f0_dev[i];
1161 if (f0_dev && f0_dev->enabled) {
1163 httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1164 httc &= ~HTTC_RSP_PASS_PW;
1165 if (!dev->link_list->disable_relaxed_ordering) {
1166 httc |= HTTC_RSP_PASS_PW;
1168 printk(BIOS_SPEW, "%s passpw: %s\n",
1170 (!dev->link_list->disable_relaxed_ordering)?
1171 "enabled":"disabled");
1172 pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1178 static struct device_operations pci_domain_ops = {
1179 .read_resources = amdfam10_domain_read_resources,
1180 .set_resources = amdfam10_domain_set_resources,
1181 .enable_resources = NULL,
1183 .scan_bus = amdfam10_domain_scan_bus,
1184 #if CONFIG_MMCONF_SUPPORT_DEFAULT
1185 .ops_pci_bus = &pci_ops_mmconf,
1187 .ops_pci_bus = &pci_cf8_conf1,
1191 static void sysconf_init(device_t dev) // first node
1193 sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
1195 sysconf.ht_c_num = 0;
1197 unsigned ht_c_index;
1199 for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
1200 sysconf.ht_c_conf_bus[ht_c_index] = 0;
1203 sysconf.nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
1204 #if CONFIG_MAX_PHYSICAL_CPUS > 8
1205 sysconf.nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
1208 sysconf.enabled_apic_ext_id = 0;
1209 sysconf.lift_bsp_apicid = 0;
1211 /* Find the bootstrap processors apicid */
1212 sysconf.bsp_apicid = lapicid();
1213 sysconf.apicid_offset = sysconf.bsp_apicid;
1215 #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
1216 if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1218 sysconf.enabled_apic_ext_id = 1;
1220 #if (CONFIG_APIC_ID_OFFSET>0)
1221 if(sysconf.enabled_apic_ext_id) {
1222 if(sysconf.bsp_apicid == 0) {
1223 /* bsp apic id is not changed */
1224 sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
1226 sysconf.lift_bsp_apicid = 1;
1233 static void add_more_links(device_t dev, unsigned total_links)
1235 struct bus *link, *last = NULL;
1238 for (link = dev->link_list; link; link = link->next)
1242 int links = total_links - last->link_num;
1243 link_num = last->link_num;
1245 link = malloc(links*sizeof(*link));
1247 die("Couldn't allocate more links!\n");
1248 memset(link, 0, links*sizeof(*link));
1254 link = malloc(total_links*sizeof(*link));
1255 memset(link, 0, total_links*sizeof(*link));
1256 dev->link_list = link;
1259 for (link_num = link_num + 1; link_num < total_links; link_num++) {
1260 link->link_num = link_num;
1262 link->next = link + 1;
1269 static u32 cpu_bus_scan(device_t dev, u32 max)
1271 struct bus *cpu_bus;
1274 device_t pci_domain;
1281 int disable_siblings;
1282 unsigned ApicIdCoreIdSize;
1284 printk(BIOS_INFO, "%s: starting...\n", __func__);
1286 ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
1287 if(ApicIdCoreIdSize) {
1288 siblings = (1<<ApicIdCoreIdSize)-1;
1290 siblings = 3; //quad core
1293 disable_siblings = !CONFIG_LOGICAL_CPUS;
1294 #if CONFIG_LOGICAL_CPUS == 1
1295 get_option(&disable_siblings, "multi_core");
1298 // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
1299 nb_cfg_54 = read_nb_cfg_54();
1302 dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
1303 if(dev_mc && dev_mc->bus) {
1304 printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
1305 pci_domain = dev_mc->bus->dev;
1306 if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
1307 printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
1308 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
1309 printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
1312 printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
1314 printk(BIOS_DEBUG, "\n");
1316 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
1318 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1319 if (dev_mc && dev_mc->bus) {
1320 printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
1321 pci_domain = dev_mc->bus->dev;
1322 if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
1323 if((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
1324 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
1325 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
1326 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
1328 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
1329 dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
1330 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
1331 dev_mc = dev_mc->sibling;
1340 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
1342 printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
1346 sysconf_init(dev_mc);
1348 nodes = sysconf.nodes;
1350 #if CONFIG_CBB && (NODE_NUMS > 32)
1351 if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe
1352 if(pci_domain->link_list && !pci_domain->link_list->next) {
1353 struct bus *new_link = new_link(pci_domain);
1354 pci_domain->link_list->next = new_link;
1355 new_link->link_num = 1;
1356 new_link->dev = pci_domain;
1357 new_link->children = 0;
1358 printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
1360 pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
1363 /* Find which cpus are present */
1364 cpu_bus = dev->link_list;
1365 for(i = 0; i < nodes; i++) {
1366 device_t cdb_dev, cpu;
1367 struct device_path cpu_path;
1368 unsigned busn, devn;
1372 devn = CONFIG_CDB+i;
1374 #if CONFIG_CBB && (NODE_NUMS > 32)
1378 pbus = pci_domain->link_list->next);
1382 /* Find the cpu's pci device */
1383 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1385 /* If I am probing things in a weird order
1386 * ensure all of the cpu's pci devices are found.
1389 for(fn = 0; fn <= 5; fn++) { //FBDIMM?
1390 cdb_dev = pci_probe_dev(NULL, pbus,
1391 PCI_DEVFN(devn, fn));
1393 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1396 /* Ok, We need to set the links for that device.
1397 * otherwise the device under it will not be scanned
1400 #if CONFIG_HT3_SUPPORT==1
1405 add_more_links(cdb_dev, linknum);
1408 cores_found = 0; // one core
1409 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
1410 if (cdb_dev && cdb_dev->enabled) {
1411 j = pci_read_config32(cdb_dev, 0xe8);
1412 cores_found = (j >> 12) & 3; // dev is func 3
1414 cores_found |= (j >> 13) & 4;
1415 printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found);
1419 if(disable_siblings) {
1426 for (j = 0; j <=jj; j++ ) {
1428 /* Build the cpu device path */
1429 cpu_path.type = DEVICE_PATH_APIC;
1430 cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ?
1432 /* See if I can find the cpu */
1433 cpu = find_dev_path(cpu_bus, &cpu_path);
1435 /* Enable the cpu if I have the processor */
1436 if (cdb_dev && cdb_dev->enabled) {
1438 cpu = alloc_dev(cpu_bus, &cpu_path);
1445 /* Disable the cpu if I don't have the processor */
1446 if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
1450 /* Report what I have done */
1452 cpu->path.apic.node_id = i;
1453 cpu->path.apic.core_id = j;
1454 #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0)
1455 if(sysconf.enabled_apic_ext_id) {
1456 if(sysconf.lift_bsp_apicid) {
1457 cpu->path.apic.apic_id += sysconf.apicid_offset;
1460 if (cpu->path.apic.apic_id != 0)
1461 cpu->path.apic.apic_id += sysconf.apicid_offset;
1465 printk(BIOS_DEBUG, "CPU: %s %s\n",
1466 dev_path(cpu), cpu->enabled?"enabled":"disabled");
1471 printk(BIOS_INFO, "%s: done.\n", __func__);
1475 static void cpu_bus_init(device_t dev)
1477 initialize_cpus(dev->link_list);
1478 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 || CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
1479 sb_After_Pci_Init();
1484 static void cpu_bus_noop(device_t dev)
1488 static void cpu_bus_read_resources(device_t dev)
1492 static void cpu_bus_set_resources(device_t dev)
1494 struct resource *resource = find_resource(dev, 0xc0010058);
1496 report_resource_stored(dev, resource, " <mmconfig>");
1498 pci_dev_set_resources(dev);
1501 static struct device_operations cpu_bus_ops = {
1502 .read_resources = cpu_bus_read_resources,
1503 .set_resources = cpu_bus_set_resources,
1504 .enable_resources = cpu_bus_noop,
1505 .init = cpu_bus_init,
1506 .scan_bus = cpu_bus_scan,
1509 static void root_complex_enable_dev(struct device *dev)
1511 /* Set the operations if it is a special bus type */
1512 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1513 dev->ops = &pci_domain_ops;
1515 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1516 dev->ops = &cpu_bus_ops;
1520 struct chip_operations northbridge_amd_amdfam10_root_complex_ops = {
1521 CHIP_NAME("AMD FAM10 Root Complex")
1522 .enable_dev = root_complex_enable_dev,