2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * Part of this file is from cx700 port, part of is from cn700 port,
22 * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch.
25 #define RAMINIT_SYSINFO 1
26 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
29 #include <device/pci_def.h>
30 #include <device/pci_ids.h>
32 #include <device/pnp_def.h>
33 #include <arch/romcc_io.h>
35 #include "pc80/serial.c"
36 #include "console/console.c"
37 #include "lib/ramtest.c"
38 #include "northbridge/via/vx800/vx800.h"
39 #include "cpu/x86/mtrr/earlymtrr.c"
40 #include "cpu/x86/bist.h"
41 #include "pc80/udelay_io.c"
42 #include "lib/delay.c"
44 #include "cpu/x86/lapic/boot_cpu.c"
46 /* This file contains the board-special SI value for raminit.c. */
47 #include "driving_clk_phase_data.c"
49 #include "northbridge/via/vx800/raminit.h"
50 #include "northbridge/via/vx800/raminit.c"
51 #include "cpu/x86/car/copy_and_run.c"
54 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
56 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
59 * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
60 * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
62 void jason_tsc_count_car(void)
65 unsigned long long start;
66 asm volatile ("rdtsc" : "=A" (start));
68 print_emerg("jason_tsc_count_car= ");
69 print_emerg_hex32((unsigned long) start);
74 int acpi_is_wakeup_early_via_vx800(void)
79 print_debug("In acpi_is_wakeup_early_via_vx800\r\n");
80 /* Power management controller */
81 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
82 PCI_DEVICE_ID_VIA_VX855_LPC), 0);
84 if (dev == PCI_DEV_INVALID)
85 die("Power management controller not found\r\n");
87 /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
88 pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
90 /* Enable ACPI accessm RTC signal gated with PSON. */
91 pci_write_config8(dev, 0x81, 0x84);
93 tmp = inw(VX800_ACPI_IO_BASE + 0x04);
94 result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
95 print_debug(" boot_mode=");
96 print_debug_hex16(result);
101 static inline int spd_read_byte(unsigned device, unsigned address)
103 return smbus_read_byte(device, address);
106 /* All content of this function came from the cx700 port of coreboot. */
107 static void enable_mainboard_devices(void)
114 * Add and close this switch, since some line cause error, some
115 * written at elsewhere (stage1 stage2).
118 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
119 PCI_DEVICE_ID_VIA_VX855_LPC), 0);
122 pci_write_config8(dev, 0x98, 0x00);
124 pci_write_config8(dev, 0x50, 0x80); /* Disable mc97. */
127 * Martin: Disable internal KBC configuration.
129 * Internal Config is needed to decide which key can be pressed to
132 pci_write_config8(dev, 0x51, 0x2d);
134 /* This causes irq0 can not be triggerd, since bit 5 was set to 0. */
135 /* pci_write_config8(dev, 0x58, 0x42); */
137 /* These writing may... TODO */
138 regdata = pci_read_config8(dev, 0x58);
140 pci_write_config8(dev, 0x58, regdata);
141 pci_write_config8(dev, 0x59, 0x80);
142 pci_write_config8(dev, 0x5b, 0x01);
145 print_debug("In enable_mainboard_devices \r\n");
147 /* Enable P2P Bridge Header for external PCI bus. */
148 dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
149 pci_write_config8(dev, 0x4f, 0x41);
152 * "5324" already is the default value of the PCI IDE device, cancel
155 * [william 20080124]: Fix bug that can not boot Ubuntu at the
160 dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0);
161 values = pci_read_config16(dev, 0xBA);
164 pci_write_config16(dev, 0xBA, values);
169 * Most content of this function came from the cx700 port of coreboot.
170 * Turn on the shadow of E-seg.
172 static void enable_shadow_ram(void)
177 * Changed the value from 0x2a to 0x3f. "read only" may block "write"?
178 * and maybe in C-seg "write" will be needed?
180 pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
182 /* 0xf0000-0xfffff - ACPI tables */
183 shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
185 pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
187 /* 0xe0000-0xeffff - elfload? */
189 * In s3 resume process, wakeup.c, I use E-seg to hold the code
190 * (which can not locate in the area to be covered) that will copy
191 * 0-A-seg and F-seg from TOP-mem back to their normal location.
193 pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff);
196 /* Enable shadow RAM as normal DRAM */
197 /* 0xc0000-0xcffff - VGA BIOS */
198 pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
199 pci_write_config8(PCI_DEV(0, 0, 7), 0x61, 0x00);
200 /* 0xd0000-0xdffff - ?? */
201 /* pci_write_config8(PCI_DEV(0, 0, 3), 0x81, 0xff); */
202 /* pci_write_config8(PCI_DEV(0, 0, 7), 0x62, 0xff); */
204 /* Do it again for the vlink controller. */
205 shadowreg = pci_read_config8(PCI_DEV(0, 0, 7), 0x63);
207 pci_write_config8(PCI_DEV(0, 0, 7), 0x63, shadowreg);
212 * Added this table 2008-11-28.
213 * This table contains the value needed to be set before begin to init DRAM.
214 * Note: REV_Bx should be checked for changes when porting a new board!
216 static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
217 /* VT3409 no PCI-E */
218 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range
219 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie
220 // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
221 // Set ROMSIP value by software
224 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3
225 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
226 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3
227 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
228 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl
229 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl
230 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit
231 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status
232 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset
233 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset
234 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status
235 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status
236 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group
237 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group
238 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group
239 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
240 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
241 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
242 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
243 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
244 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1
245 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2
246 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB
247 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD
248 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0)
249 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1)
250 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2)
251 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3)
254 // CPU Host Bus Control
255 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
256 // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
257 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
258 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance
259 // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
260 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
261 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access
262 // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2
263 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2
264 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1
265 // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
266 // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2
267 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy
268 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer
269 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl
270 // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3
271 // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2
272 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2
273 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3
274 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4
276 // Set APIC and SMRAM
277 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control
278 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
279 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table
282 #define USE_VCP 1 /* 0 means "use DVP". */
286 #define gCom1Base 0x3f8
287 #define gCom2Base 0x2f8
289 void EmbedComInit(void)
294 /* Enable NB multiple function control. */
295 ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f);
296 ByteVal = ByteVal | 0x01;
297 pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal);
300 ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1);
301 ByteVal = ByteVal | 0x80;
302 pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal);
304 ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7);
305 ByteVal = ByteVal | 0x08;
306 pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal);
308 /* Enable P2P IO/mem. */
309 ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4);
310 ByteVal = ByteVal | 0x07;
311 pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal);
313 /* Turn on graphic chip I/O port port access. */
314 ByteVal = inb(0x3C3);
315 ByteVal = ByteVal | 0x01;
316 outb(ByteVal, 0x3C3);
318 /* Turn off graphic chip register protection. */
320 ByteVal = inb(0x3C5);
321 ByteVal = ByteVal | 0x01;
322 outb(ByteVal, 0x3C5);
324 /* South module pad share enable 0x3C5.78[7]. */
326 ByteVal = inb(0x3C5);
327 ByteVal = ByteVal | 0x80;
328 outb(ByteVal, 0x3C5);
330 /* Enable UART function multiplex with DVP or VCP pad D17F0Rx46[7,6]. */
331 ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46);
333 ByteVal = (ByteVal & 0x3F) | 0x40; /* Multiplex with VCP. */
335 ByteVal = (ByteVal & 0x3F) | 0xC0; /* Multiplex with DVP. */
336 pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal);
338 /* Enable embedded COM1 and COM2 D17F0RxB0[5,4]. */
339 ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0);
340 ByteVal = ByteVal & 0xcf;
341 /* Multiplex with VCP. */
343 ByteVal = ByteVal | 0x10;
345 ByteVal = ByteVal | 0x20;
346 pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal);
355 /* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */
357 ByteVal = (u8) ((gCom1Base >> 3) | 0x80);
358 pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal);
359 ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
360 ByteVal = (ByteVal & 0xf0) | 0x04;
361 pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
364 /* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */
366 ByteVal = (u8) ((gCom2Base >> 3) | 0x80);
367 pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal);
368 ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
369 ByteVal = (ByteVal & 0x0f) | 0x30;
370 pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
372 /* No port 80 biger then 0x10. */
374 /* Disable interrupt. */
375 ByteVal = inb(ComBase + 3);
376 outb(ByteVal & 0x7F, ComBase + 3);
377 outb(0x00, ComBase + 1);
380 ByteVal = inb(ComBase + 3);
381 outb(ByteVal | 0x80, ComBase + 3);
383 outb(0x00, ComBase + 1);
385 /* Set frame format. */
386 ByteVal = inb(ComBase + 3);
387 outb(ByteVal & 0x3F, ComBase + 3);
388 outb(0x03, ComBase + 3);
389 outb(0x00, ComBase + 2);
390 outb(0x00, ComBase + 4);
392 /* SOutput("Embedded COM output\n"); */
396 /* cache_as_ram.inc jumps to here. */
397 void amd64_main(unsigned long bist)
399 unsigned cpu_reset = 0;
401 u8 rambits, Data8, Data;
406 * Enable multifunction for northbridge. These 4 lines (until
407 * console_init()) are the same with epia-cn port.
409 pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
410 /* EmbedComInit(); */
411 w83697hf_set_clksel_48(SERIAL_DEV);
412 w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
414 /* enable_vx800_serial(); */
434 jason_tsc_count_car();
436 pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA,
437 PCI_DEVICE_ID_VIA_VX855_IDE);
438 pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE,
439 PCI_DEVICE_ID_VIA_VX855_IDE);
440 pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA);
441 pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2,
442 PCI_DEVICE_ID_VIA_VX855_LPC);
443 Data8 = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79);
446 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8);
447 pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72,
448 PCI_DEVICE_ID_VIA_VX855_LPC);
451 * There are two function definitions of console_init(), while the
452 * src/arch/i386/lib is the right one.
456 /* Decide if this is a s3 wakeup or a normal boot. */
457 boot_mode = acpi_is_wakeup_early_via_vx800();
460 * 2008-11-27 Add this, to transfer "cpu restart" to "cold boot".
461 * When this boot is not a S3 resume, and PCI registers had been
462 * written, then this must be a CPU restart (result of OS reboot cmd),
463 * so we need a real "cold boot".
465 jason_tsc_count_car();
467 && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
471 /* x86 cold boot I/O cmd. */
472 /* These 2 lines are the same with epia-cn port. */
474 jason_tsc_count_car();
476 /* This fix does help vx800!, but vx855 doesn't need this. */
477 /* smbus_fixup(&ctrl); */
481 * CAR needs MTRR until memory is ok, so disable this
482 * early_mtrr_init() call.
485 print_debug("doing early_mtrr\r\n");
490 /* Halt if there was a built-in self test failure. */
491 report_bist_failure(bist);
493 print_debug("Enabling mainboard devices\r\n");
494 enable_mainboard_devices();
497 * Get NB chip revision from D0F4RxF6, revision will be used in
500 device = PCI_DEV(0, 0, 4);
501 Data = pci_read_config8(device, 0xf6);
502 print_debug("NB chip revision =");
503 print_debug_hex8(Data);
506 /* Make NB ready before DRAM init. */
507 via_pci_inittable(Data, mNbStage1InitTbl);
510 * When resume from s3, DRAM init is skipped, so need to recovery
511 * any PCI register related to DRAM init. d0f3 didn't lose its power
512 * during whole s3 time, so any register not belonging to d0f3 needs
516 if (boot_mode == 3) {
518 u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
519 DRAM_SYS_ATTR DramAttr;
521 print_debug("This is an S3 wakeup\r\n");
523 memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
525 * Step 1: DRAM detection; DDR1 or DDR2; Get SPD Data;
526 * Rank Presence; 64 or 128bit; Unbuffered or registered;
529 DRAMDetect(&DramAttr);
532 * Begin to get RAM size, 43,42 41 40 contains the end
533 * address of last rank in DDR2 slot.
535 device = PCI_DEV(0, 0, 3);
536 for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
537 rambits = pci_read_config8(device, ramregs[i]);
542 DRAMDRDYSetting(&DramAttr);
544 Data = 0x80; /* This value is same with DevInit.c. */
545 pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data);
546 pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2);
547 Data = pci_read_config8(MEMCTRL, 0x88);
548 pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data);
550 /* Just copy this function from draminit to here! */
551 DRAMRegFinalValue(&DramAttr);
553 /* Just copy this function from draminit to here! */
556 print_debug("Resume from S3, RAM init was ignored\r\n");
559 ram_check(0, 640 * 1024);
563 /* ddr2_ram_setup(); */
564 /* This line is the same with cx700 port. */
567 jason_tsc_count_car();
570 * For coreboot most time of S3 resume is the same as normal boot,
571 * so some memory area under 1M become dirty, so before this happen,
572 * I need to backup the content of mem to top-mem.
574 * I will reserve the 1M top-men in LBIO table in coreboot_table.c
575 * and recovery the content of 1M-mem in wakeup.c.
577 #if PAYLOAD_IS_SEABIOS == 1
578 if (boot_mode == 3) {
579 /* An idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
581 * I want move the 1M data, I have to set some MTRRs myself.
582 * Setting MTRR before back memory save s3 resume time about
585 * !!! Since CAR stack uses cache, and we are using cache
586 * here, we must be careful:
588 * 1. during this MTRR code, must no function call (after
589 * this MTRR, I think it should be OK to use function).
590 * 2. Before stack switch, no use variable that have value
592 * 3. Due to 2, take care of "cpu_reset", I directlly set it
595 u32 memtop = *(u32 *) WAKE_MEM_INFO;
596 u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000;
597 u32 memtop2 = *(u32 *) WAKE_MEM_INFO - 0x200000;
598 u32 memtop3 = *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000;
600 *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + 0xe0000;
603 "movl $0x204, %%ecx\n\t"
604 "xorl %%edx, %%edx\n\t"
606 "orl $(0 | 6), %%eax\n\t"
609 "movl $0x205, %%ecx\n\t"
610 "xorl %%edx, %%edx\n\t"
611 "movl $0x100000,%%eax\n\t"
614 "orl $(0 | 0x800), %%eax\n\t"
620 "movl $0x206, %%ecx\n\t"
621 "xorl %%edx, %%edx\n\t"
623 "orl $(0 | 6), %%eax\n\t"
626 "movl $0x207, %%ecx\n\t"
627 "xorl %%edx, %%edx\n\t"
628 "movl $0x100000,%%eax\n\t"
631 "orl $(0 | 0x800), %%eax\n\t"
637 "movl $0x208, %ecx\n\t"
638 "xorl %edx, %edx\n\t"
640 "orl $(0 | 6), %eax\n\t"
643 "movl $0x209, %ecx\n\t"
644 "xorl %edx, %edx\n\t"
645 "movl $0x100000,%eax\n\t"
648 "orl $(0 | 0x800), %eax\n\t"
654 * WAKE_MEM_INFO is inited in get_set_top_available_mem()
655 * in tables.c these two memcpy() not not be enabled if set
656 * the MTRR around this two lines.
662 "movl $0xa0000, %%ecx\n\t"
669 "movl $0xe0000, %%esi\n\t"
671 "movl $0x20000, %%ecx\n\t"
677 /* This can have function call, because no variable used before this. */
678 print_debug("Copy memory to high memory to protect s3 wakeup vector code \r\n");
679 memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
680 0x100000), (unsigned char *)0, 0xa0000);
681 memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
682 0x100000 + 0xe0000), (unsigned char *)0xe0000, 0x20000);
684 /* Restore the MTRR previously modified. */
688 "xorl %edx, %edx\n\t"
689 "xorl %eax, %eax\n\t"
690 "movl $0x204, %ecx\n\t"
692 "movl $0x205, %ecx\n\t"
694 "movl $0x206, %ecx\n\t"
696 "movl $0x207, %ecx\n\t"
698 "movl $0x208, %ecx\n\t"
700 "movl $0x209, %ecx\n\t"
709 * The following code is copied from tyan\s2735\romstage.c.
710 * Only the code around CLEAR_FIRST_1M_RAM is changed. Removed all the code
711 * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c".
712 * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop
713 * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my
714 * $CONFIG_XIP_ROM_BASE+SIZE area.
716 * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have
717 * some diff with x86-version.
722 * Check value of esp to verify if we have enough ROM for
723 * stack in Cache as RAM.
726 __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
727 #if CONFIG_USE_PRINTK_IN_CAR
728 printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
730 print_debug("v_esp=");
731 print_debug_hex32(v_esp);
740 /* It seems that cpu_reset is not used before this, so I just reset
741 * it, (this is because the s3 resume, setting in MTRR and copy data
746 #if CONFIG_USE_PRINTK_IN_CAR
747 printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
749 print_debug("cpu_reset = ");
750 print_debug_hex32(cpu_reset);
755 print_debug("Clearing initial memory region: ");
756 print_debug("No cache as ram now - ");
758 /* Store cpu_reset to ebx. */
759 __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset));
762 * Cancel these lines, CLEAR_FIRST_1M_RAM cause the
763 * cpu/x86/car/cache_as_ram_post.c stop at somewhere.
766 if (cpu_reset == 0) {
767 #define CLEAR_FIRST_1M_RAM 1
768 #include "cpu/via/car/cache_as_ram_post.c"
770 #undef CLEAR_FIRST_1M_RAM
771 #include "cpu/via/car/cache_as_ram_post.c"
775 #include "cpu/via/car/cache_as_ram_post.c"
776 /* #include "cpu/x86/car/cache_as_ram_post.c" */
778 /* Set new esp *//* before CONFIG_RAMBASE */
780 "subl %0, %%esp\n\t"::
781 "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_RAMBASE)
785 unsigned new_cpu_reset;
787 /* Get back cpu_reset from ebx. */
788 __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset));
790 /* We can't go back anymore, we lost old stack data in CAR. */
791 if (new_cpu_reset == 0)
792 print_debug("Use Ram as Stack now - done\r\n");
794 print_debug("Use Ram as Stack now - \r\n");
796 #if CONFIG_USE_PRINTK_IN_CAR
797 printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
799 print_debug("new_cpu_reset = ");
800 print_debug_hex32(new_cpu_reset);
804 jason_tsc_count_car();
805 /* Copy and execute coreboot_ram. */
806 copy_and_run(new_cpu_reset);
807 /* We will not return. */
811 print_debug("should not be here -\r\n");